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 

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SLLS206J − MAY 1995 − REVISED NOVEMBER 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D Single Chip With Easy Interface Between

UART and Serial-Port Connector of IBM

PC/AT and Compatibles

D Meet or Exceed the Requirements of

TIA/EIA-232-F and ITU v.28 Standards

D Designed to Support Data Rates up to

120 kbit/s

D Pinout Compatible With SN75C185 and

SN75185

description/ordering information

The GD65232 and GD75232 combine three

drivers and five receivers from the

Texas Instruments trade-standard SN75188 and

SN75189 bipolar quadruple drivers and receivers, respectively. The pinout matches the flow-through design

of the SN75C185 to decrease the part count, reduce the board space required, and allow easy interconnection

of the UART and serial-port connector of an IBM PC/AT and compatibles. The bipolar circuits and processing

of the GD65232 and GD75232 provide a rugged, low-cost solution for this function at the expense of quiescent

power and external passive components relative to the SN75C185.

The GD65232 and GD75232 comply with the requirements of the TIA/EIA-232-F and ITU (formerly CCITT) V.28

standards. These standards are for data interchange between a host computer and a peripheral at signaling

rates up to 20 kbit/s. The switching speeds of these devices are fast enough to support rates up to 120 kbit/s

with lower capacitive loads (shorter cables). Interoperability at the higher signaling rates cannot be expected

unless the designer has design control of the cable and the interface circuits at both ends. For interoperability

at signaling rates up to 120 kbit/s, use of TIA/EIA-423-B (ITU V.10) and TIA/EIA-422-B (ITU V.11) standards

is recommended.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP (N) Tube of 20 GD65232N GD65232N

SOIC (DW)

Tube of 25 GD65232DW

GD65232

−40°C to 85°C

SOIC (DW)

Reel of 2000 GD65232DWR

GD65232

−40°C to 85°C

SSOP (DB) Reel of 2000 GD65232DBR GD65232

TSSOP (PW)

Tube of 70 GD65232PW

GD65232

TSSOP (PW)

Reel of 2000 GD65232PWR

GD65232

PDIP (N) Tube of 20 GD75232N GD75232N

SOIC (DW)

Tube of 25 GD75232DW

GD75232

0°C to 70°C

SOIC (DW)

Reel of 2000 GD75232DWR

GD75232

0°C to 70°C

SSOP (DB) Reel of 2000 GD75232DBR GD75232

TSSOP (PW)

Tube of 70 GD75232PW

GD75232

TSSOP (PW)

Reel of 2000 GD75232PWR

GD75232

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

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

RA1

RA2

RA3

DY1

DY2

RA4

DY3

RA5

RY1

RY2

RY3

DA1

DA2

RY4

DA3

RY5

GND

GD65232, GD75232 . . . DB, DW, N, OR PW PACKAGE

(TOP VIEW)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

IBM is a trademark of International Business Machines Corporation.

Summary of content (23 pages)

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SLLS206J − MAY 1995 − REVISED NOVEMBER 2004 D Single Chip With Easy Interface Between D D D GD65232, GD75232 . . . DB, DW, N, OR PW PACKAGE (TOP VIEW) UART and Serial-Port Connector of IBM PC/AT and Compatibles Meet or Exceed the Requirements of TIA/EIA-232-F and ITU v.
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SLLS206J − MAY 1995 − REVISED NOVEMBER 2004 logic diagram (positive logic) RA1 RA2 RA3 DY1 DY2 RA4 DY3 RA5 2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 RY1 RY2 RY3 DA1 DA2 RY4 DA3 RY5 schematic (each driver) To Other Drivers VDD 11.6 kΩ 9.4 kΩ Input DAx 75.8 Ω 320 Ω 4.2 kΩ GND To Other Drivers 10.4 kΩ 3.3 kΩ VSS To Other Drivers Resistor values shown are nominal. 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 68.
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SLLS206J − MAY 1995 − REVISED NOVEMBER 2004 schematic (each receiver) To Other Receivers VCC 9 kΩ 5 kΩ 1.66 kΩ Output RYx 2 kΩ Input RAx 3.8 kΩ 10 kΩ GND To Other Receivers Resistor values shown are nominal. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage (see Note 1): VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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SLLS206J − MAY 1995 − REVISED NOVEMBER 2004 recommended operating conditions MIN NOM MAX VDD VSS Supply voltage (see Note 4) 7.5 9 15 UNIT V Supply voltage (see Note 4) −7.5 −9 −15 V VCC VIH Supply voltage (see Note 4) 4.5 5 5.5 V High-level input voltage (driver only) 1.9 VIL Low-level input voltage (driver only) IOH High-level output current IOL Low-level output current TA Operating free-air temperature V 0.
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SLLS206J − MAY 1995 − REVISED NOVEMBER 2004 DRIVER SECTION electrical characteristics over recommended operating free-air temperature range, VDD = 9 V, VSS = −9 V, VCC = 5 V (unless otherwise noted) PARAMETER VOH VOL High-level output voltage IIH IIL High-level input current IOS(H) IOS(L) ro TEST CONDITIONS MIN MAX RL = 3 kΩ, See Figure 1 RL = 3 kΩ, See Figure 1 VI = 5 V, VI = 0, See Figure 2 10 µA Low-level input current See Figure 2
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SLLS206J − MAY 1995 − REVISED NOVEMBER 2004 RECEIVER SECTION electrical characteristics over recommended operating conditions (unless otherwise noted) PARAMETER MIN TYP† MAX See Figure 5 1.75 1.9 2.3 See Figure 5 1.55 TEST CONDITIONS TA = 25°C, TA = 0°C to 70°C, VIT+ Positive-going input threshold voltage VIT− Vhys Negative-going input threshold voltage 0.75 Input hysteresis voltage (VIT+ − VIT−) 0.
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SLLS206J − MAY 1995 − REVISED NOVEMBER 2004 PARAMETER MEASUREMENT INFORMATION IOS(L) VDD VDD or GND VCC −IOS(H) VSS or GND VI VO RL = 3 kΩ VSS Figure 1. Driver Test Circuit for VOH, VOL, IOS(H), and IOS(L) VDD VCC IIH VI −IIL VI VSS Figure 2. Driver Test Circuit for IIH and IIL 3V Input VDD Input V CC 1.5 V 1.
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SLLS206J − MAY 1995 − REVISED NOVEMBER 2004 PARAMETER MEASUREMENT INFORMATION VDD VCC VI VSS Figure 4. Receiver Test Circuit for IOS VDD VCC −IOH VOH VIT, VI VOL IOL VSS Figure 5. Receiver Test Circuit for VIT, VOH, and VOL 4V Input VDD Input V CC 50% 50% 0V tPHL Pulse Generator RL See Note A CL (see Note B) 90% Output VSS 50% 10% tPLH 50% 10% tTHL TEST CIRCUIT VOLTAGE WAVEFORMS NOTES: A.
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SLLS206J − MAY 1995 − REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS DRIVER SECTION OUTPUT CURRENT vs OUTPUT VOLTAGE ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ VOLTAGE TRANSFER CHARACTERISTICS 12 9 12 IO − Output Current − mA VO − Output Voltage − V 16 VDD = 9 V, VSS = −9 V 6 VDD = 6 V, VSS = −6 V 3 0 −3 −6 −9 ÎÎÎÎ ÎÎÎÎ 0 0.2 0.4 0.6 VDD = 9 V VSS = −9 V TA = 25°C 4 0 −4 1 1.2 1.4 1.6 1.
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SLLS206J − MAY 1995 − REVISED NOVEMBER 2004 TYPICAL CHARACTERISTICS 2.4 2 2.2 1.8 2 V IT − Input Threshold Voltage − V V IT − Input Threshold Voltage − V INPUT THRESHOLD VOLTAGE vs FREE-AIR TEMPERATURE VIT+ 1.8 1.6 1.4 1.2 1 VIT− 0.8 0.6 INPUT THRESHOLD VOLTAGE vs SUPPLY VOLTAGE VIT+ 1.6 1.4 1.2 1 VIT− 0.8 0.6 0.4 0.2 0.
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SLLS206J − MAY 1995 − REVISED NOVEMBER 2004 APPLICATION INFORMATION Diodes placed in series with the VDD and VSS leads protect the GD65232 and GD75232 in the fault condition in which the device outputs are shorted to ±15 V and the power supplies are at low and provide low-impedance paths to ground (see Figure 15). VDD GD65232, GD75232 ±15 V VDD Output GD65232, GD75232 VSS VSS Figure 15.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com (4) 18-Oct-2013 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
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PACKAGE MATERIALS INFORMATION www.ti.com 9-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 12.0 24.0 Q1 GD65232DWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 GD65232PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 GD75232DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 9-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) GD65232DWR SOIC DW 20 2000 367.0 367.0 45.0 GD65232PWR TSSOP PW 20 2000 367.0 367.0 38.0 GD75232DBR SSOP DB 20 2000 367.0 367.0 38.0 GD75232DWR SOIC DW 20 2000 367.0 367.0 45.0 GD75232DWR SOIC DW 20 2000 367.0 367.0 45.0 GD75232PWR TSSOP PW 20 2000 364.0 364.0 27.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.