Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsLinear IC - In-amp, Op-amp InAmp PDIP 16

Difet

; Burr-Brown Corporation

FEATURES

● LOW INPUT BIAS CURRENT: 3fA typ

● BUFFERED GUARD DRIVE PINS

● LOW OFFSET VOLTAGE: 2mV max

● HIGH COMMON-MODE REJECTION:

84dB (G = 10)

● LOW QUIESCENT CURRENT: 1mA

● INPUT OVER-VOLTAGE PROTECTION:

±40V

APPLICATIONS

● LABORATORY INSTRUMENTATION

● pH MEASUREMENT

● ION–SPECIFIC PROBES

● LEAKAGE CURRENT MEASUREMENT

Ultra Low Input Bias Current

INSTRUMENTATION AMPLIFIER

INA116

60kΩ60kΩ

V+

V–

INA116

Ref

G = 1 +

50kΩ

–

25kΩ

Guard

Over-Voltage

Protection

Over-Voltage

Protection

DESCRIPTION

The INA116 is a complete monolithic FET-input instru-

mentation amplifier with extremely low input bias

current.

Difet

inputs and special guarding techniques

yield input bias currents of 3fA at 25°C, and only 25fA

at 85°C. Its 3-op amp topology allows gains to be set

from 1 to 1000 by connecting a single external resistor.

Guard pins adjacent to both input connections can be

used to drive circuit board and input cable guards to

maintain extremely low input bias current.

The INA116 is available in 16-pin plastic DIP and SOL-16

surface-mount packages, specified for the –40°C to +85°C

temperature range.

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111

Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132

SBOS034

Summary of content (11 pages)

PAGE 1
® INA116 INA 116 INA 116 Ultra Low Input Bias Current INSTRUMENTATION AMPLIFIER FEATURES DESCRIPTION ● LOW INPUT BIAS CURRENT: 3fA typ The INA116 is a complete monolithic FET-input instrumentation amplifier with extremely low input bias current. Difet ® inputs and special guarding techniques yield input bias currents of 3fA at 25°C, and only 25fA at 85°C. Its 3-op amp topology allows gains to be set from 1 to 1000 by connecting a single external resistor.
PAGE 2
SPECIFICATIONS AT TA = +25°C, VS = ±15V, RL = 10kΩ, unless otherwise noted. INA116P, U PARAMETER CONDITIONS INPUT Offset Voltage, RTI Initial vs Temperature vs Power Supply Long-Term Stability Bias Current vs Temperature Offset Current vs Temperature Impedance, Differential Common-Mode Common-Mode Voltage Range Safe Input Voltage Common-Mode Rejection TA = +25°C TA = TMIN to TMAX VS = ±4.5V to ±18V VCM = ±11V, ∆RS = 1kΩ G=1 G = 10 G = 100 VCM = ±5V, G = 1000 NOISE Voltage Noise, RTI f = 1kHz fB = 0.
PAGE 3
ELECTROSTATIC DISCHARGE SENSITIVITY PIN CONFIGURATION Top View DIP SOL-16 RG 1 16 RG Guard – 2 15 NC – VIN 3 14 NC Guard – 4 13 V+ Guard + 5 12 NC + VIN 6 11 VO Guard + 7 10 NC V– 8 9 This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
PAGE 4
TYPICAL PERFORMANCE CURVES At TA = +25°C, VS = ±15V, RL = 10kΩ, unless otherwise noted.
PAGE 5
TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VS = ±15V, RL = 10kΩ, unless otherwise noted.
PAGE 6
TYPICAL PERFORMANCE CURVES (CONT) At TA = +25°C, VS = ±15V, RL = 10kΩ, unless otherwise noted. VOLTAGE NOISE, 0.
PAGE 7
APPLICATIONS INFORMATION The 50kΩ term in equation 1 is the sum of the two feedback resistors of A1 and A2. These on-chip metal film resistors are laser trimmed to accurate absolute values. The accuracy and temperature coefficient of these resistors are included in the gain accuracy and drift specifications of the INA116. Figure 1 shows the connections required for basic operation of the INA116.
PAGE 8
– VIN V+ VO INA116 RG + VIN CIRCUIT BOARD LAYOUT AND ASSEMBLY Careful circuit board layout and assembly techniques are required to achieve the exceptionally low input bias current performance of the INA116. Guard terminals adjacent to both inputs make it easy to properly guard the critical input terminal layout. Since traces are not required to run between device pins, this layout is easily accomplished, even with the surface mount package.
PAGE 9
INPUT CONNECTIONS Some applications must make high impedance input connections to external sensors or input connectors. To assure low leakage, the input should be guarded all the way to the signal source—see Figure 5. Coaxial cable can be used with the shield driven by the guard. A separate connection is required to provide a ground reference at the signal source. Triaxial cable may reduce noise pickup and provides the ground reference at the source.
PAGE 10
PACKAGE OPTION ADDENDUM www.ti.
PAGE 11
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.