Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - current control/management Current/voltage monitor VQFN 16 (4x4)

Power

Supply

(0V to 26V)

Load 1

Load 2

Power

Supply

(0V to 26V)

Load 3

Power

Supply

(0V to 26V)

BYPASS

0.1µF

(Supply

Voltage)

CH 1

CH 2

IN-

IN+

IN-

IN+

CH 3

IN-

IN+

Interface

SDA

SCL

Critical

Warning

GND

ADC

Shunt

Voltages 1-3

Critical Limit

Alerts 1-3

Bus

Voltages 1-3

Power Valid

Timing Control

Shunt Voltage

Sum Alerts

10kΩ

VPU

10kΩ

INA3221

www.ti.com

SBOS576A –MAY 2012–REVISED JUNE 2013

Triple-Channel, High-Side Measurement, Shunt and Bus Voltage Monitor

with I

C™ Interface

Check for Samples: INA3221

FEATURES

DESCRIPTION

The INA3221 is a three-channel, high-side current

• Senses Bus Voltages From 0 V to +26 V

and bus voltage monitor with an I

C interface. The

• Reports Shunt and Bus Voltage

INA3221 monitors both shunt voltage drops and bus

• High Accuracy:

supply voltages in addition to having programmable

conversion times and averaging modes for these

– Offset Voltage: ±80 µV (max)

signals. The INA3221 offers both critical and warning

– Gain Error: 0.25% (max)

alerts to detect multiple programmable out-of-range

• Configurable Averaging Options

conditions for each channel.

• Four Programmable Addresses

The INA3221 senses current on buses that can vary

• Power-Supply Operation: 2.7 V to 5.5 V

from 0 V to +26 V. The device is powered from a

single +2.7-V to +5.5-V supply and draws 350 μA

• Programmable Alert and Warning Outputs

(typ) of supply current. The INA3221 is specified over

the operating temperature range of –40°C to +125°C.

APPLICATIONS

The I

C interface features four programmable

• Computers

addresses.

• Power Management

Summary of content (39 pages)

PAGE 1
INA3221 www.ti.com SBOS576A – MAY 2012 – REVISED JUNE 2013 Triple-Channel, High-Side Measurement, Shunt and Bus Voltage Monitor with I2C™ Interface Check for Samples: INA3221 FEATURES DESCRIPTION • • • The INA3221 is a three-channel, high-side current and bus voltage monitor with an I2C interface. The INA3221 monitors both shunt voltage drops and bus supply voltages in addition to having programmable conversion times and averaging modes for these signals.
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INA3221 SBOS576A – MAY 2012 – REVISED JUNE 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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INA3221 www.ti.com SBOS576A – MAY 2012 – REVISED JUNE 2013 ELECTRICAL CHARACTERISTICS: VS = +3.3 V At TA = +25°C, VIN+ = 12 V, VSENSE = (VIN+) – (VIN–) = 0 mV, and VBUS = 12 V, unless otherwise noted. INA3221 PARAMETER CONDITIONS MIN TYP MAX UNIT –163.84 163.8 mV 0 26 INPUT Voltage input range CMR Shunt Bus Common-mode rejection VOS Shunt PSRR Offset voltage, RTI (1) VOS 110 PSRR dB ±40 ±80 μV TA = –40°C to +125°C 0.1 0.5 μV/°C vs power supply, VS = +2.7 V to +5.
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INA3221 SBOS576A – MAY 2012 – REVISED JUNE 2013 www.ti.com ELECTRICAL CHARACTERISTICS: VS = +3.3 V (continued) At TA = +25°C, VIN+ = 12 V, VSENSE = (VIN+) – (VIN–) = 0 mV, and VBUS = 12 V, unless otherwise noted. INA3221 PARAMETER CONDITIONS MIN TYP MAX UNIT POWER SUPPLY Operating supply range Quiescent current +2.7 Power-down mode +5.5 V 350 450 μA 0.
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INA3221 www.ti.com SBOS576A – MAY 2012 – REVISED JUNE 2013 PIN CONFIGURATIONS VPU IN+2 IN 2 TC 16 15 14 13 RGV PACKAGE QFN-16 (Top View) GND 3 10 PV VS 4 9 Critical 8 IN 1 Warning 11 7 2 SDA IN+3 6 IN+1 SCL 12 5 1 A0 IN 3 PIN DESCRIPTIONS PIN NAME NO ANALOG OR DIGITAL INPUT/OUTPUT DESCRIPTION Address pin. Connect to GND, SCL, SDA, or VS. Table 7 shows pin settings and corresponding addresses.
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INA3221 SBOS576A – MAY 2012 – REVISED JUNE 2013 www.ti.com REGISTER BLOCK DIAGRAM Bus Voltage(1) Shunt Voltage Channel Channel 2 ADC X Power Valid Upper Limit (2) Channel 3 Bus Voltage Channel Power Valid Lower Limit(2) Shunt Voltage(1) X Critical Limit(2) Warning Limit(2) Channel 2 Summation(1) Channel 3 Summation Limit(2) (1) Read-only. (2) Read/write. Figure 1.
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INA3221 www.ti.com SBOS576A – MAY 2012 – REVISED JUNE 2013 TYPICAL CHARACTERISTICS At TA = +25°C, VS = +3.3 V, VIN+ = 12 V, VSENSE = (VIN+) – (VIN–) = 0 mV, and VBUS = 12 V, unless otherwise noted. SHUNT INPUT OFFSET VOLTAGE PRODUCTION DISTRIBUTION FREQUENCY RESPONSE 0 −10 Population Gain (dB) −20 −30 −40 200 160 120 G001 80 100k 40 10k 0 100 1k Frequency (Hz) −40 10 −80 1 −160 −60 −120 −50 Input Offset Voltage (µV) G003 Figure 2. Figure 3.
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INA3221 SBOS576A – MAY 2012 – REVISED JUNE 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = +3.3 V, VIN+ = 12 V, VSENSE = (VIN+) – (VIN–) = 0 mV, and VBUS = 12 V, unless otherwise noted. SHUNT INPUT GAIN ERROR vs COMMON-MODE VOLTAGE BUS INPUT OFFSET VOLTAGE PRODUCTION DISTRIBUTION 150 Population Input Offset Voltage (mV) Figure 8. Figure 9.
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INA3221 www.ti.com SBOS576A – MAY 2012 – REVISED JUNE 2013 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = +3.3 V, VIN+ = 12 V, VSENSE = (VIN+) – (VIN–) = 0 mV, and VBUS = 12 V, unless otherwise noted. INPUT BIAS CURRENT vs TEMPERATURE INPUT BIAS CURRENT vs TEMPERATURE (Shutdown) 30 450 400 IB− Input Bias Current (nA) Input Bias Current (µA) 25 20 15 IB+ 10 350 300 250 200 150 100 5 IB+, IB− 50 0 −50 −25 0 25 50 75 Temperature (°C) 100 125 0 −50 150 −25 0 G014 Figure 14.
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INA3221 SBOS576A – MAY 2012 – REVISED JUNE 2013 www.ti.com APPLICATION INFORMATION The INA3221 is a current-shunt and bus voltage monitor that communicates over an I2C- and SMBus-compatible interface. The device provides digital shunt and bus voltage readings necessary for accurate decision making in precisely-controlled systems and also monitors multiple rails to ensure compliance voltages are maintained.
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INA3221 www.ti.com SBOS576A – MAY 2012 – REVISED JUNE 2013 BASIC ADC FUNCTIONS The INA3221 performs two measurements on up to three power supplies of interest. The voltage developed from the load current passing through a shunt resistor creates a shunt voltage that is measured between the IN+ and IN– pins. The device also internally measures the power-supply bus voltage at the IN– pin for each channel.
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INA3221 SBOS576A – MAY 2012 – REVISED JUNE 2013 www.ti.com INA3221 AVERAGING FUNCTION The INA3221 includes three channels to monitor up to three independent supply buses. Multichannel monitoring potentially results in poor shunt resistor placement. Ideally, the shunt resistors should be located as close as possible to the corresponding channel input pins.
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INA3221 www.ti.com SBOS576A – MAY 2012 – REVISED JUNE 2013 MULTIPLE CHANNEL MONITORING The INA3221 can be configured to monitor shunt and voltage measurements for up to three unique power-supply rails. This configuration allows for a total of six different signals to be measured. The INA3221 can be configured to adjust the number of channels and signals being measured through the Channel Enable and MODE bits in the Configuration Register.
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INA3221 SBOS576A – MAY 2012 – REVISED JUNE 2013 www.ti.com The conversion times selected can also have an impact on measurement accuracy. This effect can seen in Figure 23. Multiple conversion times shown in Figure 23 illustrate the impact of noise on the measurement. These curves were taken without averaging used.
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INA3221 www.ti.com SBOS576A – MAY 2012 – REVISED JUNE 2013 Warning Alert The Warning Alert monitors the averaged value of each shunt voltage channel. The averaged value of each shunt voltage channel is based on the number of averages set with the Average Mode bits in the Configuration Register. The average value is updated in the shunt voltage output register each time there is a conversion on the corresponding channel.
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INA3221 SBOS576A – MAY 2012 – REVISED JUNE 2013 www.ti.com The Power Valid output pin allows for a 0-V output that indicates a power invalid condition. An output equal to the pull-up supply voltage connected to VPU indicates a power valid condition, as shown in Figure 25. It is also possible to divide down the High Power Valid pull-up voltage by adding a resistor to ground at the PV output, thus allowing this function to interface with lower-voltage circuitry if needed.
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INA3221 www.ti.com SBOS576A – MAY 2012 – REVISED JUNE 2013 1.2 V Detected on Channel 1 Bus Voltage Measurement Measure For 1.2 V on Channel 2 Bus Voltage 1.2 V on Channel 2 Detected High Timing Control Output 28.6 ms 1.2 V on Channel 2 Not Detected Low Figure 27. Timing Control State Diagram The Timing Control Alert function is only monitored at power-up or when a software reset is issued by setting the RESET bit (bit 15) in the Configuration Register.
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INA3221 SBOS576A – MAY 2012 – REVISED JUNE 2013 www.ti.com Overload conditions are another consideration for the INA3221 inputs. The INA3221 inputs are specified to tolerate 26 V across the inputs. A large differential scenario might be a short to ground on the load side of the shunt. This type of event can result in full power-supply voltage across the shunt (as long as the power supply or energy storage capacitors can support it).
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INA3221 www.ti.com SBOS576A – MAY 2012 – REVISED JUNE 2013 REGISTER INFORMATION The INA3221 uses a bank of registers for holding configuration settings, measurement results, minimum and maximum limits, and status information. Table 1 summarizes the INA3221 registers; refer to Figure 1 for an illustration of the registers. Table 1.
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INA3221 SBOS576A – MAY 2012 – REVISED JUNE 2013 www.ti.com REGISTER DETAILS All 16-bit INA3221 registers are two 8-bit bytes via the I2C interface. Table 2 shows a register map for the INA3221. Table 2.
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INA3221 www.ti.com SBOS576A – MAY 2012 – REVISED JUNE 2013 Configuration Register (Address = 00h, Read/Write) BIT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME RST CH1en CH2en CH3en AVG2 AVG1 AVG0 VBUSCT2 VBUSCT1 VBUSCT0 VSHCT2 VSHCT1 VSHCT0 MODE3 MODE2 MODE1 POR VALUE 0 1 1 1 0 0 0 1 0 0 1 0 0 1 1 1 Bit 15 RST: Reset bit Setting this bit to '1' generates a system reset that is the same as a power-on reset (POR).
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INA3221 SBOS576A – MAY 2012 – REVISED JUNE 2013 Bits[5:3] www.ti.com VSH CT: Shunt voltage conversion time Sets the conversion time for the shunt voltage measurement. Table 5 shows the VSH CT bit options and related conversion times for each bit. Table 5. VSH CT Bit Settings, Bits[5:3] Bits[2:0] VSH CT2 D5 VSH CT1 D4 VSH CT0 D3 CONVERSION TIME 0 0 0 140 µs 0 0 1 204 µs 0 1 0 332 µs 0 1 1 588 µs 1 (default) 0 (default) 0 (default) 1.1 ms (default) 1 0 1 2.116 ms 1 1 0 4.
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INA3221 www.ti.com SBOS576A – MAY 2012 – REVISED JUNE 2013 Channel 1 Shunt Voltage Register (Address = 01h, Read-Only) Full-scale range = 163.8 mV (decimal = 7FF8); LSB (SD0): 40 μV. This register contains the averaged shunt voltage measurement for channel 1.
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INA3221 SBOS576A – MAY 2012 – REVISED JUNE 2013 www.ti.com Channel 2 Shunt Voltage Register (Address = 03h, Read-Only) Full-scale range = 163.8 mV (decimal = 7FF8); LSB (SD0): 40 μV. This register contains the averaged shunt voltage measurement for channel 2.
PAGE 25
INA3221 www.ti.com SBOS576A – MAY 2012 – REVISED JUNE 2013 Critical Alert Channel 1 Limit Register (Address = 07h, Read/Write) BIT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME C1L12 C1L11 C1L10 C1L9 C1L8 C1L7 C1L6 C1L5 C1L4 C1L3 C1L2 C1L1 C1L0 — — — POR VALUE 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 This register contains the value used to compare to each shunt voltage conversion on channel 1 to detect fast overcurrent events.
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INA3221 SBOS576A – MAY 2012 – REVISED JUNE 2013 www.ti.com Critical Alert Channel 3 Limit Register (Address = 0Bh, Read/Write) BIT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME C3L12 C3L11 C3L10 C3L9 C3L8 C3L7 C3L6 C3L5 C3L4 C3L3 C3L2 C3L1 C3L0 — — — POR VALUE 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 This register contains the value used to compare to each shunt voltage conversion on channel 3 to detect fast overcurrent events.
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INA3221 www.ti.com SBOS576A – MAY 2012 – REVISED JUNE 2013 Mask/Enable Register (Address = 0Fh, Read/Write) BIT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME — SCC1 SCC2 SCC3 WEN CEN CF1 CF2 CF3 SF WF1 WF2 WF3 PVF TCF CVRF POR VALUE 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 Bits[14:12] SCC: Summation Channel Control These bits determine which shunt voltage measurement channels are enabled to fill the Shunt Voltage Sum register.
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INA3221 SBOS576A – MAY 2012 – REVISED JUNE 2013 www.ti.com Power Valid Upper Limit Register (Address = 10h, Read/Write) (1) BIT D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME SIGN PVU11 PVU10 PVU9 PVU8 PVU7 PVU6 PVU5 PVU4 PVU3 PVU2 PVU1 PVU0 — — — POR VALUE 0 0 1 0 0 1 1 1 0 0 0 1 0 0 0 0 (1) Power-on reset value is 2710h (10.000 V) This register contains the value used to determine if the Power Valid conditions are met.
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INA3221 www.ti.com SBOS576A – MAY 2012 – REVISED JUNE 2013 BUS OVERVIEW The INA3221 offers compatibility with both I2C and SMBus interfaces. The I2C and SMBus protocols are essentially compatible with one another. The I2C interface is used throughout this data sheet as the primary example, with the SMBus protocol specified only when a difference between the two systems is discussed. Two bidirectional lines, the serial clock (SCL) and data signal line (SDA), connect the INA3221 to the bus.
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INA3221 SBOS576A – MAY 2012 – REVISED JUNE 2013 www.ti.com WRITING TO AND READING FROM THE INA3221 Accessing a specific INA3221 register is accomplished by writing the appropriate value to the register pointer. Refer to Table 1 for a complete list of registers and corresponding addresses. The value for the register pointer (refer to Figure 32) is the first byte transferred after the slave address byte with the R/W bit low. Every write operation to the INA3221 requires a register pointer value.
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INA3221 www.ti.com SBOS576A – MAY 2012 – REVISED JUNE 2013 Figure 31 shows the timing diagram for the SMBus Alert response operation. Figure 32 illustrates a typical register pointer configuration. 1 9 1 9 SCL SDA 0 0 0 1 1 0 0 Start By Master 1 R/W 0 0 0 ACK By Device 0 A0 From Device Frame 1: SMBus ALERT Response Address Byte (1) 0 0 No ACK By Master(2) Stop By Master Frame 2: Slave Address Byte (1) The value of the Slave Address Byte is determined by the A0 pin setting.
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INA3221 SBOS576A – MAY 2012 – REVISED JUNE 2013 www.ti.com High-Speed I2C Mode When the bus is idle, the SDA and SCL lines are pulled high by the pull-up devices. The master generates a start condition followed by a valid serial byte with the High-Speed (HS) master code 00001XXX. This transmission is made in fast (400 kHz) or standard (100 kHz) (F/S) mode at no more than 400 kHz. The INA3221 does not acknowledge the HS master code, but does recognize it and switches its internal filters to support 3.
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INA3221 www.ti.com SBOS576A – MAY 2012 – REVISED JUNE 2013 REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (May 2012) to Revision A Page • Changed Input, Voltage input range, Shunt parameter specifications in +3.3 V Electrical Characteristics table ................ 3 • Updated Figure 24 ...................................................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 5-Jun-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant INA3221AIRGVR VQFN RGV 16 2500 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 INA3221AIRGVT VQFN RGV 16 250 180.0 12.4 4.25 4.25 1.15 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 5-Jun-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) INA3221AIRGVR VQFN RGV 16 2500 367.0 367.0 35.0 INA3221AIRGVT VQFN RGV 16 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.