Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsLinear IC - In-amp, Op-amp InAmp SON 8 (3x3)

+IN

OUT

REF

-IN

-V

MSOP-8,SO-8

INA826

www.ti.com

SBOS562E –AUGUST 2011–REVISED APRIL 2013

Precision, 200-µA Supply Current, 2.7-V to 36-V Supply

Instrumentation Amplifier with Rail-to-Rail Output

Check for Samples: INA826

FEATURES

DESCRIPTION

The INA826 is a low-cost instrumentation amplifier

234

• Input Common-Mode Range: Includes V–

that offers extremely low power consumption and

• Common-Mode Rejection:

operates over a very wide single or dual supply

– 104 dB, min (G = 10)

range. A single external resistor sets any gain from 1

to 1000. It offers excellent stability over temperature,

– 100 dB, min at 5 kHz (G = 10)

even at G > 1, as a result of the low gain drift of only

• Power-Supply Rejection: 100 dB, min (G = 1)

35 ppm/°C (max).

• Low Offset Voltage: 150 µV, max

The INA826 is optimized to provide excellent

• Gain Drift: 1 ppm/°C (G = 1), 35 ppm/°C (G > 1)

common-mode rejection ratio of over 100 dB (G = 10)

• Noise: 18 nV/√Hz, G ≥ 100

over frequencies up to 5 kHz. In G = 1, the common-

mode rejection ratio exceeds 84 dB across the full

• Bandwidth: 1 MHz (G = 1), 60 kHz (G = 100)

input common-mode range from the negative supply

• Inputs Protected up to ±40 V

all the way up to 1 V of the positive supply. Using a

• Rail-to-Rail Output

rail-to-rail output, the INA826 is well-suited for low

voltage operation from a 2.7 V single supply as well

• Supply Current: 200 µA

as dual supplies up to ±18 V.

• Supply Range:

Additional circuitry protects the inputs against

– Single Supply: +2.7 V to +36 V

overvoltage of up to ±40 V beyond the power

– Dual Supply: ±1.35 V to ±18 V

supplies by limiting the input currents to less than

• Specified Temperature Range:

8 mA.

–40°C to +125°C

The INA826 is available in SO-8, MSOP-8, and tiny

• Packages: MSOP-8, SO-8 and DFN-8

3-mm × 3-mm DFN-8 surface-mount packages. All

versions are specified for the –40°C to +125°C

APPLICATIONS

temperature range.

• Industrial Process Controls

Summary of content (43 pages)

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INA826 www.ti.com SBOS562E – AUGUST 2011 – REVISED APRIL 2013 Precision, 200-µA Supply Current, 2.
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INA826 SBOS562E – AUGUST 2011 – REVISED APRIL 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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INA826 www.ti.com SBOS562E – AUGUST 2011 – REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1, unless otherwise noted. INA826 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RTI 40 150 vs temperature, TA = –40°C to +125°C 0.
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INA826 SBOS562E – AUGUST 2011 – REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1, unless otherwise noted. INA826 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT GAIN 49.4 kW G Gain equation G Range of gain GE Gain error Gain vs temperature (4) Gain nonlinearity 1+ V/V RG 1 1000 V/V G = 1, VO = ±10 V ±0.003 ±0.015 % G = 10, VO = ±10 V ±0.03 ±0.15 % G = 100, VO = ±10 V ±0.04 ±0.
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INA826 www.ti.com SBOS562E – AUGUST 2011 – REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS (continued) At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1, unless otherwise noted. INA826 PARAMETER TEST CONDITIONS MIN TYP MAX UNIT REFERENCE INPUT RIN Input impedance 100 Voltage range kΩ (V–) Gain to output (V+) V 1 Reference gain error V/V 0.01 % POWER SUPPLY VS Power-supply voltage IQ Quiescent current Single Dual +2.7 +36 ±1.
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INA826 SBOS562E – AUGUST 2011 – REVISED APRIL 2013 www.ti.com PIN CONFIGURATIONS DGK PACKAGE MSOP-8, SO-8 (TOP VIEW) DRG PACKAGE 3-mm × 3-mm DFN-8 (TOP VIEW) -IN 1 8 +VS RG 2 7 VOUT RG 3 6 REF +IN 4 5 -VS -IN 1 RG 2 RG 3 +IN 4 Exposed Thermal Die Pad on Underside 8 +VS 7 VOUT 6 REF 5 -VS PIN DESCRIPTIONS 6 NAME NO. –IN 1 Negative input DESCRIPTION RG 2 Gain setting pin. Place a gain resistor between pin 2 and pin 3. RG 3 Gain setting pin.
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INA826 www.ti.com SBOS562E – AUGUST 2011 – REVISED APRIL 2013 TYPICAL CHARACTERISTICS At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1, unless otherwise noted. TYPICAL DISTRIBUTION OF INPUT OFFSET VOLTAGE TYPICAL DISTRIBUTION OF INPUT OFFSET VOLTAGE DRIFT 1600 25 1400 20 1200 Count Count 1000 800 15 10 600 400 5 200 −2 −1.8 −1.6 −1.4 −1.2 −1 −0.8 −0.6 −0.4 −0.2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.
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INA826 SBOS562E – AUGUST 2011 – REVISED APRIL 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1, unless otherwise noted.
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INA826 www.ti.com SBOS562E – AUGUST 2011 – REVISED APRIL 2013 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1, unless otherwise noted. INPUT COMMON-MODE VOLTAGE vs OUTPUT VOLTAGE (Dual Supply, VS = ±3.3 V) INPUT COMMON-MODE VOLTAGE vs OUTPUT VOLTAGE (Dual Supply, VS = ±5 V) 5 3 VS = ±3.
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INA826 SBOS562E – AUGUST 2011 – REVISED APRIL 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1, unless otherwise noted. CMRR vs FREQUENCY (RTI) CMRR vs FREQUENCY (RTI, 1-kΩ Source Imbalance) 140 Common−Mode Rejection Ratio (dB) Common−Mode Rejection Ratio (dB) 160 140 120 100 80 60 G=1 G = 10 G = 100 G = 1000 40 20 0 10 100 1k Frequency (Hz) 10k 120 100 80 60 40 G=1 G = 10 G = 100 G = 1000 20 0 100k 10 100 G001 Figure 19.
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INA826 www.ti.com SBOS562E – AUGUST 2011 – REVISED APRIL 2013 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1, unless otherwise noted. CURRENT NOISE SPECTRAL DENSITY vs FREQUENCY (RTI) 0.1-Hz TO 10-Hz RTI VOLTAGE NOISE (G = 1) 1k 3 Noise (µV/div) Current Noise (fA/ Hz) 2 100 1 0 −1 −2 10 1 10 100 Frequency (Hz) 1k −3 10k 0 1 2 3 G020 Figure 25. 4 5 6 Time (s/div) 7 8 9 10 G007 Figure 26. 0.
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INA826 SBOS562E – AUGUST 2011 – REVISED APRIL 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1, unless otherwise noted.
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INA826 www.ti.com SBOS562E – AUGUST 2011 – REVISED APRIL 2013 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1, unless otherwise noted. GAIN NONLINEARITY (G = 10) 4 3 3 Nonlinearity (ppm) Nonlinearity (ppm) GAIN NONLINEARITY (G = 1) 4 2 1 2 1 0 −10 −8 −6 −4 −2 0 2 4 Output Voltage (V) 6 8 0 −10 10 −8 −6 −4 G021 Figure 37.
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INA826 SBOS562E – AUGUST 2011 – REVISED APRIL 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1, unless otherwise noted. OFFSET VOLTAGE vs NEGATIVE COMMON-MODE VOLTAGE (VS = +2.7 V) VS = 2.7 V 250 Offset Voltage (µV) 200 VS = 2.7 V −50°C −40°C +25°C +85°C +125°C +150°C 200 150 100 50 0 −50 15 0.3 0.4 −50 −100 1 2.4 NEGATIVE OUTPUT VOLTAGE SWING vs OUTPUT CURRENT (VS = ±15 V) −14 −50°C −40°C +25°C +85°C +125°C +150°C 14.
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INA826 www.ti.com SBOS562E – AUGUST 2011 – REVISED APRIL 2013 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1, unless otherwise noted. SETTLING TIME vs STEP SIZE (VS = ±15-V) LARGE-SIGNAL FREQUENCY RESPONSE 25 30 VS = ±15 V VS = +5 V 27 0.01% 0.001% 21 21 Settling Time (µs) Output Voltage (V) 24 18 15 12 9 6 17 13 9 3 1k 10k 5 1M 2 4 6 8 G014 10 12 14 Step Size (V) 16 Figure 50.
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INA826 SBOS562E – AUGUST 2011 – REVISED APRIL 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) At TA = +25°C, VS = ±15 V, RL = 10 kΩ, VREF = 0 V, and G = 1, unless otherwise noted. SMALL-SIGNAL RESPONSE (G = 1000, RL = 10 kΩ, CL = 100 pF) 100 OPEN-LOOP OUTPUT IMPEDANCE 100k 80 40 10k 20 ZO (Ω) Amplitude (mV) 60 0 −20 1k −40 −60 −80 −100 0 100 200 300 400 500 600 700 800 900 1000 time (us) G012 100 1 10 100 Figure 55. 1k 10k Frequency (Hz) 100k 1M 10M G062 Figure 56.
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INA826 www.ti.com SBOS562E – AUGUST 2011 – REVISED APRIL 2013 APPLICATION INFORMATION Figure 58 shows the basic connections required for operation of the INA826. Good layout practice mandates the use of bypass capacitors placed as close to the device pins as possible. The output of the INA826 is referred to the output reference (REF) terminal, which is normally grounded. This connection must be low-impedance to assure good common-mode rejection.
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INA826 SBOS562E – AUGUST 2011 – REVISED APRIL 2013 www.ti.com SETTING THE GAIN Gain of the INA826 is set by a single external resistor, RG, connected between pins 2 and 3. The value of RG is selected according to Equation 1: G=1+ 49.4 kW RG (1) Table 1 lists several commonly-used gains and resistor values. The 49.4-kΩ term in Equation 1 comes from the sum of the two internal 24.7-kΩ feedback resistors. These on-chip resistors are laser-trimmed to accurate absolute values.
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INA826 www.ti.com SBOS562E – AUGUST 2011 – REVISED APRIL 2013 OFFSET TRIMMING Most applications require no external offset adjustment; however, if necessary, adjustments can be made by applying a voltage to the REF terminal. Figure 59 shows an optional circuit for trimming the output offset voltage. The voltage applied to the REF terminal is summed at the output. The op amp buffer provides low impedance at the REF terminal to preserve good common-mode rejection.
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INA826 SBOS562E – AUGUST 2011 – REVISED APRIL 2013 www.ti.com INSIDE THE INA826 See Figure 58 for a simplified representation of the INA826. A more detailed diagram (shown in Figure 60) provides additional insight into the INA826 operation. Each input is protected by two field-effect transistors (FETs) that provide a low series resistance under normal signal conditions, and preserve excellent noise performance. When excessive voltage is applied, these transistors limit input current to approximately 8 mA.
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INA826 www.ti.com SBOS562E – AUGUST 2011 – REVISED APRIL 2013 INPUT BIAS CURRENT RETURN PATH The input impedance of the INA826 is extremely high—approximately 20 GΩ. However, a path must be provided for the input bias current of both inputs. This input bias current is typically 35 nA. High input impedance means that this input bias current changes very little with varying input voltage. Input circuitry must provide a path for this input bias current for proper operation.
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INA826 SBOS562E – AUGUST 2011 – REVISED APRIL 2013 www.ti.com REFERENCE TERMINAL The output voltage of the INA826 is developed with respect to the voltage on the reference terminal. Often, in dual-supply operation, the reference pin (pin 6) is connected to the low-impedance system ground. In singlesupply operation, it can be useful to offset the output signal to a precise mid-supply level (for example, 2.5 V in a 5-V supply environment).
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INA826 www.ti.com SBOS562E – AUGUST 2011 – REVISED APRIL 2013 OPERATING VOLTAGE The INA826 operates over a power-supply range of +2.7 V to +36 V (±1.35 V to ±18 V). Supply voltages higher than 40 V (±20 V) can permanently damage the device. Parameters that vary over supply voltage or temperature are shown in the Typical Characteristics section of this data sheet. Low-Voltage Operation The INA826 can operate on power supplies as low as ±1.35 V.
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INA826 SBOS562E – AUGUST 2011 – REVISED APRIL 2013 www.ti.com Resistor-adjustable INAs such as the INA826 show the lowest gain error in G = 1 because of the inherently wellmatched drift of the internal resistors of the differential amplifier. At gains greater than 1 (for instance, G = 10 V/V or G = 100 V/V) the gain error becomes a significant error source because of the contribution of the resistor drift of the 24.7-kΩ feedback resistors in conjunction with the external gain resistor.
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INA826 www.ti.com SBOS562E – AUGUST 2011 – REVISED APRIL 2013 APPLICATION IDEAS Circuit Breaker Figure 64 showns the INA826 used in a circuit breaker application. +3 V AVDD DVDD SCLK Serial Interface (SPI) Passive Integrator 100 kW RG DIO MSP430 Microcontroller CS INA826 IP Mux Ch 1 ADC REF G=1 Rogowski Coil 100 kW PGA112 PGA113 +3 V GND REF3312 REF 1.2 V Figure 64.
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INA826 SBOS562E – AUGUST 2011 – REVISED APRIL 2013 www.ti.com TINA-TI (FREE DOWNLOAD SOFTWARE) Using TINA-TI SPICE-Based Analog Simulation Program with the INA826 TINA is a simple, powerful, and easy-to-use circuit simulation program based on a SPICE engine. TINA-TI is a free, fully functional version of the TINA software, preloaded with a library of macromodels in addition to a range of both passive and active models.
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INA826 www.ti.com SBOS562E – AUGUST 2011 – REVISED APRIL 2013 Figure 67 is an example of a LEAD I ECG circuit. The input signals come from leads attached to the right arm (RA) and left arm (LA). These signals are simulated with the circuitry in the corresponding boxes. Protection resistors (RPROT1 and RPROT2) and filtering are also provided. The OPA333 is used as an integrator to remove the gained-up dc offsets and servo the INA826 outputs to VREF.
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INA826 SBOS562E – AUGUST 2011 – REVISED APRIL 2013 www.ti.com Figure 68 shows an example of how the INA826 can be used for low-side current sensing. The load current (ILOAD) creates a voltage drop across the shunt resistor (RSHUNT). This voltage is amplified by the INA826, with gain set to 100. The output swing of the INA826 is set by the common-mode voltage (which is 0 V in low-side current sensing) and power supplies. Therefore, a dual-supply circuit is implemented.
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INA826 www.ti.com SBOS562E – AUGUST 2011 – REVISED APRIL 2013 Figure 69 shows an example of how the INA826 can be used for RTD signal conditioning. This circuit creates an excitation current (ISET) by forcing +2.5 V from the REF5025 across RSET. The zero-drift, low-noise OPA188 creates the virtual ground that maintains a constant differential voltage across RSET with changing common-mode voltage.
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INA826 SBOS562E – AUGUST 2011 – REVISED APRIL 2013 www.ti.com The circuit in Figure 70 creates a precision current ISET by forcing the INA826 VDIFF across RSET. The input voltage VIN is amplified to the output of the INA826 and then divided down by the gain of the INA826 to create VDIFF. ISET can be controlled either by changing the value of the gain-set resistor RG, the set resistor RSET, or by changing VOUT through the gain of the composite loop.
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INA826 www.ti.com SBOS562E – AUGUST 2011 – REVISED APRIL 2013 EVALUATION MODULE (EVM) The INA826EVM is intended to provide basic functional evaluation of the INA826. A diagram of the INA826EVM is provided in Figure 71. Figure 71.
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INA826 SBOS562E – AUGUST 2011 – REVISED APRIL 2013 www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (March 2013) to Revision E • Deleted package marking column from Package/Ordering Information table ......................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 29-May-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 29-May-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing INA826AIDGKR VSSOP SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 INA826AIDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 INA826AIDRGR SON DRG 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 29-May-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) INA826AIDGKR VSSOP DGK 8 2500 358.0 335.0 35.0 INA826AIDR SOIC D 8 2500 367.0 367.0 35.0 INA826AIDRGR SON DRG 8 3000 367.0 367.0 35.0 INA826AIDRGT SON DRG 8 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.