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ISO5500

www.ti.com

SLLSE64C –SEPTEMBER 2011–REVISED JUNE 2013

2.5 A Isolated IGBT, MOSFET Gate Driver

Check for Samples: ISO5500

FEATURES

• 2.5 A Maximum Peak Output Current • Wide V

CC1

Range: 3 V to 5.5 V

• Drives IGBTs up to I

= 150 A, V

= 600 V • Wide V

CC2

Range: 15 V to 30 V

• Capacitive Isolated Fault Feedback • Operating Temperature: –40°C to 125°C

• CMOS/TTL Compatible Inputs • Wide-body SO-16 Package

• 300 ns Maximum Propagation Delay • ±50 kV/us Transient Immunity Typical

• Soft IGBT Turn-off • 6000 V

Peak

Isolation

• Integrated Fail-safe IGBT Protection • Regulatory Approvals:

– High V

(DESAT) Detection – UL1577, CSA, DIN EN 60747-5-2,

IEC 60950-1 and 61010-1 Approved

– Under-Voltage Lockout (UVLO) Protection

with Hysteresis

APPLICATIONS

• User Configurable Functions

• Isolated IGBT and MOSFET Drives in

– Inverting, Non-inverting Inputs

– Motor Control

– Auto-Reset

– Motion Control

– Auto-Shutdown

– Industrial Inverters

– Switched-Mode Power Supplies

DESCRIPTION

The ISO5500 is an isolated gate driver for IGBTs and MOSFETs with power ratings of up to I

= 150 A and

= 600 V. Input TTL logic and output power stage are separated by a capacitive, silicon dioxide (SiO

isolation barrier. When used in conjunction with isolated power supplies, the device blocks high voltage, isolates

ground, and prevents noise currents from entering the local ground and interfering with or damaging sensitive

circuitry.

The device provides over-current protection (DESAT) to an IGBT or MOSFET while an Undervoltage Lockout

circuit (UVLO) monitors the output power supply to ensure sufficient gate drive voltage. If the output supply drops

below 12 V, the UVLO turns the power transistor off by driving the gate drive output to a logic low state.

For a DESAT fault, the ISO5500 initiates a soft shutdown procedure that slowly reduces the IGBT/MOSFET

current to zero while preventing large di/dt induced voltage spikes. A fault signal is then transmitted across the

isolation barrier, actively driving the open-drain FAULT output low and disabling the device inputs. The inputs are

blocked as long as the FAULT-pin is low. FAULT remains low until the inputs are configured for an output low

state, followed by a logic low input on the RESET pin.

The ISO5500 is available in a 16-pin SOIC package and is specified for operating temperatures from –40°C to

125°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (41 pages)

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ISO5500 www.ti.com SLLSE64C – SEPTEMBER 2011 – REVISED JUNE 2013 2.5 A Isolated IGBT, MOSFET Gate Driver Check for Samples: ISO5500 FEATURES 1 • • • • • • • • 2.
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ISO5500 SLLSE64C – SEPTEMBER 2011 – REVISED JUNE 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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ISO5500 www.ti.com SLLSE64C – SEPTEMBER 2011 – REVISED JUNE 2013 1 16 VE VIN- 2 15 VEE-L VCC1 3 14 DESAT 13 VCC2 12 VC 11 VOUT ISOLATION VIN+ GND1 4 RESET 5 FAULT 6 NC 7 10 VEE-L GND1 8 9 VEE-P PIN FUNCTIONS PIN NO. DESCRIPTION NAME 1 VIN+ Non-inverting gate drive voltage control input 2 VIN– Inverting gate drive voltage control input 3 VCC1 Positive input supply (3 V to 5.5 V) 4,8 GND1 Input ground 5 RESET FAULT reset input 6 FAULT Open-drain output.
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ISO5500 SLLSE64C – SEPTEMBER 2011 – REVISED JUNE 2013 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) VALUE MIN Supply voltage, VCC1 Total output supply voltage, VOUT(total) (VCC2 – VEE-P) MAX –0.5 6 V –0.5 35 V V V Positive output supply Voltage, VOUT+ (VCC2 – VE) –0.5 35 – (VE – VEE-P) Negative output supply voltage, VOUT- (VE – VEE-P) –0.5 VCC2 VE – 0.5 VCC2 DESAT Voltage at Peak gate drive output voltage VIN+, VIN–, RESET –0.
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ISO5500 www.ti.com SLLSE64C – SEPTEMBER 2011 – REVISED JUNE 2013 RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN VCC1 Supply voltage VOUT(total) Total output supply voltage (VCC2 – VEE-P) TYP MAX UNIT 3 5.5 V 15 30 V 15 30V – (VE – VEE-P) V VOUT+ Positive output supply voltage (VCC2 – VE) VOUT– Negative output supply voltage (VE – VEE-P) 0 15 V VC Collector voltage VEE-P + 8 VCC2 V tui Input pulse width 0.
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ISO5500 SLLSE64C – SEPTEMBER 2011 – REVISED JUNE 2013 www.ti.com ELECTRICAL CHARACTERISTICS All typical values are at TA = 25°C, VCC1 = 5 V, VCC2 – VE = 30 V, VE – VEE-P = 0 V (unless otherwise noted) PARAMETER TEST CONDITIONS Quiescent MIN TYP MAX VI = VCC1 or 0 V, No load, See Figure 1, Figure 2, Figure 28, and Figure 29 5.5 8.5 5.7 8.7 VI = VCC1 or 0 V, No load, See Figure 3 through Figure 5, Figure 30, and Figure 31 8.
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ISO5500 SLLSE64C – SEPTEMBER 2011 – REVISED JUNE 2013 www.ti.com TYPICAL CHARACTERISTICS VCC1 SUPPLY CURRENT vs. TEMPERATURE 8 ICC1 - Supply Current (mA) ICC1 - Supply Current (mA) 7 6 5 4 3 2 VCC1 = 4.5 V VCC1 = 5 V VCC1 = 5.5 V VCC1 = 3 V VCC1 = 3.3 V VCC1 = 3.6 V 1 0 -40 -20 0 40 20 60 80 100 120 VCC1 SUPPLY CURRENT vs. FREQUENCY 7 6 5 4 3 2 VCC1 = 3.3 V VCC1 = 5 V 1 0 140 100 50 o Ambient Temperature ( C) Figure 1.
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ISO5500 www.ti.com SLLSE64C – SEPTEMBER 2011 – REVISED JUNE 2013 TYPICAL CHARACTERISTICS (continued) OUTPUT DRIVE CURRENT vs. TEMPERATURE OUTPUT SINK CURRENT vs. TEMPERATURE 8 -0.5 IOL - Output Sink Current (A) IOH - Output Drive Current (A) 0 -1 -1.5 -2 -2.5 -3 -3.5 -4 VOUT = VC - 4 V VOUT = VC - 15 V -4.5 -5 -40 -20 0 40 20 60 80 100 120 VOUT = 2.5 V VOUT = 15 V 7 6 5 4 3 2 1 0 -40 140 -20 0 o Figure 8.
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ISO5500 SLLSE64C – SEPTEMBER 2011 – REVISED JUNE 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) BLANKING CAPACITANCE CHARGING CURRENT vs. TEMPERATURE LOW OUTPUT VOLTAGE vs. OUTPUT SINK CURRENT -0.15 ICHG - Blanking Capacitor Charging Current (mA) VOL - Low Output Voltage (V) 6 5 4 3 2 TA = -40oC TA = 25oC TA = 125oC 1 0 0 1 0.5 1.5 -0.19 -0.21 -0.23 -0.25 -0.27 -0.29 -0.31 -0.33 -0.35 -40 2.5 2 -0.17 -20 0 DESAT THRESHOLD vs.
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ISO5500 www.ti.com SLLSE64C – SEPTEMBER 2011 – REVISED JUNE 2013 TYPICAL CHARACTERISTICS (continued) PROPAGATION DELAY vs. LOAD CAPACITANCE DESAT SENSE to 90% VOUT DELAY vs TEMPERATURE 1400 Propagation Delay (ns) 1200 1000 800 600 400 tPLH at VCC1 = 3.3 V tPHL at VCC1 = 3.
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ISO5500 SLLSE64C – SEPTEMBER 2011 – REVISED JUNE 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) RESET to FAULT DELAY vs TEMPERATURE OUTPUT WAVEFORM 10 VCC2 - VEE = 30 V R G = 0 W, 9 CL = 10 nF 8.5 8 7.5 7 VCC1 = 3 V VCC1 = 3.3 V VCC1 = 3.6 V VCC1 = 4.5 V VCC1 = 5 V VCC1 = 5.5 V 6.5 6 5.5 5 -40 -20 0 20 40 60 80 100 120 5 V / div Reset to Fault Delay (ms) 9.5 Time 125 ns / div 140 o Ambient Temperature ( C) Figure 25. Figure 26. VC SUPPLY CURRENT vs.
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ISO5500 www.ti.com SLLSE64C – SEPTEMBER 2011 – REVISED JUNE 2013 PARAMETER MEASUREMENT INFORMATION TEST CIRCUITS SPACER 2 3 4 5 6 7 8 1 VE 16 VIN+ 5.5 V VEE-L 15 VINVCC1 ICC1 5.5 V ICC1 1 0.1 µF 0.1 µF 2 3 DESAT 14 GND1 RESET FAULT 6 VOUT 11 7 VEE-L 10 NC GND1 8 VEE-P 9 Figure 28. ICC1H Test Circuit VIN- VEE-L 15 DESAT 14 GND1 5 VC 12 VE 16 VCC1 4 VCC2 13 VIN+ VCC2 13 RESET VC 12 FAULT VOUT 11 NC VEE-L 10 GND1 VEE-P 9 Figure 29.
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ISO5500 SLLSE64C – SEPTEMBER 2011 – REVISED JUNE 2013 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) SPACER 1 0.1 µF 3V 2 3 4 5 0.4 V 6 IFAULT 7 8 VE VIN+ VIN- VEE-L DESAT VCC1 GND1 VCC2 RESET FAULT VC 16 15 NC VEE-L GND1 VEE-P 5V 2 14 3 13 4 12 5 11 VOUT 1 0.1 µF 6 0.1 µF 30 V 10 7 9 8 Figure 34. IFL Test Circuit VIN+ VE VIN- VEE-L VCC1 GND1 RESET DESAT VCC2 VC FAULT VOUT NC VEE-L GND1 VEE-P 16 15 14 13 VPULSE 12 30 V 11 10 0.1 µF 4.
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ISO5500 www.ti.com SLLSE64C – SEPTEMBER 2011 – REVISED JUNE 2013 PARAMETER MEASUREMENT INFORMATION (continued) 1 0.1 µF 5V 2 3 4 5 6 7 8 VIN+ VE VIN- VEE-L GND1 1 15 0.1 µF 0.1 µF 5V 2 3 V1 VCC2 RESET IE 14 DESAT VCC1 16 VC 13 12 5 0.1 µF 11 FAULT VOUT NC VEE-L GND1 VEE-P 4 0.1 µF V2 6 10 7 9 8 Figure 40. IEH Test Circuit VIN+ VE VIN- VEE-L DESAT VCC1 GND1 VCC2 RESET VC FAULT VOUT NC VEE-L GND1 VEE-P 16 IE 15 0.1 µF 14 V1 13 0.1 µF 12 0.
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ISO5500 SLLSE64C – SEPTEMBER 2011 – REVISED JUNE 2013 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) 1 5V 0.1 µF 2 3 4 3k 5 6 100 pF 7 8 VIN+ VE VIN- VEE-L DESAT VCC1 GND1 VCC2 RESET FAULT VC VOUT VEE-L NC GND1 VEE-P 16 1 VIN 15 2 GND1 14 3 13 4 12 0.1 µF 11 10 9 5V SCOPE 4.7 µF 0.1 µF 5 30 V 3k 6 7 10 W 8 10 nF VIN+ VE VIN- VEE-L VCC1 GND1 DESAT VCC2 RESET VC FAULT VOUT NC VEE-L GND1 VEE-P 16 15 14 13 12 VOUT V1 0.1 µF 4.
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ISO5500 www.ti.com SLLSE64C – SEPTEMBER 2011 – REVISED JUNE 2013 PARAMETER MEASUREMENT INFORMATION (continued) VIN- VIN- 0V 50 % VIN+ 50 % 50 % VIN+ tr VCC1 tr tf VOUT tf 90% 90% 50% 50% VOUT 10% tPLH 50 % 10% tPLH tPHL Figure 49. VOUT Propagation Delay, Non-inverting Configuration tPHL Figure 50. VOUT Propagation Delay, Inverting Configuration tDESAT (FAULT ) tDESAT (10%) 7.
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ISO5500 SLLSE64C – SEPTEMBER 2011 – REVISED JUNE 2013 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) Spacer between centered title and PACKAGE CHARACTERISTICS table PACKAGE CHARACTERISTICS PARAMETER TEST CONDITIONS (1) UNIT 8.1 mm 0.
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ISO5500 SLLSE64C – SEPTEMBER 2011 – REVISED JUNE 2013 www.ti.com BEHAVIORAL MODEL Figure 53 and Figure 54 show the detailed behavioral model of the ISO5500 for a non-inverting input configuration and its corresponding timing diagram for normal operation, fault condition, and Reset. +HV ISO5500 DESAT + 1 VIN+ PWM DIS - ISO CBLK 7.2V 270 μA 2 VIN- 3 VCC1 DELAY 3.3V to 5V VCC2 - UVLO ISO - Barrie r μC + 13 VREG 12.
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ISO5500 www.ti.com SLLSE64C – SEPTEMBER 2011 – REVISED JUNE 2013 DEVICE INFORMATION POWER SUPPLIES VCC1 and GND1 are the power supply input and output for the input side of the ISO5500. The supply voltage at VCC1 can range from 3 V up to 5.5 V with respect to GND1, thus supporting the direct interface to state-of-the-art 3.3 V low-power controllers as well as legacy 5 V controllers. VCC2, VEE-P and VEE-L are the power supply input and supply returns for the output side of the ISO5500.
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ISO5500 SLLSE64C – SEPTEMBER 2011 – REVISED JUNE 2013 www.ti.com OUTPUT STAGE The output stage provides the actual IGBT gate drive by switching the output voltage pin, VOUT, between the most positive potential, typically VCC2, and the most negative potential, VEE-P. VCC2 ISO5500 VC VIN+ Q1b 15V Q1a 30V On VOUT VOUT Gate Drive Q1 Q3 Q2 VE Q3 Slow Off Q2 0V VGE Off Q1 Q2b +15V Q2a 15V VE VEE-P VE VGE -15V VEE-L Figure 57.
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ISO5500 www.ti.com SLLSE64C – SEPTEMBER 2011 – REVISED JUNE 2013 VCC2 UVLO On 11.1V 2V VC + 12.3V VCC2 - 15V VIN+ Gate Drive 12.3V Q1b Q1a VOUT VGE VE Failsafe Low VOUT Q1 Q2 Q1 Q2 Q1 0V R PD Q2 Off Q2b ISO5500 15V Q2a VE VEE-P +15V VE VGE VEE-L -15V Figure 58. Under Voltage Lockout (UVLO) Function Because VCC2 with respect to VE represents the gate-on voltage, VGE-ON = VCC2 – VE, the UVLO comparator compares VCC2 to a 12.
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ISO5500 SLLSE64C – SEPTEMBER 2011 – REVISED JUNE 2013 www.ti.com VCC2 VC ISO5500 15V DESAT + VIN+ DESAT - CBLK On Gate Drive 7.2V VDESAT Q4 Q1a Q1b VOUT Dschg 7.2V VCE Q4 VOUT VE Fault Off Slow Off Q3 Q2b 15V Q2a Fault VEE-P VEE-L Figure 59. DESAT Fault Detection and Protection The DESAT fault detection involves a comparator that monitors the IGBT’s VCE and compares it to an internal 7.2 V reference.
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ISO5500 www.ti.com SLLSE64C – SEPTEMBER 2011 – REVISED JUNE 2013 The timing diagram in Figure 59 shows the DESAT function for both, normal operation and a short-circuit fault condition. The use of VIN+ as control input implies non-inverting input configuration. During normal operation VDESAT will display a small sawtooth waveform every time VIN+ goes high. The ramp of the sawtooth is caused by the internal current source charging the blanking capacitor.
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ISO5500 SLLSE64C – SEPTEMBER 2011 – REVISED JUNE 2013 www.ti.com APPLICATION INFORMATION TYPICAL APPLICATION Figure 61 shows the typical application of a three-phase inverter using six ISO5500 isolated gate drivers. Threephase inverters are used for variable-frequency drives to control the operating speed of AC motors and for high power applications such as High-Voltage DC (HVDC) power transmission.
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ISO5500 www.ti.com SLLSE64C – SEPTEMBER 2011 – REVISED JUNE 2013 1 2 3 μC 3.3V 3.3 kΩ 0.1 μF 4 5 6 330 pF 7 8 ISO5500 V IN+ V IN- VE VEE -L DESAT V CC1 GND1 V CC2 RESET VC FAULT VOUT NC VEE -L GND1 V EE-P 16 15 100 0.1 pF μF 0.1 μF DS (opt.) 100 Ω 14 D DESAT + 13 12 VF Q1 4.7 μF + 15V VCE Rg 11 - 0.1 μF 10 Q2 15V 3-PHASE OUTPUT + 9 VCE - Figure 62. Recommended Application Circuit FAULT PIN CIRCUITRY The FAULT pin is an open-drain output requiring a 3.
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ISO5500 SLLSE64C – SEPTEMBER 2011 – REVISED JUNE 2013 www.ti.com LOCAL SHUTDOWN AND RESET In applications with local shutdown and reset, the FAULT output of each gate driver is polled separately, and the individual reset lines are asserted low independently to reset the motor controller after a fault condition. 1 2 3 µC 4 RF 5 6 7 8 VIN+ 1 ISO5500 2 VIN- 3 VCC1 µC GND1 4 RF 5 RESET 6 FAULT 7 NC 8 GND1 VIN+ ISO5500 VINVCC1 GND1 RESET FAULT NC GND1 Figure 64.
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ISO5500 www.ti.com SLLSE64C – SEPTEMBER 2011 – REVISED JUNE 2013 1 2 3 µC 4 5 6 7 8 VIN+ 1 ISO5500 2 VIN- 3 VCC1 µC GND1 4 5 RESET 6 FAULT 7 NC 8 GND1 VIN+ ISO5500 VINVCC1 GND1 RESET FAULT NC GND1 Figure 66. Auto Reset for Non-inverting and Inverting Input Configuration RESETTING FOLLOWING A FAULT CONDITION To resume normal switching operation following a fault condition (FAULT output low), the gate control signal must be driven into a 'gate low' state before asserting RESET low.
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ISO5500 SLLSE64C – SEPTEMBER 2011 – REVISED JUNE 2013 ISO5500 VE VEE-L DESAT VCC2 VC VOUT www.ti.com 16 100 pF 15 DS (opt.) RS 14 DDESAT - 13 12 15V VFW-inst Rg 11 VEE-L 10 VEE-P + VFW + 15V 9 Figure 68.
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ISO5500 www.ti.com SLLSE64C – SEPTEMBER 2011 – REVISED JUNE 2013 DETERMINING THE MAXIMUM AVAILABLE, DYNAMIC OUTPUT POWER, POD-max The ISO5500 total power consumption of PD = 592 mW consists of the total input power, PID, the total output power, POD, and the output power under load, POL: PD = PID + POD + POL With: PID = VCC1-max × ICC1-max = 5.5 V × 8.5 mA = 47 mW, and: POD = (VCC2 – VEE-P) x ICC2-q = 30 V × 14 mA = 420 mW, then: POL = PD – PID – POD = 592 mW – 47 mW – 420 mW = 125 mW.
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ISO5500 SLLSE64C – SEPTEMBER 2011 – REVISED JUNE 2013 www.ti.com DETERMINING GATE RESISTOR, RG The value of the gate resistor determines the peak charge and discharge currents, ION-PK and IOFF-PK. Due to the transient nature of these currents, their peak values only occur during the on-to-off and off-to-on transitions of the gate voltage. In order to calculate RG for the maximum peak current, ron and roff must be assumed zero. The resulting charge and discharge models are shown in Figure 70.
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ISO5500 www.ti.com SLLSE64C – SEPTEMBER 2011 – REVISED JUNE 2013 DETERMINING COLLECTOR RESISTOR, RC Despite equal charge and discharge currents, many power devices possess longer turn-off propagation and fall times than turn-on propagation and rise times. In order to compensate for the difference in switching times, it might be necessary to significantly reduce the charge current, ION-PK, versus the discharge current, IOFF-PK.
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ISO5500 SLLSE64C – SEPTEMBER 2011 – REVISED JUNE 2013 www.ti.com HIGHER OUTPUT CURRENT USING AN EXTERNAL CURRENT BUFFER To increase the IGBT gate drive current, a non-inverting current buffer (such as the npn/pnp buffer shown in Figure 72) may be used. Inverting types are not compatible with the desaturation fault protection circuitry and must be avoided. The MJD44H11/MJD45H11 pair is appropriate for currents up to 8 A, the D44VH10/ D45VH10 pair for up to 15 A maximum.
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ISO5500 www.ti.com SLLSE64C – SEPTEMBER 2011 – REVISED JUNE 2013 REVISION HISTORY Changes from Original (September 2011) to Revision A • Page Changed the device From: Product Preview To: Production ................................................................................................ 1 Changes from Revision A (July 2012) to Revision B Page • Changed the Regulatory Approvals List ................................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 9-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device ISO5500DWR Package Package Pins Type Drawing SOIC DW 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 10.75 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.7 2.7 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 9-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ISO5500DWR SOIC DW 16 2000 367.0 367.0 38.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.