Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsLinear IC - Op-amp Transimpedance SOIC 14

IVC102

11 12 13

Digital

Ground

Analog

Ground

Logic Low closes switches

V+

V–

Ionization

Chamber

Photodiode

60pF

30pF

10pF

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PRECISION SWITCHED INTEGRATOR

TRANSIMPEDANCE AMPLIFIER

APPLICATIONS

● PRECISION LOW CURRENT MEASUREMENT

● PHOTODIODE MEASUREMENTS

● IONIZATION CHAMBER MEASUREMENTS

● CURRENT/CHARGE-OUTPUT SENSORS

● LEAKAGE CURRENT MEASUREMENT

IVC102

FEATURES

● ON-CHIP INTEGRATING CAPACITORS

● GAIN PROGRAMMED BY TIMING

● LOW INPUT BIAS CURRENT: 750fA max

● LOW NOISE

● LOW SWITCH CHARGE INJECTION

● FAST PULSE INTEGRATION

● LOW NONLINEARITY: 0.005% typ

● 14-PIN DIP, SO-14 SURFACE MOUNT

DESCRIPTION

The IVC102 is a precision integrating amplifier with

FET op amp, integrating capacitors, and low leakage

FET switches. It integrates low-level input current for

a user-determined period, storing the resulting voltage

on the integrating capacitor. The output voltage can be

held for accurate measurement. The IVC102 provides

a precision, lower noise alternative to conventional

transimpedance op amp circuits that require a very

high value feedback resistor.

The IVC102 is ideal for amplifying low-level sensor

currents from photodiodes and ionization chambers.

The input signal current can be positive or negative.

TTL/CMOS-compatible timing inputs control the inte-

gration period, hold and reset functions to set the

effective transimpedance gain and to reset (discharge)

the integrator capacitor.

Package options include 14-Pin plastic DIP and SO-14

surface-mount packages. Both are specified for the

–40°C to 85°C industrial temperature range.

Hold Integrate Hold Reset

Positive or Negative

Signal Integration

(t)

V

–1

∫

INT

SBFS009

Summary of content (14 pages)

PAGE 1
IVC102 ® PRECISION SWITCHED INTEGRATOR TRANSIMPEDANCE AMPLIFIER APPLICATIONS DESCRIPTION ● PRECISION LOW CURRENT MEASUREMENT The IVC102 is a precision integrating amplifier with FET op amp, integrating capacitors, and low leakage FET switches. It integrates low-level input current for a user-determined period, storing the resulting voltage on the integrating capacitor. The output voltage can be held for accurate measurement.
PAGE 2
SPECIFICATIONS At TA = +25°C, VS = ±15V, RL = 2kΩ, C INT = C1 + C2 + C3 , 1ms integration period(1), unless otherwise specified. IVC102P, U PARAMETER CONDITIONS TRANSFER FUNCTION Gain Error vs Temperature Nonlinearity Input Current Range Offset Voltage(2) vs Temperature vs Power Supply Droop Rate, Hold Mode OP AMP Input Bias Current vs Temperature Offset Voltage (Op Amp VOS) vs Temperature vs Power Supply Noise Voltage VO = ±10V IIN = 0, CIN = 50pF VS = +4.
PAGE 3
ELECTROSTATIC DISCHARGE SENSITIVITY ABSOLUTE MAXIMUM RATINGS Supply Voltage, V+ to V– .................................................................... 36V Logic Input Voltage ...................................................................... V– to V+ Output Short Circuit to Ground ............................................... Continuous Operating Temperature ................................................. –40°C to +125°C Storage Temperature .....................................................
PAGE 4
TYPICAL PERFORMANCE CURVES At TA = +25°C, VS = ±15V, RL = 2kΩ, C INT = C1 + C2 + C3 , 1ms integration period, unless otherwise specified. INPUT BIAS CURRENT vs TEMPERATURE TOTAL OUTPUT NOISE vs CIN 100p 1000 rms Variation of 100 Measurement Cycles, TINT = 1ms. Noise Voltage (µVrms) Input Bias Current (A) S1, S2 Open 10p 1p 100f CINT = 10pF CINT = 30pF 100 CINT = 100pF CINT = 300pF CINT = 1000pF 10 Reset Mode, S1 Open, S2 Closed.
PAGE 5
APPLICATION INFORMATION BASIC RESET-AND-INTEGRATE MEASUREMENT Figure 1 shows the circuit and timing for a simple reset-andintegrate measurement. The input current is connected directly to the inverting input of the IVC102, pin 3. Input current is shown flowing out of pin 3, which produces a positive-going ramp at VO. Current flowing into pin 3 would produce a negative-going ramp. Figure 1 shows the basic circuit connections to operate the IVC102.
PAGE 6
measurement from the final sample at T2. Op amp offset voltage, charge injection effects and I•RS2 offset voltage on S2 are removed with this two-point measurement. The effective integration period is the time between the two measurements, T2-T1. In addition, the offset voltage of the internal op amp and charge injection of S2 contribute to the voltage on CINT at the start of integration.
PAGE 7
V+ +15V 0.1µF 3a C3 6 C2 5 4 Photodiode Sensor C1 14 60pF 30pF 10pF S2 3 2 I R C 10 S1 1 VO 9 A/D Converter Digital Data 0.1µF 11 I: Signal - Dependent Current R: Sensor Resistance C: Sensor Capacitance S1 12 S2 13 –15V V– See timing signals below Effective Signal Integration Period, TS A 3b 0V 0V VO waveform with approx. half-scale input current. Charge transferred from sensor C to CINT. VO (S1 Open) S1 (S1 Closed) (S2 Open) S2 10µs Hold 10µs 10µs Reset Pre-Int.
PAGE 8
OFFSET ERRORS The input current, IIN, is shown as a conventional current flowing into pin 2 in this diagram but the input current could be bipolar (positive or negative). Current flowing out of pin 2 would produce a positive-ramping VO. Figure 3c shows the effect on VO due to op amp input offset voltage, input bias current and switch charge injection. It assumes zero input current from the sensor.
PAGE 9
INPUT BIAS CURRENT ERRORS CHOOSING CINT Careful circuit board layout and assembly techniques are required to achieve the very low input bias current capability of the IVC102. The critical input connections are at ground potential, so analog ground should be used as a circuit board guard trace surrounding all critical nodes. These include pins 2, 3, 4, 5 and 6. See Figure 4. Internal capacitors C1, C2 and C3 are high quality metal/ oxide types with low leakage and excellent dielectric characteristics.
PAGE 10
Slew rate limit of the internal op amp is approximately 3V/µs. For most applications, the slew rate of VOUT should be limited to 1V/µs or less. The rate of change is proportional to IIN and inversely proportional to CINT: Frequency Response (dB) 0 –10 –20dB/decade slope Corner at f = 0.32/TINT Slew Rate = –20 –3dB at f = 0.44/TINT –30 –40 This can be important in some applications since the slewinduced input voltage is applied to the sensor or signal source.
PAGE 11
PACKAGE OPTION ADDENDUM www.ti.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device IVC102U/2K5 Package Package Pins Type Drawing SOIC D 14 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 6.5 B0 (mm) K0 (mm) P1 (mm) 9.0 2.1 8.0 W Pin1 (mm) Quadrant 16.
PAGE 13
PACKAGE MATERIALS INFORMATION www.ti.com 24-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) IVC102U/2K5 SOIC D 14 2500 367.0 367.0 38.
PAGE 14
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.