LF198,LF198A,LF298,LF398,LF398A LF198/LF298/LF398, LF198A/LF398A Monolithic Sample-and-Hold Circuits Literature Number: SNOSBI3A
LF198/LF298/LF398, LF198A/LF398A Monolithic Sample-and-Hold Circuits General Description Features The LF198/LF298/LF398 are monolithic sample-and-hold circuits which utilize BI-FET technology to obtain ultra-high dc accuracy with fast acquisition of signal and low droop rate. Operating as a unity gain follower, dc gain accuracy is 0.002% typical and acquisition time is as low as 6 µs to 0.01%. A bipolar input stage is used to achieve low offset voltage and wide bandwidth.
LF198/LF298/LF398, LF198A/LF398A Absolute Maximum Ratings (Note 1) Hold Capacitor Short Circuit Duration Lead Temperature (Note 4) H package (Soldering, 10 sec.) N package (Soldering, 10 sec.) M package: Vapor Phase (60 sec.) Infrared (15 sec.
Parameter Conditions LF198A Min Input Impedance Gain Error Typ Tj = 25˚C 1010 Tj = 25˚C, RL = 10k 0.002 Full Temperature Range Feedthrough Attenuation Ratio LF398A Max Min Units Typ Max Ω 1010 0.005 0.004 0.005 0.01 Tj = 25˚C, Ch = 0.01 µF 86 96 0.01 86 90 % % dB at 1 kHz Output Impedance Tj = 25˚C, “HOLD” mode 0.5 Full Temperature Range “HOLD” Step, (Note 6) 1 0.5 4 1 Ω 6 Ω Tj = 25˚C, Ch = 0.01µF, VOUT = 0 0.5 1 1.0 1 mV Supply Current, (Note 5) Tj≥25˚C 4.5 5.
LF198/LF298/LF398, LF198A/LF398A Typical Performance Characteristics Output Droop Rate (Continued) Hold Step “Hold” Settling Time (Note 10) DS005692-21 DS005692-20 DS005692-22 Leakage Current into Hold Capacitor Phase and Gain (Input to Output, Small Signal) DS005692-25 DS005692-23 Power Supply Rejection DS005692-24 Output Short Circuit Current DS005692-27 DS005692-26 Note 10: See Definition www.national.
Input Bias Current (Continued) Feedthrough Rejection Ratio (Hold Mode) Hold Step vs Input Voltage DS005692-31 DS005692-29 DS005692-30 Output Transient at Start of Sample Mode Output Transient at Start of Hold Mode DS005692-12 DS005692-13 Logic Input Configurations TTL & CMOS 3V ≤ VLOGIC (Hi State) ≤ 7V DS005692-33 Threshold = 1.4V DS005692-34 Threshold = 1.4V *Select for 2.8V at pin 8 5 www.national.
LF198/LF298/LF398, LF198A/LF398A Logic Input Configurations (Continued) CMOS 7V ≤ VLOGIC (Hi State) ≤ 15V DS005692-35 Threshold = 0.6 (V+) + 1.4V DS005692-36 Threshold = 0.6 (V+) − 1.4V Op Amp Drive DS005692-37 Threshold ≈ +4V DS005692-38 Threshold = −4V Application Hints Hold Capacitor Hold step, acquisition time, and droop rate are the major trade-offs in the selection of a hold capacitor value. Size and cost may also become important for larger values.
LF198/LF298/LF398, LF198A/LF398A Application Hints (Continued) Guarding Technique logic input for signal delay, calculate the slope of the waveform at the threshold point to ensure that it is at least 1.0 V/µs. Sampling Dynamic Signals Sample error to moving input signals probably causes more confusion among sample-and-hold users than any other parameter.
LF198/LF298/LF398, LF198A/LF398A Typical Applications X1000 Sample & Hold Sample and Difference Circuit (Output Follows Input in Hold Mode) DS005692-40 VOUT = VB + ∆VIN(HOLD MODE) DS005692-39 *For lower gains, the LM108 must be frequency compensated Ramp Generator with Variable Reset Level Integrator with Programmable Reset Level DS005692-42 DS005692-43 www.national.
LF198/LF298/LF398, LF198A/LF398A Typical Applications (Continued) Output Holds at Average of Sampled Input Increased Slew Current DS005692-46 DS005692-47 Reset Stabilized Amplifier (Gain of 1000) Fast Acquisition, Low Droop Sample & Hold DS005692-49 DS005692-50 9 www.national.
LF198/LF298/LF398, LF198A/LF398A Typical Applications (Continued) Synchronous Correlator for Recovering Signals Below Noise Level 2–Channel Switch DS005692-53 A B Gain 1 ± 0.02% 1 ± 0.2% ZIN 1010Ω 47 kΩ BW . 1 MHz . 400 kHz Crosstalk −90 dB −90 dB ≤ 6 mV ≤ 75 mV @ 1 kHz Offset DS005692-52 DC & AC Zeroing Staircase Generator DS005692-59 DS005692-55 *Select for step height 50k → ≅ 1V Step www.national.
LF198/LF298/LF398, LF198A/LF398A Typical Applications (Continued) Differential Hold Capacitor Hysteresis Compensation DS005692-56 DS005692-57 **Adjust for amplitude Definition of Terms Hold Settling Time: The time required for the output to settle within 1 mV of final value after the “hold” logic command. Dynamic Sampling Error: The error introduced into the held output due to a changing analog input at the time the hold command is given.
LF198/LF298/LF398, LF198A/LF398A Physical Dimensions inches (millimeters) unless otherwise noted Metal Can Package (H) Order Number LF198H, LF298H, LF398H, LF198AH or LF398AH NS Package Number H08C Molded Small-Outline Package (M) Order Number LF298M or LF398M NS Package Number M14A www.national.
inches (millimeters) unless otherwise noted (Continued) Molded Dual-In-Line Package (N) Order Number LF398N or LF398AN NS Package Number N08E LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1.
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