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LF412-N

www.ti.com

SNOSBH7E –APRIL 1999–REVISED MARCH 2013

LF412 Low Offset, Low Drift Dual JFET Input Operational Amplifier

Check for Samples: LF412-N

FEATURES

DESCRIPTION

These devices are low cost, high speed, JFET input

• Internally Trimmed Offset Voltage: 1 mV (max)

operational amplifiers with very low input offset

• Input Offset Voltage Drift: 10 µV/°C (max)

voltage and guaranteed input offset voltage drift.

• Low Input Bias Current: 50 pA

They require low supply current yet maintain a large

gain bandwidth product and fast slew rate. In

• Low Input Noise Current: 0.01 pA / √Hz

addition, well matched high voltage JFET input

• Wide Gain Bandwidth: 3 MHz (min)

devices provide very low input bias and offset

• High Slew Rate: 10V/µs (min)

currents. The LF412 dual is pin compatible with the

LM1558, allowing designers to immediately upgrade

• Low Supply Current: 1.8 mA/Amplifier

the overall performance of existing designs.

• High Input Impedance: 10

These amplifiers may be used in applications such as

• Low Total Harmonic Distortion: ≤0.02%

high speed integrators, fast D/A converters, sample

• Low 1/f Noise Corner: 50 Hz

and hold circuits and many other circuits requiring low

• Fast Settling Time to 0.01%: 2 µs

input offset voltage and drift, low input bias current,

high input impedance, high slew rate and wide

bandwidth.

Typical Connection

Figure 1.

Connection Diagram

Figure 2. TO Package – Top View

See Package Number NEV0008A

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2BI-FET II is a trademark of Texas Instruments.

3All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (17 pages)

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LF412-N www.ti.com SNOSBH7E – APRIL 1999 – REVISED MARCH 2013 LF412 Low Offset, Low Drift Dual JFET Input Operational Amplifier Check for Samples: LF412-N FEATURES DESCRIPTION • • • • • • • • • • • These devices are low cost, high speed, JFET input operational amplifiers with very low input offset voltage and guaranteed input offset voltage drift. They require low supply current yet maintain a large gain bandwidth product and fast slew rate.
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LF412-N SNOSBH7E – APRIL 1999 – REVISED MARCH 2013 www.ti.com Figure 3. PDIP/CDIP Package – Top View See Package Number P0008E or NAB0008A Simplified Schematic (1) Available per JM38510/11905 Figure 4.
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LF412-N www.ti.com SNOSBH7E – APRIL 1999 – REVISED MARCH 2013 Detailed Schematic Figure 5. These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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LF412-N SNOSBH7E – APRIL 1999 – REVISED MARCH 2013 Absolute Maximum Ratings www.ti.com (1) (2) LF412A LF412 Supply Voltage ±22V ±18V Differential Input Voltage ±38V ±30V Continuous Continuous TO Package PDIP Package Input voltage Range (3) Output Short Circuit Duration Power Dissipation (4) (5) See Tj max θjA (Typical) Operating Temp. Range Storage Temp.
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LF412-N www.ti.
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LF412-N SNOSBH7E – APRIL 1999 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics 6 Input Bias Current Input Bias Current Figure 6. Figure 7. Supply Current Positive Common-Mode Input Voltage Limit Figure 8. Figure 9. Negative Common-Mode Input Voltage Limit Positive Current Limit Figure 10. Figure 11.
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LF412-N www.ti.com SNOSBH7E – APRIL 1999 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Negative Current Limit Output Voltage Swing Figure 12. Figure 13. Output Voltage Swing Gain Bandwidth Figure 14. Figure 15. Bode Plot Slew Rate Figure 16. Figure 17.
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LF412-N SNOSBH7E – APRIL 1999 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) 8 Distortion vs Frequency Undistorted Output Voltage Swing Figure 18. Figure 19. Open Loop Frequency Response Common-Mode Rejection Ratio Figure 20. Figure 21. Power Supply Rejection Ratio Equivalent Input Noise Voltage Figure 22. Figure 23.
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LF412-N www.ti.com SNOSBH7E – APRIL 1999 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Open Loop Voltage Gain Output Impedance Figure 24. Figure 25. Inverter Settling Time Figure 26. PULSE RESPONSE RL=2 kΩ, CL=10 pF Figure 27. Small Signal Inverting Figure 28.
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LF412-N SNOSBH7E – APRIL 1999 – REVISED MARCH 2013 www.ti.com Figure 29. Large Signal Inverting Figure 30. Large Signal Non-Inverting Figure 31. Current Limit (RL=100Ω) APPLICATION HINTS The LF412 series of JFET input dual op amps are internally trimmed (BI-FET II™) providing very low input offset voltages and guaranteed input offset voltage drift. These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need for clamps across the inputs.
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LF412-N www.ti.com SNOSBH7E – APRIL 1999 – REVISED MARCH 2013 A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and capacitance from the input of the device (usually the inverting input) to AC ground set the frequency of the pole. In many instances the frequency of this pole is much greater than the expected 3 dB frequency of the closed loop gain and consequently there is negligible effect on stability margin.
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LF412-N SNOSBH7E – APRIL 1999 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision D (March 2013) to Revision E • 12 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
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MECHANICAL DATA NEV0008A LMC0008A H08A (REV C) www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.