Datasheet

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LM12L458

www.ti.com

SNAS085B –JULY 1999–REVISED MARCH 2013

LM12L458 12-Bit + Sign Data Acquisition System with Self-Calibration

Check for Samples: LM12L458

FEATURES

DESCRIPTION

The LM12L458 is a highly integrated 3.3V Data

• Three Operating Modes: 12-Bit + Sign, 8-Bit +

Acquisition System. It combines a fully-differential

Sign, and “Watchdog”

self-calibrating (correcting linearity and zero errors)

• Single-Ended or Differential Inputs

13-bit (12-bit + sign) analog-to-digital converter (ADC)

• Built-In Sample-and-Hold

and sample-and-hold (S/H) with extensive analog

functions and digital functionality. Up to 32

• Instruction RAM and Event Sequencer

consecutive conversions, using two's complement

• 8-Channel Multiplexer

format, can be stored in an internal 32-word (16-bit

• 32-Word Conversion FIFO

wide) FIFO data buffer. An internal 8-word RAM can

store the conversion sequence for up to eight

• Programmable Acquisition Times and

acquisitions through the LM12L458's eight-input

Conversion Rates

multiplexer. The LM12L458 can also operate with 8-

• Self-Calibration and Diagnostic Mode

bit + sign resolution and in a supervisory “watchdog”

• 8- or 16-Bit Wide Data Bus Microprocessor or

mode that compares an input signal against two

DSP Interface programmable limits. Programmable acquisition times

and conversion rates are possible through the use of

• CMOS Compatible I/O

internal clock-driven timers.

APPLICATIONS

All registers, RAM, and FIFO are directly addressable

through the high speed microprocessor interface to

• Data Logging

either an 8-bit or 16-bit data bus. The LM12L458

• Process Control

includes a direct memory access (DMA) interface for

high-speed conversion data transfer.

• Energy Management

• Medical Instrumentation

Additional applications information can be found in

applications notes AN-906 (JAJA265), AN-947

KEY SPECIFICATIONS

(SNAA012), and AN-949 (SNAA013).

• (f

CLK

= 6 MHz)

• Resolution: 12-Bit + Sign or 8-Bit + Sign

• Single Supply: +3 to +5.5 V

• 13-bit Conversion Time: 7.3 μs

• 9-bit Conversion Time: 3.5 μs

• 13-bit Through-Put Rate: 106 k Samples/s

(Min)

• Comparison Time (“Watchdog” Mode): 1.8 μs

(Max)

• ILE: ±1 LSB (Max)

• Power Consumption: 15 mW (max)

• Stand-By Mode: 5 μW (typ)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (38 pages)

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LM12L458 www.ti.com SNAS085B – JULY 1999 – REVISED MARCH 2013 LM12L458 12-Bit + Sign Data Acquisition System with Self-Calibration Check for Samples: LM12L458 FEATURES DESCRIPTION • The LM12L458 is a highly integrated 3.3V Data Acquisition System. It combines a fully-differential self-calibrating (correcting linearity and zero errors) 13-bit (12-bit + sign) analog-to-digital converter (ADC) and sample-and-hold (S/H) with extensive analog functions and digital functionality.
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LM12L458 SNAS085B – JULY 1999 – REVISED MARCH 2013 www.ti.com Connection Diagram *Pin names in ( ) apply to the obsolete LM12L454, shown for reference only. Figure 1. Connection Diagram Functional Diagram Figure 2. LM12L458 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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LM12L458 www.ti.com SNAS085B – JULY 1999 – REVISED MARCH 2013 Absolute Maximum Ratings (1) (2) Supply Voltage (VA+ and VD+) 6.0V −0.3V to (V+ + 0.3V) Voltage at Input and Output Pins, except analog inputs − 5V to (V+ + 5V) Voltage at Analog Inputs |(VA+) − (VD+)| Input Current at Any Pin 300 mV (3) ±5 mA Package Input Current (3) ±20 mA Power Consumption (TA = 25°C) (4) 875 mW −65°C to +150°C Storage Temperature Lead Temperature, Infrared, 15 sec.
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LM12L458 SNAS085B – JULY 1999 – REVISED MARCH 2013 www.ti.com Converter Characteristics The following specifications apply for VA+ = VD+ = +3.3V, VREF+ = +2.5V, VREF− = 0V, 12-bit + sign conversion mode, fCLK = 6.0 MHz, RS = 25Ω, source impedance for VREF+ and VREF− ≤ 25Ω, fully-differential input with fixed 1.25V common-mode voltage, and minimum acquisition time unless otherwise specified.
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LM12L458 www.ti.com SNAS085B – JULY 1999 – REVISED MARCH 2013 Converter Characteristics (continued) The following specifications apply for VA+ = VD+ = +3.3V, VREF+ = +2.5V, VREF− = 0V, 12-bit + sign conversion mode, fCLK = 6.0 MHz, RS = 25Ω, source impedance for VREF+ and VREF− ≤ 25Ω, fully-differential input with fixed 1.25V common-mode voltage, and minimum acquisition time unless otherwise specified.
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LM12L458 SNAS085B – JULY 1999 – REVISED MARCH 2013 www.ti.com DC Characteristics The following specifications apply for VA+ = VD+ = +3.3V, VREF+ = +2.5V, VREF− = 0V, fCLK = 6.0 MHz and minimum acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C. (1) (2) (3) Symbol Parameter Conditions ID+ VD+ Supply Current CS = “1” IA+ VA+ Supply Current CS = “1” IST Stand-By Supply Current (ID+ + IA+) Power-Down Mode Selected 3.
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LM12L458 www.ti.com SNAS085B – JULY 1999 – REVISED MARCH 2013 Digital Characteristics The following specifications apply for VA+ = VD+ = +3.3V, unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C. (1) (2) (3) Symbol Parameter Conditions Typical (4) Limits (5) Units VIN(1) Logical “1” Input Voltage VA+ = VD+ = +3.6V 2.0 V (min) VIN(0) Logical “0” Input Voltage VA+ = VD+ = +3.0V ALE, Pin 22 0.7 0.
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LM12L458 SNAS085B – JULY 1999 – REVISED MARCH 2013 www.ti.com Digital Timing Characteristics (continued) The following specifications apply for VA+ = VD+ = +3.3V, tr = tf = 3 ns, and CL = 100 pF on data I/O, INT and DMARQ lines unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25°C.
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LM12L458 www.ti.com SNAS085B – JULY 1999 – REVISED MARCH 2013 Input and Reference Range VREF = VREF+ − VREF− VIN = VIN+ − VIN− GND ≤ VIN+ ≤ VA+ GND ≤ VIN− ≤ VA+ Figure 5. The General Case of Output Digital Code vs.
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LM12L458 SNAS085B – JULY 1999 – REVISED MARCH 2013 www.ti.com VREF+ − VREF− = 2.5V VIN = VIN+ − VIN− GND ≤ VIN+ ≤ VA+ GND ≤ VIN− ≤ VA+ Figure 6. Specific Case of Output Digital Code vs. the Operating Input Voltage Range for VREF = 2.5V Figure 7.
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LM12L458 www.ti.com SNAS085B – JULY 1999 – REVISED MARCH 2013 Figure 8. The Specific Case of the VREF Operating Range for VA+ = 3.3V Transfer Characteristic and Static Errors Figure 9.
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LM12L458 SNAS085B – JULY 1999 – REVISED MARCH 2013 www.ti.com Figure 10. Simplified Error Curve vs. Output Code without Auto-Calibration or Auto-Zero Cycles Figure 11. Simplified Error Curve vs. Output Code after Auto-Calibration Cycle Figure 12.
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LM12L458 www.ti.com SNAS085B – JULY 1999 – REVISED MARCH 2013 Typical Performance Characteristics The following curves apply for 12-bit + sign mode after auto-calibration with VA+ = VD+ = +3.3V, VREF+ = +2.5V, VREF− = 0V, TA = 25°C, and fCLK = 6 MHz unless otherwise specified. The performance for 8-bit + sign and “watchdog” modes is equal to or better than shown. (1) (1) Linearity Error Change vs. Clock Frequency Linearity Error Change vs. Temperature Figure 13. Figure 14. Linearity Error Change vs.
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LM12L458 SNAS085B – JULY 1999 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) The following curves apply for 12-bit + sign mode after auto-calibration with VA+ = VD+ = +3.3V, VREF+ = +2.5V, VREF− = 0V, TA = 25°C, and fCLK = 6 MHz unless otherwise specified. The performance for 8-bit + sign and “watchdog” modes is equal to or better than shown. (1) 14 Full-Scale Error Change vs. Reference Voltage Full-Scale Error vs. Supply Voltage Figure 19. Figure 20.
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LM12L458 www.ti.com SNAS085B – JULY 1999 – REVISED MARCH 2013 Typical Performance Characteristics (continued) The following curves apply for 12-bit + sign mode after auto-calibration with VA+ = VD+ = +3.3V, VREF+ = +2.5V, VREF− = 0V, TA = 25°C, and fCLK = 6 MHz unless otherwise specified. The performance for 8-bit + sign and “watchdog” modes is equal to or better than shown. (1) Analog Supply Current vs. Temperature Digital Supply Current vs. Clock Frequency Figure 25. Figure 26.
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LM12L458 SNAS085B – JULY 1999 – REVISED MARCH 2013 www.ti.com Timing Diagrams VA+ = VD+ = +3.3V, tR = tF = 3 ns, CL = 100 pF for the INT, DMARQ, D0–D15 outputs. Figure 28. Multiplexed Data Bus 1, 3: CS or Address valid to ALE low set-up time. 11: WR pulse width 2, 4: CS or Address valid to ALE low hold time.
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LM12L458 www.ti.com SNAS085B – JULY 1999 – REVISED MARCH 2013 Figure 29.
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LM12L458 SNAS085B – JULY 1999 – REVISED MARCH 2013 www.ti.com PIN DESCRIPTIONS VA+, VD+ Analog and digital supply voltage pins. The LM12L458's supply voltage operating range is +3.0V to +5.5V. Accuracy is ensured only if VA+ and VD+ are connected to the same power supply. Each pin should have a parallel combination of 10 μF (electrolytic or tantalum) and 0.1 μF (ceramic) bypass capacitors connected between it and ground. D0–D15 The internal data input/output TRI-STATE buffers are connected to these pins.
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LM12L458 www.ti.com SNAS085B – JULY 1999 – REVISED MARCH 2013 or non-adjacent, can operate as a fully differential pair. VREF− This is the negative reference input. The LM12L458 operates with 0V ≤ VREF− ≤ VREF+. This pin should be bypassed to ground with a parallel combination of 10 μF and 0.1 μF (ceramic) capacitors. VREF+ Positive reference input. The LM12L458 operate with 0V ≤ VREF+ ≤ VA+. This pin should be bypassed to ground with a parallel combination of 10 μF and 0.1 μF (ceramic) capacitors. N.C.
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LM12L458 SNAS085B – JULY 1999 – REVISED MARCH 2013 www.ti.com Microprocessor overhead is reduced through the use of the internal conversion FIFO. Thirty-two consecutive conversions can be completed and stored in the FIFO without any microprocessor intervention. The microprocessor can, at any time, interrogate the FIFO and retrieve its contents. It can also wait for the LM12L458 to issue an interrupt when the FIFO is full or after any number (≤32) of conversions have been stored.
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LM12L458 www.ti.com SNAS085B – JULY 1999 – REVISED MARCH 2013 Bits 5–7 select which of the seven input channels (“001” to “111” for IN1 to IN7) will be configured as inverting inputs to the LM12L458's ADC. (See Table 4.) Fully differential operation is created by selecting two multiplexer channels, one operating in the non-inverting mode and the other operating in the inverting mode. A code of “000” selects ground as the inverting input for single ended operation. Bit 8 is the SYNC bit.
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LM12L458 SNAS085B – JULY 1999 – REVISED MARCH 2013 www.ti.com Table 2.
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LM12L458 www.ti.com SNAS085B – JULY 1999 – REVISED MARCH 2013 Table 3.
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LM12L458 SNAS085B – JULY 1999 – REVISED MARCH 2013 www.ti.com Instruction RAM “01” The second Instruction RAM section is selected by placing a “01” in Bits 8 and 9 of the Configuration register. Bits 0–7 hold “watchdog” limit #1.
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LM12L458 www.ti.com SNAS085B – JULY 1999 – REVISED MARCH 2013 Writing a “1” to Bit 3 initiates a complete calibration process that includes a “long” auto-zero offset voltage correction (this calibration averages eight samples of the comparator offset voltage when creating a correction coefficient) followed by an ADC linearity calibration. This complete calibration is started after the currently running instruction is completed if the Sequencer is running when Bit 3 is set to “1”.
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LM12L458 SNAS085B – JULY 1999 – REVISED MARCH 2013 www.ti.com Table 4.
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LM12L458 www.ti.com SNAS085B – JULY 1999 – REVISED MARCH 2013 Bit 5 enables an external interrupt when an internal Pause interrupt has been generated. Bit 6 is a “Don't Care”. Bit 7 enables an external interrupt when the LM12L458 return from power-down to active mode. Bits 8–10 form the storage location of the user-programmable value against which the Sequencer's address is compared.
PAGE 28
LM12L458 SNAS085B – JULY 1999 – REVISED MARCH 2013 www.ti.com Bits 0–7 show the Limit #1 status. Each bit will be set high (“1”) when the corresponding instruction's input voltage exceeds the threshold stored in the instruction's Limit #1 register. When, for example, instruction 3 is a “watchdog” operation (Bit 11 is set high) and the input for instruction 3 meets the magnitude and/or polarity data stored in instruction 3's Limit #1 register, Bit 3 in the Limit Status register will be set to a “1”.
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LM12L458 www.ti.com SNAS085B – JULY 1999 – REVISED MARCH 2013 Bits 13–15 hold either the instruction responsible for the associated conversion data or the sign bit. Either mode is selected with Bit 5 in the Configuration register. Using the FIFO's full depth is achieved as follows. Set the value of the Interrupt Enable registers's Bits 11–15 to 1111 and the Interrupt Enable register's Bit 2 to a “1”. This generates an external interrupt when the 31st conversion is stored in the FIFO.
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LM12L458 SNAS085B – JULY 1999 – REVISED MARCH 2013 www.ti.com State 5: Perform a conversion or second comparison. This state takes 44 clock cycles when using the 12-bit + sign mode or 21 clock cycles when using the 8-bit + sign mode. The “watchdog” mode takes 5 clock cycles. Figure 31.
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LM12L458 www.ti.com SNAS085B – JULY 1999 – REVISED MARCH 2013 Analog Considerations REFERENCE VOLTAGE The difference in the voltages applied to the VREF+ and VREF− defines the analog input voltage span (the difference between the voltages applied between two multiplexer inputs or the voltage applied to one of the multiplexer inputs and analog ground), over which 4095 positive and 4096 negative codes exist. The voltage sources driving VREF+ or VREF− must have very low output impedance and noise.
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LM12L458 SNAS085B – JULY 1999 – REVISED MARCH 2013 www.ti.com POWER SUPPLIES Noise spikes on the VA+ and VD+ supply lines can cause conversion errors; the comparator will respond to the noise. The ADC is especially sensitive to any power supply spikes that occur during the auto-zero or linearity correction. Low inductance tantalum capacitors of 10 μF or greater paralleled with 0.1 μF monolithic ceramic capacitors are recommended for supply bypassing.
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LM12L458 www.ti.com SNAS085B – JULY 1999 – REVISED MARCH 2013 Excessive output capacitance on the digital lines. The current required to charge the capacitance on the digital outputs can cause noise on the supply bus within the LM12L458, causing internal supply "bounce" even when the external supply pin is pretty stable. The current required to discharge the output capacitance can cause die ground "bounce". Either of these can cause noise to be induced at the analog inputs, resulting in conversion errors.
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LM12L458 SNAS085B – JULY 1999 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision A (March 2013) to Revision B • 34 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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MECHANICAL DATA MPLC004A – OCTOBER 1994 FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER 20 PIN SHOWN Seating Plane 0.004 (0,10) 0.180 (4,57) MAX 0.120 (3,05) 0.090 (2,29) D D1 0.020 (0,51) MIN 3 1 19 0.032 (0,81) 0.026 (0,66) 4 E 18 D2 / E2 E1 D2 / E2 8 14 0.021 (0,53) 0.013 (0,33) 0.007 (0,18) M 0.050 (1,27) 9 13 0.008 (0,20) NOM D/E D2 / E2 D1 / E1 NO. OF PINS ** MIN MAX MIN MAX MIN MAX 20 0.385 (9,78) 0.395 (10,03) 0.350 (8,89) 0.356 (9,04) 0.141 (3,58) 0.169 (4,29) 28 0.
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