Datasheet

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PVIN

AGND

PGOOD

SS/TRK

AVIN

COMP

LM20125

VCC

PGND

VCC

OUT

FB2

FB1

(optional)

LM20125

www.ti.com

SNVS525E –OCTOBER 2007–REVISED MARCH 2013

LM20125/LM20125Q 5A, 500kHz PowerWise

Synchronous Buck Regulator

Check for Samples: LM20125

FEATURES

DESCRIPTION

The LM20125 is a full featured 500 kHz synchronous

• LM20125Q is AEC-Q100 Qualified and

buck regulator capable of delivering up to 5A of

Manufactured on an Automotive Grade Flow

continuous output current. The current mode control

• Input Voltage Range 2.95V to 5.5V

loop can be compensated to be stable with virtually

• Accurate Current Limit Minimizes Inductor

any type of output capacitor. For most cases,

compensating the device only requires two external

Size

components, providing maximum flexibility and ease

• 97% Efficiency with 500 kHz Switching

of use. The device is optimized to work over the input

Frequency

voltage range of 2.95V to 5.5V making it suited for a

• 32 mΩ Integrated FET Switches

wide variety of low voltage systems.

• Starts up into Pre-Biased Loads

The device features internal over voltage protection

• Output Voltage Tracking

(OVP) and over current protection (OCP) circuits for

increased system reliability. A precision enable pin

• Peak Current Mode Control

and integrated UVLO allows the turn-on of the device

• Adjustable Output Voltage Down to 0.8V

to be tightly controlled and sequenced. Start-up

• Adjustable Soft-Start with External Capacitor

inrush currents are limited by both an internally fixed

and externally adjustable Soft-Start circuit. Fault

• Precision Enable Pin with Hysteresis

detection and supply sequencing is possible with the

• Integrated OVP, UVLO, Power Good and

integrated power good circuit.

Thermal Shutdown

The LM20125 is designed to work well in multi-rail

• HTSSOP 16-Pin Exposed Pad Package

power supply architectures. The output voltage of the

device can be configured to track a higher voltage rail

APPLICATIONS

using the SS/TRK pin. If the output of the LM20125 is

• Simple to Design, High Efficiency Point of

pre-biased at startup it will not sink current to pull the

Load Regulation from a 5V or 3.3V Bus

output low until the internal soft-start ramp exceeds

the voltage at the feedback pin.

• High Performance DSPs, FPGAs, ASICs and

Microprocessors

The LM20125 is offered in a 16-pin HTSSOP

package with an exposed pad that can be soldered to

• Broadband, Networking and Optical

the PCB, eliminating the need for bulky heatsinks.

Communications Infrastructure

TYPICAL APPLICATION CIRCUIT

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (28 pages)

PAGE 1
LM20125 www.ti.com SNVS525E – OCTOBER 2007 – REVISED MARCH 2013 LM20125/LM20125Q 5A, 500kHz PowerWise® Synchronous Buck Regulator Check for Samples: LM20125 FEATURES DESCRIPTION • The LM20125 is a full featured 500 kHz synchronous buck regulator capable of delivering up to 5A of continuous output current. The current mode control loop can be compensated to be stable with virtually any type of output capacitor.
PAGE 2
LM20125 SNVS525E – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
PAGE 3
LM20125 www.ti.com SNVS525E – OCTOBER 2007 – REVISED MARCH 2013 ABSOLUTE MAXIMUM RATINGS (1) Voltages from the indicated pins to GND AVIN, PVIN, EN, PGOOD, SS/TRK, COMP, FB, SW -0.3V to +6V Storage Temperature -65°C to 150°C Junction Temperature 150°C (2) 2.6W Lead Temperature (Soldering, 10 sec) 260°C Power Dissipation Minimum ESD Rating (3) (1) (2) (3) ±2kV Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
PAGE 4
LM20125 SNVS525E – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com ELECTRICAL CHARACTERISTICS Unless otherwise stated, the following conditions apply: AVIN = PVIN = VIN = 5V. Limits in standard type are for TJ = 25°C only, limits in bold face type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation.
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LM20125 www.ti.com SNVS525E – OCTOBER 2007 – REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise specified: CIN = COUT = 100 µF, L = 1.5 µH (Coilcraft MSS1038), VIN = 5V, VOUT = 1.2V, RLOAD = 1.2Ω, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. Efficiency vs. Load Current (VIN = 5V) Efficiency vs. Load Current (VIN = 3.3V) Figure 1. Figure 2. High-Side FET resistance vs. Temperature Low-Side FET resistance vs.Temperature Figure 3.
PAGE 6
LM20125 SNVS525E – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: CIN = COUT = 100 µF, L = 1.5 µH (Coilcraft MSS1038), VIN = 5V, VOUT = 1.2V, RLOAD = 1.2Ω, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. 6 Load Regulation Feedback Voltage vs. Temperature Figure 7. Figure 8. Switching Frequency vs. Temperature Quiescent Current vs. VIN (Not Switching) Figure 9. Figure 10.
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LM20125 www.ti.com SNVS525E – OCTOBER 2007 – REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: CIN = COUT = 100 µF, L = 1.5 µH (Coilcraft MSS1038), VIN = 5V, VOUT = 1.2V, RLOAD = 1.2Ω, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. UVLO Threshold vs. Temperature Peak Current Limit vs. Temperature Figure 13. Figure 14. Peak Current Limit vs. VOUT Peak Current Limit vs. VIN Figure 15. Figure 16.
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LM20125 SNVS525E – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: CIN = COUT = 100 µF, L = 1.5 µH (Coilcraft MSS1038), VIN = 5V, VOUT = 1.2V, RLOAD = 1.2Ω, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. Start-Up (Soft-Start) Start-Up (Tracking) Figure 19. Figure 20. Power Down Short Circuit Input Current vs. VIN Figure 21. Figure 22. PGOOD vs. IPGOOD Figure 23.
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LM20125 www.ti.com SNVS525E – OCTOBER 2007 – REVISED MARCH 2013 BLOCK DIAGRAM +2.7V REGULATOR AVIN 2.7V VCC UVLO + - SLOPE COMP PVIN COMP 2.7V CURRENT SENSE + 5 PA DISCHARGE (50 Ps) SS/TRK ERROR AMP gm = 510 Pmho + + FB 7.4A VREF + - 800 mV DISCHARGE CURRENT LIMIT + - PVIN + - 864 mV PWM COMPARATOR OVERVOLTAGE + - PG-L 752 mV UNDERVOLTAGE + - DIODE EMULATION CONTROL LOGIC + - SW PVIN THERMAL PROTECTION EN 1.
PAGE 10
LM20125 SNVS525E – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com PRECISION ENABLE The enable (EN) pin allows the output of the device to be enabled or disabled with an external control signal. This pin is a precision analog input that enables the device when the voltage exceeds 1.18V (typical). The EN pin has 66 mV of hysteresis and will disable the output when the enable voltage falls below 1.11V (typical). If the EN pin is not used, it should be connected to VIN.
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LM20125 www.ti.com SNVS525E – OCTOBER 2007 – REVISED MARCH 2013 POWER GOOD AND OVER VOLTAGE FAULT HANDLING The LM20125 has built in under and over voltage comparators that control the power switches. Whenever there is an excursion in output voltage above the set OVP threshold, the part will terminate the present on-pulse, turnon the low side FET, and pull the PGOOD pin low.
PAGE 12
LM20125 Switchnode Voltage SNVS525E – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com Continuous Conduction Mode (CCM) VIN Time (s) Inductor Current Continuous Conduction Mode (CCM) IAVERAGE Inductor Current Time (s) DCM - CCM Boundary IAVERAGE Switchnode Voltage Time (s) Discontinuous Conduction Mode (DCM) VIN Inductor Current Time (s) Discontinuous Conduction Mode (DCM) IPeak Time (s) Figure 24.
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LM20125 www.ti.com SNVS525E – OCTOBER 2007 – REVISED MARCH 2013 LM20125 PVIN SW VIN CIN L VOUT RFB1 EN RF AVIN FB CF VIN COUT RFB2 RPG COMP RC1 CC1 PGOOD VCC SS/TRK PGND GND VPG CSS CVCC Figure 25. Typical Application Circuit The first equation to calculate for any buck converter is duty-cycle.
PAGE 14
LM20125 SNVS525E – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com OUTPUT CAPACITOR SELECTION (COUT) The output capacitor, COUT, filters the inductor ripple current and provides a source of charge for transient load conditions. A wide range of output capacitors may be used with the LM20125 that provide excellent performance. The best performance is typically obtained using ceramic, SP, or OSCON type chemistries.
PAGE 15
LM20125 www.ti.com SNVS525E – OCTOBER 2007 – REVISED MARCH 2013 As indicated by the RMS ripple current equation, highest requirement for RMS current rating occurs at 50% duty cycle. For this case, the RMS ripple current rating of the input capacitor should be greater than half the output current. For best performance, low ESR ceramic capacitors should be placed in parallel with higher capacitance capacitors to provide the best input filtering for the device.
PAGE 16
LM20125 www.ti.com Output Filter Pole, fP(FIL) AM 0 dB Output Filter Zero, fZ(FIL) Complex Double Pole, fP(MOD) Modulator and Output Filter Transfer Function SNVS525E – OCTOBER 2007 – REVISED MARCH 2013 Pole, fP2(EA) 0 dB Error Amp Zero, fZ(EA) AEA + AM Error Amp Pole, fP(EA) 0 dB Complex Double Pole, fP(MOD) fC Error Amplifier Transfer Function Optional Error Amp Compensated Closed Loop Transfer Function GAIN (dB) Error Amp Pole, fP1(EA) AEA fSW/2 FREQUENCY (Hz) Figure 27.
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LM20125 www.ti.com SNVS525E – OCTOBER 2007 – REVISED MARCH 2013 If the output filter zero, fZ(FIL) approaches the crossover frequency, an additional capacitor (CC2) should be placed at the COMP pin to ground. This capacitor adds a pole to cancel the output filter zero assuring the crossover frequency will occur before the double pole at fSW/2 degrades the phase margin. The output filter zero is set by the output capacitor value and ESR as shown in the equation below.
PAGE 18
LM20125 SNVS525E – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com USING PRECISION ENABLE AND POWER GOOD The precision enable (EN) and power good (PGOOD) pins of the LM20125 can be used to address many sequencing requirements. The turn-on of the LM20125 can be controlled with the precision enable pin by using two external resistors as shown in Figure 29. External Power Supply VOUT1 LM20125 RA VOUT2 EN RB Figure 29.
PAGE 19
LM20125 www.ti.com SNVS525E – OCTOBER 2007 – REVISED MARCH 2013 SIMULTANEOUS START UP VOLTAGE VOUT1 VOUT2 §VOUT2 · -1¸¸ x R2 R1 = ¨¨ © 0.8V ¹ VEN VOUT2 < 0.8 x VOUT1 TIME RATIOMETRIC START UP VOUT1 VOLTAGE VOUT2 R1 = ( VOUT1 -1) x R2 VEN TIME Figure 31. Common Start Up Sequences A simultaneous start up is preferred when powering most FPGAs, DSPs, or other microprocessors. In these systems the higher voltage, VOUT1, usually powers the I/O, and the lower voltage, VOUT2, powers the core.
PAGE 20
LM20125 SNVS525E – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com THERMAL CONSIDERATIONS The thermal characteristics of the LM20125 are specified using the parameter θJA, which relates the junction temperature to the ambient temperature. Although the value of θJA is dependant on many variables, it still can be used to approximate the operating junction temperature of the device.
PAGE 21
LM20125 www.ti.com SNVS525E – OCTOBER 2007 – REVISED MARCH 2013 PCB LAYOUT CONSIDERATIONS PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability. Good layout can be implemented by following a few simple design rules. 1.
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LM20125 SNVS525E – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com Typical Application Circuits This section provides several application solutions with a bill of materials. All bill of materials reference the below figure. The compensation for these solutions were optimized to work over a wide range of input and output voltages; if a faster transient response is needed reduce the value of CC1 and calculate the new value for RC1 as outline in the design guide.
PAGE 23
LM20125 www.ti.com SNVS525E – OCTOBER 2007 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision D (March 2013) to Revision E • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 25
PACKAGE MATERIALS INFORMATION www.ti.com 7-Jun-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LM20125MHE/NOPB HTSSOP PWP 16 250 178.0 12.4 LM20125MHX/NOPB HTSSOP PWP 16 2500 330.0 12.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.95 8.3 1.6 8.0 12.0 Q1 6.95 8.3 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 7-Jun-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM20125MHE/NOPB HTSSOP PWP LM20125MHX/NOPB HTSSOP PWP 16 250 210.0 185.0 35.0 16 2500 367.0 367.0 35.
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MECHANICAL DATA PWP0016A MXA16A (Rev A) www.ti.
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