Datasheet

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PVIN

AGND

PGOOD

SS/TRK

AVIN

COMP

LM20133

VCC

PGND

VCC

OUT

FB2

FB1

(optional)

SYNC

LM20133, LM20133Q

www.ti.com

SNVS526F –OCTOBER 2007–REVISED MARCH 2013

3A, PowerWise

Synchronous Buck Regulator with Input Synchronization

Check for Samples: LM20133, LM20133Q

FEATURES

DESCRIPTION

The LM20133 is a full featured synchronous buck

• LM20133Q is AEC-Q100 Qualified and

regulator capable of delivering up to 3A of continuous

Manufactured on an Automotive Grade Flow

output current. The current mode control loop can be

• Input Voltage Range 2.95V to 5.5V

compensated to be stable with virtually any type of

• Accurate Current Limit Minimizes Inductor

output capacitor. For most cases, compensating the

device only requires two external components,

Size

providing maximum flexibility and ease of use. The

• 97% Peak Efficiency

device is optimized to work over the input voltage

• Frequency Synchronization Pin

range of 2.95V to 5.5V making it suited for a wide

• 32 mΩ Integrated FET Switches

variety of low voltage systems.

• Starts up into Pre-Biased Loads

The device features internal over voltage protection

(OVP) and over current protection (OCP) circuits for

• Output Voltage Tracking

increased system reliability. A precision enable pin

• Peak Current Mode Control

and integrated UVLO allows the turn on of the device

• Adjustable Soft-Start with External Capacitor

to be tightly controlled and sequenced. Start-up

• Precision Enable Pin with Hysteresis

inrush currents are limited by both an internally fixed

and externally adjustable Soft-Start circuit. Fault

• Integrated OVP, UVLO, Power Good and

detection and supply sequencing is possible with the

Thermal Shutdown

integrated power good circuit.

• HTSSOP 16-Pin Exposed Pad Package

The switching frequency of the LM20133 can be

synchronized to an external clock by use of the

APPLICATIONS

SYNC pin. The SYNC pin is capable of synchronizing

• Simple to Design, High Efficiency Point of

to input signals ranging from 500 kHz to 1.5 MHz.

Load Regulation from a 5V or 3.3V bus

The LM20133 is designed to work well in multi-rail

• High Performance DSPs, FPGAs, ASICs and

power supply architectures. The output voltage of the

Microprocessors

device can be configured to track a higher voltage rail

using the SS/TRK pin. If the output of the LM20133 is

• Broadband, Networking and Optical

pre-biased at startup it will not sink current to pull the

Communications Infrastructure

output low until the internal soft-start ramp exceeds

the voltage at the feedback pin.

Typical Application Circuit

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (29 pages)

PAGE 1
LM20133, LM20133Q www.ti.com SNVS526F – OCTOBER 2007 – REVISED MARCH 2013 3A, PowerWise® Synchronous Buck Regulator with Input Synchronization Check for Samples: LM20133, LM20133Q FEATURES DESCRIPTION • The LM20133 is a full featured synchronous buck regulator capable of delivering up to 3A of continuous output current. The current mode control loop can be compensated to be stable with virtually any type of output capacitor.
PAGE 2
LM20133, LM20133Q SNVS526F – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION CONTINUED The LM20133 is offered in a 16-pin HTSSOP package with an exposed pad that can be soldered to the PCB, eliminating the need for bulky heatsinks.
PAGE 3
LM20133, LM20133Q www.ti.com SNVS526F – OCTOBER 2007 – REVISED MARCH 2013 ABSOLUTE MAXIMUM RATINGS (1) Voltages from the indicated pins to GND AVIN, PVIN, EN, PGOOD, SS/TRK, COMP, FB, SW, SYNC -0.3V to +6V Storage Temperature -65°C to 150°C Junction Temperature 150°C (2) 2.6W Lead Temperature (Soldering, 10 sec) 260°C Power Dissipation Minimum ESD Rating (1) (2) ±2kV Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
PAGE 4
LM20133, LM20133Q SNVS526F – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com ELECTRICAL CHARACTERISTICS Unless otherwise stated, the following conditions apply: AVIN = PVIN = VIN = 5V. Limits in standard type are for TJ = 25°C only, limits in bold face type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified by test, design, or statistical correlation.
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LM20133, LM20133Q www.ti.com SNVS526F – OCTOBER 2007 – REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise specified: CIN = COUT = 100 µF, L = 1.0 µH (Coilcraft MSS1038), VIN = 5V, VOUT = 1.2V, RLOAD = 1.2Ω, fSW = 1 MHz, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. Efficiency vs. Load Current (VIN = 5V, fSW = 1.5 MHz) Efficiency vs. Load Current (VIN = 3.3V, fSW = 1.5 MHz) Figure 1. Figure 2. Efficiency vs.
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LM20133, LM20133Q SNVS526F – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: CIN = COUT = 100 µF, L = 1.0 µH (Coilcraft MSS1038), VIN = 5V, VOUT = 1.2V, RLOAD = 1.2Ω, fSW = 1 MHz, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. 6 High-Side FET resistance vs. Temperature Low-Side FET resistance vs. Temperature Figure 7. Figure 8. Error Amplifier Gain vs.
PAGE 7
LM20133, LM20133Q www.ti.com SNVS526F – OCTOBER 2007 – REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: CIN = COUT = 100 µF, L = 1.0 µH (Coilcraft MSS1038), VIN = 5V, VOUT = 1.2V, RLOAD = 1.2Ω, fSW = 1 MHz, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. Switching Frequency vs. Temperature Switch Synchronization Figure 13. Figure 14. Quiescent Current vs. VIN (Not Switching) Shutdown Current vs.
PAGE 8
LM20133, LM20133Q SNVS526F – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: CIN = COUT = 100 µF, L = 1.0 µH (Coilcraft MSS1038), VIN = 5V, VOUT = 1.2V, RLOAD = 1.2Ω, fSW = 1 MHz, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. 8 Peak Current Limit vs. Temperature Peak Current Limit vs. VOUT Figure 19. Figure 20. Peak Current Limit vs. VIN Load Transient Response Figure 21.
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LM20133, LM20133Q www.ti.com SNVS526F – OCTOBER 2007 – REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: CIN = COUT = 100 µF, L = 1.0 µH (Coilcraft MSS1038), VIN = 5V, VOUT = 1.2V, RLOAD = 1.2Ω, fSW = 1 MHz, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. Start-Up (Tracking) Power Down Figure 25. Figure 26. Short Circuit Input Current vs. VIN PGOOD vs. IPGOOD Figure 27. Figure 28.
PAGE 10
LM20133, LM20133Q SNVS526F – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com BLOCK DIAGRAM +2.7V REGULATOR AVIN 2.7V VCC UVLO + - SLOPE COMP PVIN COMP 2.7V CURRENT SENSE + 5 PA DISCHARGE (50 Ps) ERROR AMP gm = 510 Pmho SS/TRK + + FB 5.2A VREF + - 800 mV DISCHARGE CURRENT LIMIT + - PVIN + - 864 mV PWM COMPARATOR OVERVOLTAGE + - PG-L 752 mV UNDERVOLTAGE + - DIODE EMULATION CONTROL LOGIC + - SW PVIN THERMAL PROTECTION EN + - 1.
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LM20133, LM20133Q www.ti.com SNVS526F – OCTOBER 2007 – REVISED MARCH 2013 PRECISION ENABLE The enable (EN) pin allows the output of the device to be enabled or disabled with an external control signal. This pin is a precision analog input that enables the device when the voltage exceeds 1.18V (typical). The EN pin has 66 mV of hysteresis and will disable the output when the enable voltage falls below 1.11V (typical). If the EN pin is not used, it should be connected to VIN.
PAGE 12
LM20133, LM20133Q SNVS526F – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com PRE-BIAS START UP CAPABILITY The LM20133 is in a pre-biased state when the device starts up with an output voltage greater than zero. This often occurs in many multi-rail applications such as when powering an FPGA, ASIC, or DSP. In these applications the output can be pre-biased through parasitic conduction paths from one supply rail to another.
PAGE 13
LM20133, LM20133Q SNVS526F – OCTOBER 2007 – REVISED MARCH 2013 Switchnode Voltage www.ti.com Continuous Conduction Mode (CCM) VIN Time (s) Inductor Current Continuous Conduction Mode (CCM) IAVERAGE Inductor Current Time (s) DCM - CCM Boundary IAVERAGE Switchnode Voltage Time (s) Discontinuous Conduction Mode (DCM) VIN Inductor Current Time (s) Discontinuous Conduction Mode (DCM) IPeak Time (s) Figure 29.
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LM20133, LM20133Q SNVS526F – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com LM20133 PVIN SW VIN CIN L VOUT RFB1 EN RF AVIN FB CF VIN COUT RFB2 RPG SYNC COMP RC1 CC1 PGOOD VCC SS/TRK PGND GND VPG CSS CVCC Figure 30. Typical Application Circuit The first equation to calculate for any buck converter is duty-cycle.
PAGE 15
LM20133, LM20133Q www.ti.com SNVS526F – OCTOBER 2007 – REVISED MARCH 2013 OUTPUT CAPACITOR SELECTION (COUT) The output capacitor, COUT, filters the inductor ripple current and provides a source of charge for transient load conditions. A wide range of output capacitors may be used with the LM20123 that provide excellent performance. The best performance is typically obtained using ceramic, SP, or OSCON type chemistries.
PAGE 16
LM20133, LM20133Q SNVS526F – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com As indicated by the RMS ripple current equation, highest requirement for RMS current rating occurs at 50% duty cycle. For this case, the RMS ripple current rating of the input capacitor should be greater than half the output current. For best performance, low ESR ceramic capacitors should be placed in parallel with higher capacitance capacitors to provide the best input filtering for the device.
PAGE 17
LM20133, LM20133Q SNVS526F – OCTOBER 2007 – REVISED MARCH 2013 Output Filter Pole, fP(FIL) AM 0 dB Output Filter Zero, fZ(FIL) Complex Double Pole, fP(MOD) Modulator and Output Filter Transfer Function www.ti.com Pole, fP2(EA) 0 dB Error Amp Zero, fZ(EA) AEA + AM Error Amp Pole, fP(EA) 0 dB Complex Double Pole, fP(MOD) fC Error Amplifier Transfer Function Optional Error Amp Compensated Closed Loop Transfer Function GAIN (dB) Error Amp Pole, fP1(EA) AEA fSW/2 FREQUENCY (Hz) Figure 32.
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LM20133, LM20133Q SNVS526F – OCTOBER 2007 – REVISED MARCH 2013 fZ(FIL) = www.ti.com 1 2 x S x COUT x RESR (9) If needed, the value for CC2 should be calculated using the equation shown below.
PAGE 19
LM20133, LM20133Q www.ti.com SNVS526F – OCTOBER 2007 – REVISED MARCH 2013 External Power Supply VOUT1 LM20133 RA VOUT2 EN RB Figure 34. Sequencing LM20133 with Precision Enable The value for resistor RB can be selected by the user to control the current through the divider. Typically this resistor will be selected to be between 10 kΩ and 1 MΩ. Once the value for RB is chosen the resistor RA can be solved using the equation below to set the desired turn-on voltage.
PAGE 20
LM20133, LM20133Q SNVS526F – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com SIMULTANEOUS START UP VOLTAGE VOUT1 VOUT2 §VOUT2 · -1¸¸ x R2 R1 = ¨¨ © 0.8V ¹ VEN VOUT2 < 0.8 x VOUT1 TIME RATIOMETRIC START UP VOUT1 VOLTAGE VOUT2 R1 = ( VOUT1 -1) x R2 VEN TIME Figure 36. Common Start Up Sequences A simultaneous start up is preferred when powering most FPGAs, DSPs, or other microprocessors.
PAGE 21
LM20133, LM20133Q www.ti.com SNVS526F – OCTOBER 2007 – REVISED MARCH 2013 THERMAL CONSIDERATIONS The thermal characteristics of the LM20133 are specified using the parameter θJA, which relates the junction temperature to the ambient temperature. Although the value of θJA is dependant on many variables, it still can be used to approximate the operating junction temperature of the device.
PAGE 22
LM20133, LM20133Q SNVS526F – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com PCB LAYOUT CONSIDERATIONS PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability. Good layout can be implemented by following a few simple design rules.
PAGE 23
LM20133, LM20133Q www.ti.com SNVS526F – OCTOBER 2007 – REVISED MARCH 2013 Typical Application Circuits This section provides several application solutions with a bill of materials. All bill of materials reference the below figure. The compensation for these solutions were optimized to work over a wide range of input and output voltages; if a faster transient response is needed reduce the value of CC1 and calculate the new value for RC1 as outline in the design guide.
PAGE 24
LM20133, LM20133Q SNVS526F – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision E (March 2013) to Revision F • 24 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 7-Jun-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LM20133MHE/NOPB HTSSOP PWP 16 250 178.0 12.4 LM20133MHX/NOPB HTSSOP PWP 16 2500 330.0 12.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.95 8.3 1.6 8.0 12.0 Q1 6.95 8.3 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 7-Jun-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM20133MHE/NOPB HTSSOP PWP LM20133MHX/NOPB HTSSOP PWP 16 250 210.0 185.0 35.0 16 2500 367.0 367.0 35.
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MECHANICAL DATA PWP0016A MXA16A (Rev A) www.ti.
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