Datasheet

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PVIN

AGND

PGOOD

SS/TRK

AVIN

COMP

LM20143

VCC

PGND

VCC

OUT

FB2

FB1

(optional)

LM20143

www.ti.com

SNVS528G –OCTOBER 2007–REVISED MARCH 2013

LM20143/LM20143Q 3A, PowerWise

Adjustable Frequency Synchronous Buck Regulator

Check for Samples: LM20143

FEATURES

DESCRIPTION

The LM20143 is a full featured adjustable frequency

• Available in AEC-Q100 Temperature Grade 1

synchronous buck regulator capable of delivering up

• Input Voltage Range: 2.95V to 5.50V

to 3A of continuous output current. The current mode

• Accurate Current Limit Minimizes Inductor

control loop can be compensated to be stable with

Size

virtually any type of output capacitor. For most cases,

compensating the device only requires two external

• 97% Peak Efficiency

components, providing maximum flexibility and ease

• Adjustable Output Voltage Down to 0.80V

of use. The device is optimized to work over the input

• Adjustable Switching Frequency (500 kHz to

voltage range of 2.95V to 5.5V making it suited for a

1.5 MHz)

wide variety of low voltage systems.

• 32 mΩ Integrated FET Switches

The device features internal over voltage protection

(OVP) and over current protection (OCP) circuits for

• Starts into Prebiased Loads

increased system reliability. A precision enable pin

• Output Voltage Tracking

and integrated UVLO allows the turn-on of the device

• Peak Current Mode Control

to be tightly controlled and sequenced. Start-up

• Adjustable Soft-Start with External Capacitor

inrush currents are limited by both an internally fixed

and externally adjustable Soft-Start circuit. Fault

• Precision Enable Pin with Hysteresis

detection and supply sequencing is possible with the

• Integrated OVP, UVLO, Power Good and

integrated power good circuit.

Thermal Shutdown

The frequency of this device can be adjusted from

• HTSSOP 16-Pin Exposed Pad Package

500 kHz to 1.5 MHz by connecting an external

resistor from the RT pin to ground.

APPLICATIONS

The LM20143 is designed to work well in multi-rail

• Simple to Design, High Efficiency Point of

power supply architectures. The output voltage of the

Load Regulation from a 5V or 3.3V Bus

device can be configured to track a higher voltage rail

• High Performance DSPs, FPGAs, ASICs and

using the SS/TRK pin. If the output of the LM20143 is

pre-biased at startup it will not sink current to pull the

Microprocessors

output low until the internal soft-start ramp exceeds

• Broadband, Networking and Optical

the voltage at the feedback pin.

Communications Infrastructure

The LM20143 is offered in a 16-pin HTSSOP

package with an exposed pad that can be soldered to

the PCB, eliminating the need for bulky heatsinks.

Typical Application Circuit

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (30 pages)

PAGE 1
LM20143 www.ti.com SNVS528G – OCTOBER 2007 – REVISED MARCH 2013 LM20143/LM20143Q 3A, PowerWise® Adjustable Frequency Synchronous Buck Regulator Check for Samples: LM20143 FEATURES DESCRIPTION • • • The LM20143 is a full featured adjustable frequency synchronous buck regulator capable of delivering up to 3A of continuous output current. The current mode control loop can be compensated to be stable with virtually any type of output capacitor.
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LM20143 SNVS528G – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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LM20143 www.ti.com SNVS528G – OCTOBER 2007 – REVISED MARCH 2013 ABSOLUTE MAXIMUM RATINGS (1) Voltages from the indicated pins to GND AVIN, PVIN, EN, PGOOD, SS/TRK, COMP, FB, RT -0.3V to +6V Storage Temperature -65°C to 150°C Junction Temperature 150°C Power Dissipation (2) 2.6W Lead Temperature (Soldering, 10 sec) 260°C Minimum ESD Rating (1) (2) ±2kV Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
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LM20143 SNVS528G – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com ELECTRICAL CHARACTERISTICS Unless otherwise stated, the following conditions apply: AVIN = PVIN = VIN = 5V. Limits in standard type are for TJ = 25°C only, limits in bold face type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specifed by test, design, or statistical correlation.
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LM20143 www.ti.com SNVS528G – OCTOBER 2007 – REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise specified: CIN = COUT = 100 µF, L = 1.0 µH (Coilcraft MSS1038), VIN = 5V, VOUT = 1.2V, RLOAD = 1.2Ω, fSW = 1 MHz, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. Efficiency vs. Load Current (VIN = 5V, fSW = 1.5 MHz) Efficiency vs. Load Current (VIN = 3.3V, fSW = 1.5 MHz) Figure 1. Figure 2. Efficiency vs. Load Current (VIN = 5V, fSW = 1.
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LM20143 SNVS528G – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: CIN = COUT = 100 µF, L = 1.0 µH (Coilcraft MSS1038), VIN = 5V, VOUT = 1.2V, RLOAD = 1.2Ω, fSW = 1 MHz, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. 6 High-Side FET Resistance vs. Temperature Low-Side FET Resistance vs. Temperature Figure 7. Figure 8. Error Amplifier Gain vs. Frequency Line Regulation Figure 9.
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LM20143 www.ti.com SNVS528G – OCTOBER 2007 – REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: CIN = COUT = 100 µF, L = 1.0 µH (Coilcraft MSS1038), VIN = 5V, VOUT = 1.2V, RLOAD = 1.2Ω, fSW = 1 MHz, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. Switching Frequency vs. Temperature Switching Frequency vs. RT Figure 13. Figure 14. Quiescent Current vs. VIN (Not Switching) Shutdown Current vs.
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LM20143 SNVS528G – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: CIN = COUT = 100 µF, L = 1.0 µH (Coilcraft MSS1038), VIN = 5V, VOUT = 1.2V, RLOAD = 1.2Ω, fSW = 1 MHz, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. 8 Peak Current Limit vs. Temperature Peak Current Limit vs. VOUT Figure 19. Figure 20. Peak Current Limit vs. VIN Load Transient Response Figure 21. Figure 22.
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LM20143 www.ti.com SNVS528G – OCTOBER 2007 – REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: CIN = COUT = 100 µF, L = 1.0 µH (Coilcraft MSS1038), VIN = 5V, VOUT = 1.2V, RLOAD = 1.2Ω, fSW = 1 MHz, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. Start Up (Tracking) Short Circuit Input Current vs. VIN Figure 25. Figure 26. Power Down Figure 27.
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LM20143 SNVS528G – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com BLOCK DIAGRAM +2.7V REGULATOR AVIN 2.7V VCC UVLO + - SLOPE COMP PVIN COMP 2.7V CURRENT SENSE + 5 PA DISCHARGE (50 Ps) SS/TRK ERROR AMP gm = 510 Pmho + + FB 4.8A VREF + - 800 mV DISCHARGE CURRENT LIMIT + - PVIN + - 864 mV PWM COMPARATOR OVERVOLTAGE + - PG-L 752 mV UNDERVOLTAGE + - DIODE EMULATION CONTROL LOGIC + - SW PVIN THERMAL PROTECTION EN 1.
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LM20143 www.ti.com SNVS528G – OCTOBER 2007 – REVISED MARCH 2013 OPERATION DESCRIPTION GENERAL The LM20143 switching regulator features all of the functions necessary to implement an efficient low voltage buck regulator using a minimum number of external components. This easy to use regulator features two integrated switches and is capable of supplying up to 3A of continuous output current.
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LM20143 SNVS528G – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com PRE-BIAS START UP CAPABILITY The LM20143 is in a pre-biased state when the device starts up with an output voltage greater than zero. This often occurs in many multi-rail applications such as when powering an FPGA, ASIC, or DSP. In these applications the output can be pre-biased through parasitic conduction paths from one supply rail to another.
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LM20143 SNVS528G – OCTOBER 2007 – REVISED MARCH 2013 Switchnode Voltage www.ti.com Continuous Conduction Mode (CCM) VIN Time (s) Inductor Current Continuous Conduction Mode (CCM) IAVERAGE Inductor Current Time (s) DCM - CCM Boundary IAVERAGE Switchnode Voltage Time (s) Discontinuous Conduction Mode (DCM) VIN Inductor Current Time (s) Discontinuous Conduction Mode (DCM) IPeak Time (s) Figure 28.
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LM20143 SNVS528G – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com LM20143 PVIN SW VIN CIN L VOUT RFB1 EN RF AVIN FB CF COUT VIN RFB2 RPG RT RT COMP RC1 CC1 PGOOD VCC SS/TRK PGND GND VPG CVCC CSS Figure 29. Typical Application Circuit The first equation to calculate for any buck converter is duty-cycle.
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LM20143 www.ti.com SNVS528G – OCTOBER 2007 – REVISED MARCH 2013 OUTPUT CAPACITOR SELECTION (COUT) The output capacitor, COUT, filters the inductor ripple current and provides a source of charge for transient load conditions. A wide range of output capacitors may be used with the LM20143 that provide excellent performance. The best performance is typically obtained using ceramic, SP, or OSCON type chemistries.
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LM20143 SNVS528G – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com As indicated by the RMS ripple current equation, highest requirement for RMS current rating occurs at 50% duty cycle. For this case, the RMS ripple current rating of the input capacitor should be greater than half the output current. For best performance, low ESR ceramic capacitors should be placed in parallel with higher capacitance capacitors to provide the best input filtering for the device.
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LM20143 www.ti.com SNVS528G – OCTOBER 2007 – REVISED MARCH 2013 Table 2. Recommended Compensation for COUT = 100 µF, L = 1 µH & fSW = 1 MHz VIN VOUT CC1 (nF) RC1 (kΩ) 5.00 3.30 4.7 17.8 5.00 2.50 4.7 12.1 5.00 1.80 4.7 7.68 5.00 1.50 4.7 5.9 5.00 1.20 4.7 3.57 5.00 0.80 4.7 1.58 3.30 2.50 4.7 13 3.30 1.80 4.7 9.76 3.30 1.50 4.7 6.49 3.30 1.20 4.7 4.64 3.30 0.80 4.7 1.
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LM20143 SNVS528G – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com LM20143 COMP RC1 CC2 (optional) CC1 Figure 32. Compensation Network for LM20143 A good starting value for CC1 for most applications is 4.7 nF. Once the value of CC1 is chosen the value of RC should be calculated using the equation below to cancel the output filter pole (fP(FIL)) as shown in Figure 31.
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LM20143 www.ti.com SNVS528G – OCTOBER 2007 – REVISED MARCH 2013 Table 3. Start Up Times for Different Soft-Start Capacitors Start Up Time (ms) CSS (nF) 1 none 5 33 10 68 15 100 20 120 If different start up times are needed the equation shown below can be used to calculate the start up time. tSS = 0.8V x CSS ISS (12) As shown above, the start up time is influenced by the value of the Soft-Start capacitor CSS(F) and the 5 µA SoftStart pin current ISS(A).
PAGE 20
LM20143 SNVS528G – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com External Power Supply VOUT1 LM20143 R1 EN VOUT2 SS/TRK R2 Figure 34. Tracking an External Supply Since the Soft-Start charging current ISS is always present on the SS/TRK pin, the size of R2 should be less than 10 kΩ to minimize the errors in the tracking output. Once a value for R2 is selected the value for R1 can be calculated using appropriate equation in Figure 35, to give the desired start up.
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LM20143 www.ti.com SNVS528G – OCTOBER 2007 – REVISED MARCH 2013 THERMAL CONSIDERATIONS The thermal characteristics of the LM20143 are specified using the parameter θJA, which relates the junction temperature to the ambient temperature. Although the value of θJA is dependant on many variables, it still can be used to approximate the operating junction temperature of the device.
PAGE 22
LM20143 SNVS528G – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com PCB LAYOUT CONSIDERATIONS PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability. Good layout can be implemented by following a few simple design rules. 1.
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LM20143 www.ti.com SNVS528G – OCTOBER 2007 – REVISED MARCH 2013 Typical Application Circuits This section provides several application solutions with a bill of materials. All bill of materials reference the below figure. The compensation for these solutions were optimized to work over a wide range of input and output voltages; if a faster transient response is needed reduce the value of CC1 and calculate the new value for RC1 as outline in the design guide.
PAGE 24
LM20143 SNVS528G – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision F (March 2013) to Revision G • 24 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LM20143MHE/NOPB HTSSOP PWP 16 250 178.0 12.4 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.95 8.3 1.6 8.0 12.0 Q1 LM20143MHX/NOPB HTSSOP PWP 16 2500 330.0 12.4 6.95 8.3 1.6 8.0 12.0 Q1 LM20143QMHE/NOPB HTSSOP PWP 16 250 178.0 12.4 6.95 8.3 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM20143MHE/NOPB HTSSOP PWP LM20143MHX/NOPB HTSSOP PWP 16 250 210.0 185.0 35.0 16 2500 367.0 367.0 35.0 LM20143QMHE/NOPB HTSSOP PWP LM20143QMHX/NOPB HTSSOP PWP 16 250 210.0 185.0 35.0 16 2500 367.0 367.0 35.
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MECHANICAL DATA PWP0016A MXA16A (Rev A) www.ti.
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