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VIN

AGND

PGOOD

OUT

FB1

FB2

OUT

SS/TRK

VCC

COMP

LM20333

BOOT

GND

BOOT

(Optional)

SYNC

LM20333

www.ti.com

SNVS558D –MAY 2008–REVISED APRIL 2013

LM20333 36V, 3A Synchronous Buck Regulator with Frequency Synchronization

Check for Samples: LM20333

FEATURES

DESCRIPTION

The LM20333 is a full featured synchronous buck

• 4.5V to 36V Input Voltage Range

regulator capable of delivering up to 3A of load

• 3A Output Current, 5.2A Peak Current

current. The current mode control loop is externally

• 130 mΩ/110 mΩ Integrated Power MOSFETs

compensated with only two components, offering both

high performance and ease of use. The device is

• 94% Peak Efficiency with Synchronous

optimized to work over the input voltage range of

Rectification

4.5V to 36V making it well suited for high voltage

• 1.5% Feedback Voltage Accuracy

systems.

• Current Mode Control, Selectable

The device features internal Over Voltage Protection

Compensation

(OVP) and Over Current Protection (OCP) circuits for

• Oscillator Synchronization from 250kHz to

increased system reliability. A precision Enable pin

1.5MHz

and integrated UVLO allows the turn on of the device

to be tightly controlled and sequenced. Startup inrush

• Adjustable Output Voltage Down to 0.8V

currents are limited by both an internally fixed and

• Compatible with Pre-biased Loads

externally adjustable soft-start circuit. Fault detection

• Programmable Soft-start with External

and supply sequencing are possible with the

Capacitor

integrated power good (PGOOD) circuit.

• Precision Enable Pin with Hysteresis

The LM20333 is designed to work well in multi-rail

• OVP, UVLO Inputs and PGOOD Output

power supply architectures. The output voltage of the

device can be configured to track a higher voltage rail

• Internally Protected with Peak Current Limit,

using the SS/TRK pin. If the output of the LM20333 is

Thermal Shutdown and Restart

pre-biased at startup it will not sink current to pull the

• Accurate Current Limit Minimizes Inductor

output low until the internal soft-start ramp exceeds

Size

the voltage at the feedback pin.

• Non-linear Current Mode Slope Compensation

The switching frequency of the LM20333 can be

• 20-Pin HTSSOP Exposed Pad Package

synchronized to an external clock by use of the

SYNC pin. The SYNC pin is capable of synchronizing

APPLICATIONS

to input signals ranging from 250 kHz to 1.5 MHz.

• Simple to Design, High Efficiency Point of

The LM20333 is offered in an exposed pad 20-pin

Load Regulation from a 4.5V to 36V Bus HTSSOP package that can be soldered to the PCB,

eliminating the need for bulky heatsinks.

• High Performance DSPs, FPGAs, ASICs and

Microprocessors

• Communications Infrastructure, Automotive

Simplified Application Circuit

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (29 pages)

PAGE 1
LM20333 www.ti.com SNVS558D – MAY 2008 – REVISED APRIL 2013 LM20333 36V, 3A Synchronous Buck Regulator with Frequency Synchronization Check for Samples: LM20333 FEATURES DESCRIPTION • • • • The LM20333 is a full featured synchronous buck regulator capable of delivering up to 3A of load current. The current mode control loop is externally compensated with only two components, offering both high performance and ease of use. The device is optimized to work over the input voltage range of 4.
PAGE 2
LM20333 SNVS558D – MAY 2008 – REVISED APRIL 2013 www.ti.com Connection Diagram SS/TRK 1 20 SYNC FB 2 19 EN PGOOD 3 18 COMP 4 17 BOOT VCC VIN 5 VIN 6 SW 7 14 SW SW 8 13 SW GND 9 12 AGND GND 10 11 GND EP 16 VIN 15 VIN Figure 1. 20-Pin HTSSOP, Top View See PWP0020A Package PIN DESCRIPTIONS Pin(s) Name Description 1 SS/TRK Application Information Soft-Start or Tracking control input An internal 4.
PAGE 3
LM20333 www.ti.com SNVS558D – MAY 2008 – REVISED APRIL 2013 Absolute Maximum Ratings (1) (2) VIN to GND -0.3V to +38V BOOT to GND -0.3V to +43V BOOT to SW -0.3V to +7V SW to GND -0.5V to +38V SW to GND (Transient) -1.5V (< 20 ns) FB, EN, SS/TRK, COMP, SYNC, PGOOD to GND -0.3V to +6V VCC to GND -0.3V to +8V Storage Temperature -65°C to 150°C ESD Rating Human Body Model (3) (1) (2) (3) 2kV Absolute Maximum Ratings indicate limits beyond witch damage to the device may occur.
PAGE 4
LM20333 SNVS558D – MAY 2008 – REVISED APRIL 2013 www.ti.com Electrical Characteristics (continued) Unless otherwise stated, the following conditions apply: VVIN = 12V. Limits in standard type are for TJ = 25°C only, limits in bold face type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and maximum limits are specified through test, design, or statistical correlation.
PAGE 5
LM20333 www.ti.com SNVS558D – MAY 2008 – REVISED APRIL 2013 Typical Performance Characteristics Unless otherwise specified: VVIN = 12V, VOUT = 3.3V, L= 4.7µH, fSW=750kHz, CSS = 100nF, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. Efficiency vs. Load Current fSW = 350 kHz Efficiency vs. Load Current fSW = 500 kHz Figure 2. Figure 3. Efficiency vs. Load Current fSW = 750 kHz Error Amplifier Gain Figure 4. Figure 5.
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LM20333 SNVS558D – MAY 2008 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified: VVIN = 12V, VOUT = 3.3V, L= 4.7µH, fSW=750kHz, CSS = 100nF, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. 6 Load Regulation VCC vs. VIN Figure 8. Figure 9. Non-Switching IQ vs. VIN Shutdown IQ vs. VIN Figure 10. Figure 11. PGOOD Output Low Level Voltage vs. IPGOOD Enable Threshold and Hysteresis vs.
PAGE 7
LM20333 www.ti.com SNVS558D – MAY 2008 – REVISED APRIL 2013 Typical Performance Characteristics (continued) Unless otherwise specified: VVIN = 12V, VOUT = 3.3V, L= 4.7µH, fSW=750kHz, CSS = 100nF, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. UVLO Threshold and Hysteresis vs. Temperature Enable Current vs. Temperature Figure 14. Figure 15. Clock Synchronization High-Side FET Resistance vs. Temperature Figure 16. Figure 17. Low-Side FET Resistance vs.
PAGE 8
LM20333 SNVS558D – MAY 2008 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified: VVIN = 12V, VOUT = 3.3V, L= 4.7µH, fSW=750kHz, CSS = 100nF, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. Peak Current Limit vs. Temperature Startup with prebiased output Figure 20. Figure 21. Startup with CSS = 0 Startup with CSS = 100 nF Figure 22. Figure 23. Startup with applied Track Signal Figure 24.
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LM20333 www.ti.com SNVS558D – MAY 2008 – REVISED APRIL 2013 Block Diagram VCC_INT BOOT INTERNAL +5.5V REGULATOR BOOT VCC ENABLE_INT VIN VCC 2.7V UVLO + - 4.25V +5.5V REGULATOR +2.7V REGULATOR SLOPE COMP COMP 2.7V CURRENT SENSE + 4.5 PA DISCHARGE ERROR AMP gm = 515 Pmho SS/TRK + FB DISCHARGE CURRENT LIMIT 5.2A VREF + 800 mV - BOOT + - + + PWM COMPARATOR 880 mV 740 mV + - PG-L + - VCC_INT NEGATIVE CURRENT LIMIT OVERVOLTAGE UNDERVOLTAGE + - CONTROL LOGIC -2.
PAGE 10
LM20333 SNVS558D – MAY 2008 – REVISED APRIL 2013 www.ti.com OPERATION DESCRIPTION GENERAL The LM20333 switching regulator features all of the functions necessary to implement an efficient buck regulator using a minimum number of external components. This easy to use regulator features two integrated switches and is capable of supplying up to 3A of continuous output current.
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LM20333 www.ti.com SNVS558D – MAY 2008 – REVISED APRIL 2013 CURRENT LIMIT The precise current limit enables the device to operate with smaller inductors that have lower saturation currents. When the peak inductor current reaches the current limit threshold, an over current event is triggered and the internal high-side FET turns off and the low-side FET turns on, allowing the inductor current to ramp down until the next switching cycle.
PAGE 12
LM20333 SNVS558D – MAY 2008 – REVISED APRIL 2013 www.ti.com Design Guide This section walks the designer through the steps necessary to select the external components to build a fully functional power supply. As with any DC-DC converter numerous trade-offs are possible to optimize the design for efficiency, size, or performance. These will be taken into account and highlighted throughout this discussion.
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LM20333 www.ti.com SNVS558D – MAY 2008 – REVISED APRIL 2013 VSW VIN Time IL IL AVG = IOUT 'iL Time Figure 26. Switch and Inductor Current Waveforms If needed, slightly smaller value inductors can be used, however, the peak inductor current, IOUT + ΔiL/2, should be kept below the peak current limit of the device. In general, the inductor ripple current, ΔiL, should be more than 10% of the rated output current to provide adequate current sense information for the current mode control loop.
PAGE 14
LM20333 SNVS558D – MAY 2008 – REVISED APRIL 2013 VDROOP = 'IOUTSTEP x RESR + www.ti.
PAGE 15
LM20333 www.ti.com SNVS558D – MAY 2008 – REVISED APRIL 2013 LOOP COMPENSATION (RC1, CC1) The purpose of loop compensation is to meet static and dynamic performance requirements while maintaining adequate stability. Optimal loop compensation depends on the output capacitor, inductor, load and the device itself. Table 2 below gives values for the compensation network that will result in a stable system when using a 150 µF, 6.3V POSCAP output capacitor (6TPB150MAZB). Table 2.
PAGE 16
LM20333 SNVS558D – MAY 2008 – REVISED APRIL 2013 www.ti.com To achieve a -20dB/decade slope, the error amplifier zero, located at fZ(EA), should be positioned to cancel the output filter pole (fP(FIL)). Compensation of the LM20333 is achieved by adding an RC network as shown in Figure 28 below. LM20333 COMP RC1 CC2 (optional) CC1 Figure 28. Compensation Network for LM20333 A good starting value for CC1 for most applications is 2.2 nF.
PAGE 17
LM20333 www.ti.com SNVS558D – MAY 2008 – REVISED APRIL 2013 If different start up times are needed the equation shown below can be used to calculate the start up time. tSS = 0.8V x CSS ISS 22222 (8) As shown above, the start up time is influenced by the value of the soft-start capacitor CSS and the 4.5 µA softstart pin current ISS. While the soft-start capacitor can be sized to meet many start up requirements, there are limitations to its size.
PAGE 18
LM20333 SNVS558D – MAY 2008 – REVISED APRIL 2013 www.ti.com Since the soft-start charging current ISS is always present on the SS/TRK pin, the size of R2 should be less than 10 kΩ to minimize the errors in the tracking output. Once a value for R2 is selected the value for R1 can be calculated using appropriate equation in Figure 31, to give the desired start up.
PAGE 19
LM20333 www.ti.com SNVS558D – MAY 2008 – REVISED APRIL 2013 The external Schottky conducts currents for a very small portion of the switching cycle, therefore the average current is low. An external Schottky rated for 1A will improve efficiency by several percent in some applications. A Schottky rated at a higher current will not significantly improve efficiency and may be worse due to the increased reverse capacitance.
PAGE 20
LM20333 SNVS558D – MAY 2008 – REVISED APRIL 2013 www.ti.com Figure 33. Safe Thermal Operating Areas (IOUT = 3A, fSW = 500kHz) Figure 34. Safe Thermal Operating Areas (IOUT = 3A, fSW = 750kHz) Figure 35. Safe Thermal Operating Areas (IOUT = 2.5A, fSW = 500kHz) The dashed lines in the figures above show an approximation of the minimum and maximum duty cycle limitations; while, the solid lines define areas of operation for a given ambient temperature.
PAGE 21
LM20333 www.ti.com SNVS558D – MAY 2008 – REVISED APRIL 2013 Figure 36, shown below, provides a better approximation of the θJA for a given PCB copper area. The PCB used in this test consisted of 4 layers: 1oz. copper was used for the internal layers while the external layers were plated to 2oz. copper weight. To provide an optimal thermal connection, a 5 x 4 array of 12 mil thermal vias located under the thermal pad was used to connect the 4 layers. Figure 36.
PAGE 22
LM20333 SNVS558D – MAY 2008 – REVISED APRIL 2013 www.ti.com LM20333 L SW PVIN VOUT CIN COUT PGND LOOP1 LOOP2 Figure 37. Schematic of LM20333 Highlighting Layout Sensitive Nodes VIN C1 C3 C2 GND C2, C3 should be placed at VIN pins 5,6 and 15,16 respectively.
PAGE 23
LM20333 www.ti.com SNVS558D – MAY 2008 – REVISED APRIL 2013 Table 4. Bill of Materials (VIN = 12V, VOUT = 3.3V, IOUT = 3A, fSW = 500kHz) ID Qty Part Number Size Description Vendor U1 1 LM20333MH HTSSOP IC, Switching Regulator TI C1 1 C3225X5R1E226M 1210 22µF, X5R, 25V, 20% TDK C2, C3 2 GRM21BR61E475KA12L 0805 4.
PAGE 24
LM20333 SNVS558D – MAY 2008 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision C (April 2013) to Revision D • 24 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 26
PACKAGE MATERIALS INFORMATION www.ti.com 29-May-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LM20333MHE/NOPB HTSSOP PWP 20 250 178.0 16.4 LM20333MHX/NOPB HTSSOP PWP 20 2500 330.0 16.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.95 7.1 1.6 8.0 16.0 Q1 6.95 7.1 1.6 8.0 16.
PAGE 27
PACKAGE MATERIALS INFORMATION www.ti.com 29-May-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM20333MHE/NOPB HTSSOP PWP LM20333MHX/NOPB HTSSOP PWP 20 250 210.0 185.0 35.0 20 2500 367.0 367.0 35.
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MECHANICAL DATA PWP0020A MXA20A (Rev C) www.ti.
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