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AGND

PGOOD

OUT

FB1

FB2

OUT

SS/TRK

VCC

COMP

LM20343

BOOT

GND

BOOT

(Optional)

LM20343

www.ti.com

SNVS559B –MAY 2008–REVISED APRIL 2013

LM20343 36V, 3A Adjustable Frequency Synchronous Buck Regulator

Check for Samples: LM20343

FEATURES

DESCRIPTION

The LM20343 is a full featured synchronous buck

• 4.5V to 36V Input Voltage Range

regulator capable of delivering up to 3A of load

• 3A Output Current, 5.2A Peak Current

current. The current mode control loop is externally

• 130 mΩ/110 mΩ Integrated Power MOSFETs

compensated with only two components, offering both

high performance and ease of use. The device is

• 94% Peak Efficiency with Synchronous

optimized to work over the input voltage range of

Rectification

4.5V to 36V making it well suited for high voltage

• 1.5% Feedback Voltage Accuracy

systems.

• Current Mode Control, Selectable

The device features internal Over Voltage Protection

Compensation

(OVP) and Over Current Protection (OCP) circuits for

• Resistor Programmed, 1MHz Capable

increased system reliability. A precision Enable pin

Oscillator

and integrated UVLO allows the turn on of the device

to be tightly controlled and sequenced. Startup inrush

• Adjustable Output Voltage Down to 0.8V

currents are limited by both an internally fixed and

• Compatible with Pre-biased Loads

externally adjustable soft-start circuit. Fault detection

• Programmable Soft-start with External

and supply sequencing are possible with the

Capacitor

integrated power good (PGOOD) circuit.

• Precision Enable Pin with Hysteresis

The frequency of this device can be adjusted from

• OVP, UVLO Inputs and PGOOD Output

250 kHz to 1.0 MHz by connecting an external

resistor from the RT pin to ground.

• Internally Protected with Peak Current Limit,

Thermal Shutdown and Restart

The LM20343 is designed to work well in multi-rail

power supply architectures. The output voltage of the

• Accurate Current Limit Minimizes Inductor

device can be configured to track a higher voltage rail

Size

using the SS/TRK pin. If the output of the LM20343 is

• Non-linear Current Mode Slope Compensation

pre-biased at startup it will not sink current to pull the

• 20-Pin HTSSOP Exposed Pad Package

output low until the internal soft-start ramp exceeds

the voltage at the feedback pin.

APPLICATIONS

The LM20343 is offered in an exposed pad 20-pin

• Simple to Design, High Efficiency Point of

HTSSOP package that can be soldered to the PCB,

Load Tegulation from a 4.5V to 36V Bus eliminating the need for bulky heatsinks.

• High Performance DSPs, FPGAs, ASICs and

Microprocessors

• Communications Infrastructure, Automotive

Simplified Application Circuit

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (29 pages)

PAGE 1
LM20343 www.ti.com SNVS559B – MAY 2008 – REVISED APRIL 2013 LM20343 36V, 3A Adjustable Frequency Synchronous Buck Regulator Check for Samples: LM20343 FEATURES DESCRIPTION • • • • The LM20343 is a full featured synchronous buck regulator capable of delivering up to 3A of load current. The current mode control loop is externally compensated with only two components, offering both high performance and ease of use. The device is optimized to work over the input voltage range of 4.
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LM20343 SNVS559B – MAY 2008 – REVISED APRIL 2013 www.ti.com Connection Diagram SS/TRK 1 20 FB 2 19 EN RT PGOOD 3 18 COMP 4 17 BOOT VCC VIN 5 VIN 6 SW 7 14 SW SW 8 13 SW GND 9 12 AGND GND 10 11 GND EP 16 VIN 15 VIN Figure 1. 20-Pin HTSSOP, Top View See PWP0020A Package PIN DESCRIPTIONS 2 Pin(s) Name Description 1 SS/TRK Application Information Soft-Start or Tracking control input An internal 4.
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LM20343 www.ti.com SNVS559B – MAY 2008 – REVISED APRIL 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) VIN to GND -0.3V to +38V BOOT to GND -0.3V to +43V BOOT to SW -0.3V to +7V SW to GND -0.5V to +38V SW to GND (Transient) -1.5V (< 20 ns) FB, EN, SS/TRK, RT, PGOOD to GND -0.3V to +6V VCC to GND -0.
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LM20343 SNVS559B – MAY 2008 – REVISED APRIL 2013 www.ti.com Electrical Characteristics (continued) Unless otherwise stated, the following conditions apply: VVIN = 12V. Limits in standard type are for TJ = 25°C only, limits in bold face type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation.
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LM20343 www.ti.com SNVS559B – MAY 2008 – REVISED APRIL 2013 Typical Performance Characteristics Unless otherwise specified: VVIN = 12V, VOUT = 3.3V, L= 4.7µH, fSW=750kHz, CSS= 100nF, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. Efficiency vs. Load Current fSW = 350 kHz Efficiency vs. Load Current fSW = 500 kHz Figure 2. Figure 3. Efficiency vs. Load Current fSW = 750 kHz Error Amplifier Gain Figure 4. Figure 5.
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LM20343 SNVS559B – MAY 2008 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified: VVIN = 12V, VOUT = 3.3V, L= 4.7µH, fSW=750kHz, CSS= 100nF, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. 6 Load Regulation VCC vs. VIN Figure 8. Figure 9. Non-Switching IQ vs. VIN Shutdown IQ vs. VIN Figure 10. Figure 11. PGOOD Output Low Level Voltage vs. IPGOOD EN Threshold and Hysteresis vs.
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LM20343 www.ti.com SNVS559B – MAY 2008 – REVISED APRIL 2013 Typical Performance Characteristics (continued) Unless otherwise specified: VVIN = 12V, VOUT = 3.3V, L= 4.7µH, fSW=750kHz, CSS= 100nF, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. UVLO Threshold and Hysteresis vs. Temperature EN Current vs. Temperature Figure 14. Figure 15. Oscillator Frequency vs. RRT High-Side FET Resistance vs. Temperature Figure 16. Figure 17.
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LM20343 SNVS559B – MAY 2008 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified: VVIN = 12V, VOUT = 3.3V, L= 4.7µH, fSW=750kHz, CSS= 100nF, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. Peak Current Limit vs. Temperature Startup with output voltage prebias Figure 20. Figure 21. Startup with CSS = 0 Startup with CSS = 100 nF Figure 22. Figure 23. Startup with applied Track Signal Figure 24.
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LM20343 www.ti.com SNVS559B – MAY 2008 – REVISED APRIL 2013 Block Diagram BOOT BOOT VCC +5.5V REGULATOR VIN VCC 4.25V 2.7V UVLO + - +2.7V REGULATOR SLOPE COMP COMP 2.7V CURRENT SENSE + 4.5 PA DISCHARGE ERROR AMP gm = 515 Pmho SS/TRK + FB DISCHARGE CURRENT LIMIT 5.2A VREF + 800 mV - BOOT + - + + PWM COMPARATOR 880 mV 740 mV + - PG-L + - VCC NEGATIVE CURRENT LIMIT OVERVOLTAGE UNDERVOLTAGE + - CONTROL LOGIC -2.8A SW VCC THERMAL PROTECTION 2 PA EN 1.
PAGE 10
LM20343 SNVS559B – MAY 2008 – REVISED APRIL 2013 www.ti.com OPERATION DESCRIPTION GENERAL The LM20343 switching regulator features all of the functions necessary to implement an efficient buck regulator using a minimum number of external components. This easy to use regulator features two integrated switches and is capable of supplying up to 3A of continuous output current.
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LM20343 www.ti.com SNVS559B – MAY 2008 – REVISED APRIL 2013 PRE-BIAS STARTUP CAPABILITY The LM20343 is in a pre-biased state when it starts up with an output voltage greater than zero. This often occurs in many multi-rail applications such as when powering an FPGA, ASIC, or DSP. In these applications the output can be pre-biased through parasitic conduction paths from one supply rail to another.
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LM20343 SNVS559B – MAY 2008 – REVISED APRIL 2013 www.ti.com The first equation to calculate for any buck converter is duty-cycle. Ignoring conduction losses associated with the FETs and parasitic resistances it can be approximated by: D= VOUT VIN (1) INDUCTOR SELECTION (L) The inductor value is determined based on the operating frequency, load current, ripple current and duty cycle. The inductor selected should have a saturation current rating greater than the peak current limit of the device.
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LM20343 www.ti.
PAGE 14
LM20343 SNVS559B – MAY 2008 – REVISED APRIL 2013 www.ti.com Table 1. Suggested Values for RFB1 and RFB2 RFB1(kΩ) RFB2(kΩ) VOUT short open 0.8 4.99 10 1.2 8.87 10.2 1.5 12.7 10.2 1.8 21.5 10.2 2.5 31.6 10.2 3.3 52.3 10 5.0 If different output voltages are required, RFB2 should be selected to be between 4.99 kΩ to 49.9 kΩ and RFB1 can be calculated using the equation below. RFB1 = VOUT 0.
PAGE 15
LM20343 www.ti.com SNVS559B – MAY 2008 – REVISED APRIL 2013 Output Filter Pole, fP(FIL) AM 0 dB Output Filter Zero, fZ(FIL) Complex Double Pole, fP(MOD) Modulator and Output Filter Transfer Function If the desired solution differs from the table above the loop transfer function should be analyzed to optimize the loop compensation. The overall loop transfer function is the product of the power stage and the feedback network transfer functions.
PAGE 16
LM20343 SNVS559B – MAY 2008 – REVISED APRIL 2013 www.ti.com For low duty cycle operation, when the on time of the switch node is less than 200ns, an additional capacitor (CC2) should be added from the COMP pin to AGND. The recommended value of this capacitor is 20pF.
PAGE 17
LM20343 www.ti.com SNVS559B – MAY 2008 – REVISED APRIL 2013 External Power Supply VOUT1 LM20343 RA VOUT2 EN RB Figure 29. Sequencing LM20343 with Precision Enable The value for resistor RB can be selected by the user to control the current through the divider. Typically this resistor will be selected to be between 10 kΩ and 49.9 kΩ. Once the value for RB is chosen the resistor RA can be solved using the equation below to set the desired turn-on voltage.
PAGE 18
LM20343 SNVS559B – MAY 2008 – REVISED APRIL 2013 www.ti.com SIMULTANEOUS START UP VOLTAGE VOUT1 VOUT2 §VOUT2 · -1¸¸ x R2 R1 = ¨¨ © 0.8V ¹ VEN VOUT2 < 0.8 x VOUT1 TIME RATIOMETRIC START UP VOUT1 VOLTAGE VOUT2 R1 = ( VOUT1 -1) x R2 VEN TIME Figure 31. Common Start Up Sequences A simultaneous start up is preferred when powering most FPGAs, DSPs, or other microprocessors. In these systems the higher voltage, VOUT1, usually powers the I/O, and the lower voltage, VOUT2, powers the core.
PAGE 19
LM20343 www.ti.com SNVS559B – MAY 2008 – REVISED APRIL 2013 The external Schottky conducts currents for a very small portion of the switching cycle, therefore the average current is low. An external Schottky rated for 1A will improve efficiency by several percent in some applications. A Schottky rated at a higher current will not significantly improve efficiency and may be worse due to the increased reverse capacitance.
PAGE 20
LM20343 SNVS559B – MAY 2008 – REVISED APRIL 2013 www.ti.com Figure 33. Safe Thermal Operating Areas (IOUT = 3A, fSW = 500 kHz) Figure 34. Safe Thermal Operating Areas (IOUT = 3A, fSW = 750 kHz) Figure 35. Safe Thermal Operating Areas (IOUT = 2.5A, fSW = 500 kHz) The dashed lines in the figures above show an approximation of the minimum and maximum duty cycle limitations; while, the solid lines define areas of operation for a given ambient temperature.
PAGE 21
LM20343 www.ti.com SNVS559B – MAY 2008 – REVISED APRIL 2013 Figure 36, shown below, provides a better approximation of the θJA for a given PCB copper area. The PCB used in this test consisted of 4 layers: 1oz. copper was used for the internal layers while the external layers were plated to 2oz. copper weight. To provide an optimal thermal connection, a 5 x 4 array of 12 mil thermal vias located under the thermal pad was used to connect the 4 layers. Figure 36.
PAGE 22
LM20343 SNVS559B – MAY 2008 – REVISED APRIL 2013 www.ti.com LM20343 L SW PVIN VOUT CIN COUT PGND LOOP1 LOOP2 Figure 37. Schematic of LM20343 Highlighting Layout Sensitive Nodes VIN C1 C3 C2 GND C2, C3 should be placed at VIN pins 5,6 and 15,16 respectively.
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LM20343 www.ti.com SNVS559B – MAY 2008 – REVISED APRIL 2013 Table 4. Bill of Materials (VIN = 12V, VOUT = 3.3V, IOUT = 3A, fSW = 750 kHz) ID Qty Part Number Size Description Vendor U1 1 LM20343MH HTSSOP IC, Switching Regulator TI C1 1 C3225X5R1E226M 1210 22µF, X5R, 25V, 20% TDK C2, C3 2 GRM21BR61E475KA12L 0805 4.
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LM20343 SNVS559B – MAY 2008 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision A (April 2013) to Revision B • 24 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 29-May-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LM20343MHE/NOPB HTSSOP PWP 20 250 178.0 16.4 LM20343MHX/NOPB HTSSOP PWP 20 2500 330.0 16.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.95 7.1 1.6 8.0 16.0 Q1 6.95 7.1 1.6 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 29-May-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM20343MHE/NOPB HTSSOP PWP LM20343MHX/NOPB HTSSOP PWP 20 250 210.0 185.0 35.0 20 2500 367.0 367.0 35.
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MECHANICAL DATA PWP0020A MXA20A (Rev C) www.ti.
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