Datasheet

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PGOOD

LM21212-1

OUT

AGND

COMP

PVIN

SYNC

OUT

FB1

FB2

PGND

AVIN

11-16

8,9,10

5,6,7

SS/

TRK

optional

HTSSOP-20

optional

LM21212-1

www.ti.com

SNVS671E –FEBRUARY 2011–REVISED MARCH 2013

12A High Efficiency Synchronous Point of Load Buck Regulator with Frequency

Synchronization

Check for Samples: LM21212-1

FEATURES

DESCRIPTION

The LM21212-1 is a monolithic synchronous point of

• Integrated 7.0 mΩ High Side and 4.3 mΩ Low

load buck regulator that is capable of delivering up to

Side FET Switches

12A of continuous output current while producing an

• 300 kHz to 1.5 MHz Frequency SYNC pin

output voltage down to 0.6V with outstanding

• Adjustable Output Voltage From 0.6V to V

efficiency. The device is optimized to work over an

input voltage range of 2.95V to 5.5V, making it suited

(100% duty cycle capable), ±1% Reference

for a wide variety of low voltage systems. The voltage

• Input Voltage Range 2.95V to 5.5V

mode control loop provides high noise immunity,

• Startup Into Pre-Biased Loads

narrow duty cycle capability and can be compensated

• Output Voltage Tracking Capability

to be stable with any type of output capacitance,

providing maximum flexibility and ease of use.

• Wide Bandwidth Voltage Loop Error Amplifier

The LM21212-1 features internal over voltage

• Adjustable Soft-Start With External Capacitor

protection (OVP) and over-current protection (OCP)

• Precision Enable Pin With Hysteresis

for increased system reliability. A precision enable pin

• Integrated OVP, OCP, OTP, UVLO and Power-

and integrated UVLO allow turn-on of the device to

Good

be tightly controlled and sequenced. Startup inrush

currents are limited by both an internally fixed and

• Thermally Enhanced HTSSOP-20 Exposed Pad

externally adjustable soft-start circuit. Fault detection

Package

and supply sequencing are possible with the

integrated power good circuit.

APPLICATIONS

The LM21212-1 is designed to work well in multi-rail

• Broadband, Networking and Wireless

power supply architectures. The output voltage of the

Communications

device can be configured to track an external voltage

• High-Performance FPGAs, ASICs and

rail using the SS/TRK pin. The switching frequency

Microprocessors

can be synchronized to the falling edge of a clock

between frequencies of 300kHz to 1.5MHz.

• Simple to Design, High Efficiency Point of

Load Regulation From a 5V or 3.3V Bus

If the output is pre-biased at startup, it will not sink

current, allowing the output to smoothly rise past the

pre-biased voltage. The regulator is offered in a 20-

pin HTSSOP package with an exposed pad that can

be soldered to the PCB, eliminating the need for

bulky heatsinks.

SIMPLIFIED APPLICATION CIRCUIT

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (33 pages)

PAGE 1
LM21212-1 www.ti.com SNVS671E – FEBRUARY 2011 – REVISED MARCH 2013 12A High Efficiency Synchronous Point of Load Buck Regulator with Frequency Synchronization Check for Samples: LM21212-1 FEATURES DESCRIPTION • The LM21212-1 is a monolithic synchronous point of load buck regulator that is capable of delivering up to 12A of continuous output current while producing an output voltage down to 0.6V with outstanding efficiency. The device is optimized to work over an input voltage range of 2.95V to 5.
PAGE 2
LM21212-1 SNVS671E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com CONNECTION DIAGRAM Top View 20 AGND SYNC 1 SS/TRK 2 19 FB 18 COMP EN 3 AVIN 4 17 PGOOD PVIN 5 16 SW PVIN 6 EP 15 SW PVIN 7 14 SW PGND 8 13 SW PGND 9 12 SW PGND 10 11 SW Figure 1. Top View HTSSOP-20 Package PIN DESCRIPTIONS 2 Pins Name Description 1 SYNC Frequency Synchronization input pin. Applying a clock signal to this pin will force the device to switch at the clock frequency.
PAGE 3
LM21212-1 www.ti.com SNVS671E – FEBRUARY 2011 – REVISED MARCH 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) PVIN (3), AVIN to GND −0.3V to +6V SW (4), EN, FB, COMP, PGOOD, SS/TRK to GND −0.3V to PVIN + 0.3V −65°C to 150°C Storage Temperature Lead Temperature (Soldering, 10 sec.
PAGE 4
LM21212-1 SNVS671E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Unless otherwise stated, the following conditions apply: VPVIN, AVIN = 5V. Limits in standard type are for TJ = 25°C only, limits in bold face type apply over the junction temperature (TJ) range of −40°C to +125°C. Minimum and maximum limits are specified through test, design, or statistical correlation.
PAGE 5
LM21212-1 www.ti.com SNVS671E – FEBRUARY 2011 – REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise specified: VVIN = 5V, VOUT = 1.2V, L= 0.56µH (1.8mΩ RDCR), CSS = 33nF, fSW = 1 MHz, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. Efficiency 96 FSW = 500kHz FSW = 1MHz FSW = 1.5MHz 94 VOUT = 3.3 VOUT = 1.
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LM21212-1 SNVS671E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: VVIN = 5V, VOUT = 1.2V, L= 0.56µH (1.8mΩ RDCR), CSS = 33nF, fSW = 1 MHz, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. Line Regulation Non-Switching IQTOTAL vs. VIN 0.10 1.5 0.06 1.4 IPVIN+ IAVIN(mA) 0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 3.0 1.3 1.2 1.1 IOUT = 0A IOUT = 12A 3.5 4.0 4.5 5.
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LM21212-1 www.ti.com SNVS671E – FEBRUARY 2011 – REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: VVIN = 5V, VOUT = 1.2V, L= 0.56µH (1.8mΩ RDCR), CSS = 33nF, fSW = 1 MHz, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. Enable Low Current vs. Temperature OVP/UVP Threshold vs. Temperature 58 0.68 56 0.66 54 0.64 VOVP,VUVP(V) SHUTDOWN CURRENT ISD( A) 60 52 50 48 46 44 VUVP VOVP 0.62 0.60 0.58 0.57 0.
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LM21212-1 SNVS671E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: VVIN = 5V, VOUT = 1.2V, L= 0.56µH (1.8mΩ RDCR), CSS = 33nF, fSW = 1 MHz, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. SYNC Signal Lost SYNC Signal Acquired VOUT (200mV/Div) VOUT (200 mV/Div) VSYNC (2V/Div) VSYNC (2V/Div) VSWITCH (2V/Div) VSWITCH (2V/Div) 4 µs/DIV 4 µs/DIV Figure 17. Figure 18.
PAGE 9
LM21212-1 www.ti.com SNVS671E – FEBRUARY 2011 – REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: VVIN = 5V, VOUT = 1.2V, L= 0.56µH (1.8mΩ RDCR), CSS = 33nF, fSW = 1 MHz, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others.
PAGE 10
LM21212-1 SNVS671E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com BLOCK DIAGRAM PLL SYNC Ilimit high VREF AVIN PVIN Over temp + - PVIN UVLO 2.7V + - SD OR Driver Precision enable AVIN 1.35V + - EN Control Logic PWM comparator AVIN OSC RAMP + - Zero-cross + - PWM SW INT SS PVIN + SS/TRK 0.6V EA Driver FB OVP COMP 0.68V 0.
PAGE 11
LM21212-1 www.ti.com SNVS671E – FEBRUARY 2011 – REVISED MARCH 2013 OPERATION DESCRIPTION GENERAL The LM21212-1 switching regulator features all of the functions necessary to implement an efficient low voltage buck regulator using a minimum number of external components. This easy to use regulator features two integrated switches and is capable of supplying up to 12A of continuous output current.
PAGE 12
LM21212-1 SNVS671E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com UVLO The LM21212-1 has a built-in under-voltage lockout protection circuit that keeps the device from switching until the input voltage reaches 2.7V (typical). The UVLO threshold has 200 mV of hysteresis that keeps the device from responding to power-on glitches during start up.
PAGE 13
LM21212-1 www.ti.com SNVS671E – FEBRUARY 2011 – REVISED MARCH 2013 Iclr IL Iclf VSS VFB 100 mV VOUT VSW CURRENT LIMIT SHORT-CIRCUIT SHORT-CIRCUIT REMOVED Figure 26. Current Limit Conditions THERMAL PROTECTION Internal thermal shutdown circuitry is provided to protect the integrated circuit in the event that the maximum junction temperature is exceeded. When activated, typically at 165°C, the LM21212-1 tri-states the power FETs and resets soft start.
PAGE 14
LM21212-1 SNVS671E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com tRESETSS Vss 0.6V Vovp VOVPHYS VFB Vuvp VUVPHYS VEN VPGOOD VSW OVP UVP DISABLE tPGDGL PRE-BIASED STARTUP tPGDGH Figure 27. PGOOD Conditions LIGHT LOAD OPERATION The LM21212-1 offers increased efficiency when operating at light loads.
PAGE 15
LM21212-1 SNVS671E – FEBRUARY 2011 – REVISED MARCH 2013 Switchnode Voltage www.ti.com Continuous Conduction Mode (CCM) VIN Time (s) Inductor Current Continuous Conduction Mode (CCM) IAVERAGE Inductor Current Time (s) DCM - CCM Boundary IAVERAGE Switchnode Voltage Time (s) Discontinuous Conduction Mode (DCM) VIN Inductor Current Time (s) Discontinuous Conduction Mode (DCM) IPeak Time (s) Figure 28.
PAGE 16
LM21212-1 SNVS671E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com DESIGN GUIDE OUTPUT VOLTAGE The first step in designing the LM21212-1 application is setting the output voltage. This is done by using a voltage divider between VOUT and AGND, with the middle node connected to VFB. When operating under steadystate conditions, the LM21212-1 will force VOUT such that VFB is driven to 0.6 V. VOUT LM21212-1 RFB1 0.6V FB RFB2 Figure 29.
PAGE 17
LM21212-1 www.ti.com SNVS671E – FEBRUARY 2011 – REVISED MARCH 2013 SOFT START When EN has exceeded 1.35V, and both PVIN and AVIN have exceeded the UVLO threshold, the LM21212-1 will begin charging the output linearly to the voltage level dictated by the feedback resistor network. The LM21212-1 employs a user adjustable soft start circuit to lengthen the charging time of the output set by a capacitor from the soft start pin to ground. After enable exceeds 1.
PAGE 18
LM21212-1 SNVS671E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com VSW VIN Time IL IL AVG = IOUT 'IL Time Figure 32. Switch and Inductor Current Waveforms Once the ripple current has been determined, the appropriate inductor size can be calculated using the following equation: L= (VIN ± VOUT) D üIL fSW (5) OUTPUT CAPACITOR SELECTION The output capacitor, COUT, filters the inductor ripple current and provides a source of charge for transient load conditions.
PAGE 19
LM21212-1 www.ti.com SNVS671E – FEBRUARY 2011 – REVISED MARCH 2013 INPUT CAPACITOR SELECTION Quality input capacitors are necessary to limit the ripple voltage at the PVIN pin while supplying most of the switch current during the on-time. Additionally, they help minimize input voltage droop in an output current transient condition. In general, it is recommended to use a ceramic capacitor for the input as it provides both a low impedance and small footprint.
PAGE 20
LM21212-1 SNVS671E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com The power train consists of the output inductor (L) with DCR (DC resistance RDCR), output capacitor (C0) with ESR (effective series resistance RESR), and load resistance (Ro). The error amplifier (EA) constantly forces FB to 0.6V. The passive compensation components around the error amplifier help maintain system stability.
PAGE 21
LM21212-1 www.ti.com SNVS671E – FEBRUARY 2011 – REVISED MARCH 2013 The pole located at the origin gives high open loop gain at DC, translating into improved load regulation accuracy. This pole occurs at a very low frequency due to the limited gain of the error amplifier, however, it can be approximated at DC for the purposes of compensation. The other two poles and two zeros can be located accordingly to stabilize the voltage mode loop depending on the power stage complex poles and Q.
PAGE 22
LM21212-1 SNVS671E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com where ΔVRAMP is the oscillator peak-to-peak ramp voltage (nominally 0.8V), and fCROSSOVER is the frequency at which the open-loop gain is a magnitude of 1. It is recommended that the fcrossover not exceed one-fifth of the switching frequency. The output capacitance, CO, depends on capacitor chemistry and bias voltage. For MultiLayer Ceramic Capacitors (MLCC), the total capacitance will degrade as the DC bias voltage is increased.
PAGE 23
LM21212-1 www.ti.com SNVS671E – FEBRUARY 2011 – REVISED MARCH 2013 GAIN PHASE 150 160 140 120 GAIN (dB) 100 100 80 60 50 40 20 0 PHASE MARGIN (°) 200 0 -20 -50 -40 10 100 1k 10k 100k FREQUENCY (Hz) 1M Figure 36. Loop Response It is important to verify the stability by either observing the load transient response or by using a network analyzer. A phase margin between 45° and 70° is usually desired for voltage mode systems.
PAGE 24
LM21212-1 SNVS671E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com THERMAL RESISTANCE ( JA) 30 28 26 24 22 20 18 16 14 12 10 2 3 4 5 6 7 8 2 BOARD AREA (in ) 9 10 Figure 37. Thermal Resistance vs PCB Area (4 Layer Board) Figure 38 shows a plot of the maximum ambient temperature vs. output current for the typical application circuit shown in Figure 40, assuming a θJA value of 24 °C/W. MAX. AMBIENT TEMPERATURE (°C) 125 120 115 110 105 100 95 90 85 80 0 2 4 6 8 IOUT (A) 10 12 Figure 38.
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LM21212-1 www.ti.com 3. 4. 5. 6. SNVS671E – FEBRUARY 2011 – REVISED MARCH 2013 a wide trace to minimize conductive losses. The inductor can be placed on the bottom side of the PCB relative to the LM21212-1, but care must be taken to not allow any coupling of the magnetic field of the inductor into the sensitive feedback or compensation traces. Have a solid ground plane between PGND, the EP and the input and output cap. ground connections.
PAGE 26
LM21212-1 SNVS671E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com HTSSOP-20 5,6,7 VIN 3 RF 4 CIN1 CIN2 CIN3 CF LO PVIN SW VOUT CC3 EN RFB1 RC2 AVIN LM21212-1 FB CSS 11-16 2 SS / TRK COMP CO1 CO2 CO3 19 18 CC1 RC1 RFB2 CC2 500 kHz VIN 1 17 SYNC PGOOD PGND AGND 8,9,10 RPGOOD 20 Figure 40. Typical Application Schematic 1 Table 1. Bill of Materials (VIN = 3.3 - 5.5V, VOUT = 1.
PAGE 27
LM21212-1 www.ti.com SNVS671E – FEBRUARY 2011 – REVISED MARCH 2013 HTSSOP-20 5,6,7 VIN CIN1 RF REN1 3 4 CF REN2 LO PVIN SW VOUT CC3 EN RFB1 RC2 AVIN LM21212-1 FB CSS 11-16 2 SS/ TRK COMP CO1 CO2 19 18 CC1 R C1 RFB2 CC2 VIN OPEN 1 SYNC PGOOD 17 RPGOOD PGND AGND 8,9,10 20 Figure 41. Typical Application Schematic 2 Table 2. Bill of Materials (VIN = 4.0 - 5.5V, VOUT = 0.
PAGE 28
LM21212-1 SNVS671E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision D (March 2013) to Revision E • 28 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
PAGE 29
PACKAGE OPTION ADDENDUM www.ti.
PAGE 30
PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LM21212MHE-1/NOPB HTSSOP PWP 20 250 178.0 16.4 LM21212MHX-1/NOPB HTSSOP PWP 20 2500 330.0 16.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.95 7.1 1.6 8.0 16.0 Q1 6.95 7.1 1.6 8.0 16.
PAGE 31
PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM21212MHE-1/NOPB HTSSOP PWP LM21212MHX-1/NOPB HTSSOP PWP 20 250 210.0 185.0 35.0 20 2500 367.0 367.0 35.
PAGE 32
MECHANICAL DATA PWP0020AA MYB20XX (REV E) 4214875/A NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. This drawing is subject to change without notice. C. Reference JEDEC Registration MO-153, Variation ACT. www.ti.
PAGE 33
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