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LM21215A

www.ti.com

SNOSB87B –MARCH 2011–REVISED MARCH 2013

LM21215A-1 15A High Efficiency Synchronous Buck Regulator with Frequency

Synchronization

Check for Samples: LM21215A

FEATURES

DESCRIPTION

The LM21215A-1 is a monolithic synchronous buck

• Integrated 7.0 mΩ High Side and 4.3 mΩ Low

regulator that is capable of delivering up to 15A of

Side FET Switches

continuous output current while producing an output

• 300 kHz to 1.5 MHz Frequency SYNC Pin

voltage down to 0.6V with outstanding efficiency. The

• Adjustable Output Voltage from 0.6V to V

device is optimized to work over an input voltage

range of 2.95V to 5.5V, making it suited for a wide

(100% Duty Cycle Capable), ±1% Reference

variety of low voltage systems. The voltage mode

• Input Voltage Range 2.95V to 5.5V

control loop provides high noise immunity, narrow

• Startup into Pre-biased Loads

duty cycle capability and can be compensated to be

• Output Voltage Tracking Capability

stable with any type of output capacitance, providing

maximum flexibility and ease of use.

• Wide Bandwidth Voltage Loop Error Amplifier

The LM21215A-1 features internal over voltage

• Adjustable Soft-start with External Capacitor

protection (OVP) and over-current protection (OCP)

• Precision Enable Pin with Hysteresis

for increased system reliability. A precision enable pin

• Integrated OVP, OCP, OTP, UVLO and Power-

and integrated UVLO allow turn-on of the device to

Good

be tightly controlled and sequenced. Startup inrush

currents are limited by both an internally fixed and

• Thermally Enhanced HTSSOP-20 Exposed Pad

externally adjustable soft-start circuit. Fault detection

Package

and supply sequencing are possible with the

integrated power good circuit.

APPLICATIONS

The LM21215A-1 is designed to work well in multi-rail

• Broadband, Networking and Wireless

power supply architectures. The output voltage of the

Communications

device can be configured to track an external voltage

• High-performance FPGAs, ASICs and

rail using the SS/TRK pin. The switching frequency

Microprocessors

can be synchronized to the falling edge of a clock

between frequencies of 300kHz to 1.5MHz.

• Simple to Design, High Efficiency Point of

Load Regulation from a 5V or 3.3V Bus

If the output is pre-biased at startup, it will not sink

current, allowing the output to smoothly rise past the

pre-biased voltage. The regulator is offered in a 20-

pin HTSSOP package with an exposed pad that can

be soldered to the PCB, eliminating the need for

bulky heatsinks.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (32 pages)

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LM21215A www.ti.com SNOSB87B – MARCH 2011 – REVISED MARCH 2013 LM21215A-1 15A High Efficiency Synchronous Buck Regulator with Frequency Synchronization Check for Samples: LM21215A FEATURES DESCRIPTION • The LM21215A-1 is a monolithic synchronous buck regulator that is capable of delivering up to 15A of continuous output current while producing an output voltage down to 0.6V with outstanding efficiency. The device is optimized to work over an input voltage range of 2.95V to 5.
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LM21215A SNOSB87B – MARCH 2011 – REVISED MARCH 2013 www.ti.
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LM21215A www.ti.com SNOSB87B – MARCH 2011 – REVISED MARCH 2013 PIN DESCRIPTIONS Pins Name Description 1 SYNC Frequency Synchronization input pin. Applying a clock signal to this pin will force the device to switch at the clock frequency. If left unconnected, the frequency will default to 500 kHz. 2 SS/TRK 3 EN 4 AVIN Analog input voltage supply that generates the internal bias.
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LM21215A SNOSB87B – MARCH 2011 – REVISED MARCH 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) PVIN (3), AVIN to GND −0.3V to +6V SW (4), EN, FB, COMP, PGOOD, SS/TRK to GND −0.3V to PVIN + 0.
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LM21215A www.ti.com SNOSB87B – MARCH 2011 – REVISED MARCH 2013 ELECTRICAL CHARACTERISTICS (continued) Unless otherwise stated, the following conditions apply: VPVIN, AVIN = 5V. Limits in standard type are for TJ = 25°C only, limits in bold face type apply over the junction temperature (TJ) range of −40°C to +125°C. Minimum and maximum limits are specified through test, design, or statistical correlation.
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LM21215A SNOSB87B – MARCH 2011 – REVISED MARCH 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise specified: VVIN = 5V, VOUT = 1.2V, L= 0.56µH (1.8mΩ RDCR), CSS = 33nF, fSW = 500 kHz, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. Efficiency 100 98 96 EFFICIENCY (%) EFFICIENCY (%) VOUT = 1.2V VOUT = 3.3V 98 96 94 92 90 88 86 94 92 90 88 86 84 84 82 82 80 80 0 3 6 9 12 OUTPUT CURRENT (A) Figure 2.
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LM21215A www.ti.com SNOSB87B – MARCH 2011 – REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: VVIN = 5V, VOUT = 1.2V, L= 0.56µH (1.8mΩ RDCR), CSS = 33nF, fSW = 500 kHz, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. Non-Switching IAVIN and IPVIN vs. Temperature IAVIN IPVIN 0.602 0.172 1.14 0.164 1.11 0.156 1.08 0.148 1.05 0.140 1.02 0.132 0.99 0.124 0.96 0.116 0.93 0.108 0.601 VFB(V) 0.600 0.
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LM21215A SNOSB87B – MARCH 2011 – REVISED MARCH 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: VVIN = 5V, VOUT = 1.2V, L= 0.56µH (1.8mΩ RDCR), CSS = 33nF, fSW = 500 kHz, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. Minimum On-Time vs. Temperature FET Resistance vs.
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LM21215A www.ti.com SNOSB87B – MARCH 2011 – REVISED MARCH 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified: VVIN = 5V, VOUT = 1.2V, L= 0.56µH (1.8mΩ RDCR), CSS = 33nF, fSW = 500 kHz, TA = 25°C for efficiency curves, loop gain plots and waveforms, and TJ = 25°C for all others. Output Voltage Ripple Startup with Prebiased Output VOUT (500 mV/Div) VOUT (10 mV/Div) VPGOOD (5V/Div) VENABLE (5V/Div) Figure 20. 2 µs/DIV Figure 21.
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LM21215A SNOSB87B – MARCH 2011 – REVISED MARCH 2013 www.ti.com BLOCK DIAGRAM PLL SYNC Ilimit high VREF AVIN PVIN Over temp + - PVIN UVLO 2.7V + - SD OR Driver Precision enable AVIN 1.35V + - EN Control Logic PWM comparator AVIN OSC RAMP + - Zero-cross + - PWM SW INT SS PVIN + SS/TRK 0.6V EA Driver FB OVP COMP 0.68V 0.
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LM21215A www.ti.com SNOSB87B – MARCH 2011 – REVISED MARCH 2013 OPERATION DESCRIPTION GENERAL The LM21215A-1 switching regulator features all of the functions necessary to implement an efficient low voltage buck regulator using a minimum number of external components. This easy to use regulator features two integrated switches and is capable of supplying up to 15A of continuous output current.
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LM21215A SNOSB87B – MARCH 2011 – REVISED MARCH 2013 www.ti.com CURRENT LIMIT The LM21215A-1 has current limit protection to avoid dangerous current levels on the power FETs and inductor. A current limit condition is met when the current through the high side FET exceeds the rising current limit level (ICLR). The control circuitry will respond to this event by turning off the high side FET and turning on the low side FET.
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LM21215A www.ti.com SNOSB87B – MARCH 2011 – REVISED MARCH 2013 POWERGOOD FLAG The PGOOD pin provides the user with a way to monitor the status of the LM21215A-1. In order to use the PGOOD pin, the application must provide a pull-up resistor to a desired DC voltage (i.e. Vin). PGOOD will respond to a fault condition by pulling the PGOOD pin low with the open-drain output.
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LM21215A Switchnode Voltage SNOSB87B – MARCH 2011 – REVISED MARCH 2013 www.ti.com Continuous Conduction Mode (CCM) VIN Time (s) Inductor Current Continuous Conduction Mode (CCM) IAVERAGE Inductor Current Time (s) DCM - CCM Boundary IAVERAGE Switchnode Voltage Time (s) Discontinuous Conduction Mode (DCM) VIN Inductor Current Time (s) Discontinuous Conduction Mode (DCM) IPeak Time (s) Figure 28.
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LM21215A www.ti.com SNOSB87B – MARCH 2011 – REVISED MARCH 2013 Design Guide OUTPUT VOLTAGE The first step in designing the LM21215A-1 application is setting the output voltage. This is done by using a voltage divider between VOUT and AGND, with the middle node connected to VFB. When operating under steadystate conditions, the LM21215A-1 will force VOUT such that VFB is driven to 0.6 V. VOUT LM21215A-1 RFB1 0.6V FB RFB2 Figure 29.
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LM21215A SNOSB87B – MARCH 2011 – REVISED MARCH 2013 www.ti.com SOFT START When EN has exceeded 1.35V, and both PVIN and AVIN have exceeded the UVLO threshold, the LM21215A-1 will begin charging the output linearly to the voltage level dictated by the feedback resistor network. The LM21215A-1 employs a user adjustable soft start circuit to lengthen the charging time of the output set by a capacitor from the soft start pin to ground. After enable exceeds 1.
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LM21215A www.ti.com SNOSB87B – MARCH 2011 – REVISED MARCH 2013 VSW VIN Time IL IL AVG = IOUT 'IL Time Figure 32. Switch and Inductor Current Waveforms Once the ripple current has been determined, the appropriate inductor size can be calculated using the following equation: L= (VIN ± VOUT) D üIL fSW (5) OUTPUT CAPACITOR SELECTION The output capacitor, COUT, filters the inductor ripple current and provides a source of charge for transient load conditions.
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LM21215A SNOSB87B – MARCH 2011 – REVISED MARCH 2013 www.ti.com The amount of output ripple that can be tolerated is application specific; however a general recommendation is to keep the output ripple less than 1% of the rated output voltage. Keep in mind ceramic capacitors are sometimes preferred because they have very low ESR; however, depending on package and voltage rating of the capacitor the value of the capacitance can drop significantly with applied voltage.
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LM21215A www.ti.com SNOSB87B – MARCH 2011 – REVISED MARCH 2013 PWM Modulator Power Train VIN RDCR DRIVER LOUT VOUT SW RESR RO COUT PWM + Error Amplifier and Compensation COMP + EA - CC1 RC1 0.6V FB RFB1 RC2 C C3 RFB2 CC2 Figure 33. Loop Diagram The power train consists of the output inductor (L) with DCR (DC resistance RDCR), output capacitor (C0) with ESR (effective series resistance RESR), and load resistance (Ro). The error amplifier (EA) constantly forces FB to 0.6V.
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LM21215A SNOSB87B – MARCH 2011 – REVISED MARCH 2013 www.ti.com 60 0 -40 40 GAIN (dB) -120 0 -160 -20 -200 PHASE (°) -80 20 -240 -40 -280 -60 -320 GAIN PHASE -80 100 -360 1k 10k 100k 1M FREQUENCY (HZ) 10M Figure 34. Power Train Bode Plot The complex poles created by the output inductor and capacitor cause a 180° phase shift at the resonant frequency as seen in Figure 34. The phase is boosted back up to -90° because of the output capacitor ESR zero.
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LM21215A www.ti.com SNOSB87B – MARCH 2011 – REVISED MARCH 2013 The dependancy of the pole and zero locations on the compensation components is described below. fLC 1 fZ1 = 2 = 2SR C C1 C1 1 fZ2 = fLC = 2S(R + R )C C1 FB1 C3 fP1 = fESR = fP2 = fsw 2 1 2SRC2CC3 CC1 + CC2 = 2SR C C C1 C1 C2 An example of the step-by-step procedure to generate compensation component values using the typical application setup (see Figure 40) is given.
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LM21215A SNOSB87B – MARCH 2011 – REVISED MARCH 2013 www.ti.com RC2 can then be calculated to set the second zero at the LC double pole frequency: RC2 = RFB1 fLC fESR - fLC = 166: (16) Last, CC3 can be calculated to place a pole at the same frequency as the zero created by the output capacitor ESR: 1 2SfESRRC2 = 898 pF CC3 = (17) An illustration of the total loop response can be seen in Figure 36.
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LM21215A www.ti.com SNOSB87B – MARCH 2011 – REVISED MARCH 2013 Figure 37, shown below, provides a better approximation of the θJA for a given PCB copper area. The PCB used in this test consisted of 4 layers: 1oz. copper was used for the internal layers while the external layers were plated to 2oz. copper weight. To provide an optimal thermal connection, a 3 x 4 array of 8 mil. vias under the thermal pad were used, and an additional sixteen 8 mil.
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LM21215A SNOSB87B – MARCH 2011 – REVISED MARCH 2013 www.ti.com PCB LAYOUT CONSIDERATIONS PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce, and resistive voltage loss in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability. Good layout can be implemented by following a few simple design rules. 1.
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LM21215A www.ti.com SNOSB87B – MARCH 2011 – REVISED MARCH 2013 eTSSOP-20 5,6,7 VIN 3 RF 4 CIN1 CIN2 CIN3 CF PVIN LO SW VOUT CC3 EN RFB1 RC2 AVIN LM21215A-1 CSS 11-16 2 SS / TRK FB COMP CO1 CO2 CO3 19 18 CC1 RC1 RFB2 CC2 VIN OPEN 1 17 SYNC PGOOD PGND AGND 8,9,10 RPGOOD 20 Figure 40. Typical Application Schematic 1 Table 1. Bill of Materials (VIN = 3.3V - 5.5V, VOUT = 1.
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LM21215A SNOSB87B – MARCH 2011 – REVISED MARCH 2013 www.ti.com eTSSOP-20 LO 5,6,7 VIN PVIN CIN1 RF REN1 3 4 CF SW CC3 RFB1 RC2 AVIN FB CSS VOUT EN LM21215A-1 REN2 11-16 2 SS/ TRK COMP CO1 CO2 19 18 CC1 RC1 RFB2 CC2 VIN 1 SYNC 1 MHz PGOOD 17 RPGOOD PGND AGND 8,9,10 20 Figure 41. Typical Application Schematic 2 Table 2. Bill of Materials (VIN = 4.0V - 5.5V, VOUT = 0.
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LM21215A www.ti.com SNOSB87B – MARCH 2011 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision A (March 2013) to Revision B • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM21215AMHE-1/NOPB HTSSOP PWP 20 250 178.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 LM21215AMHX-1/NOPB HTSSOP PWP 20 2500 330.0 16.4 6.95 7.1 1.6 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM21215AMHE-1/NOPB HTSSOP PWP LM21215AMHX-1/NOPB HTSSOP PWP 20 250 210.0 185.0 35.0 20 2500 367.0 367.0 35.
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MECHANICAL DATA PWP0020AA MYB20XX (REV E) 4214875/A NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. This drawing is subject to change without notice. C. Reference JEDEC Registration MO-153, Variation ACT. www.ti.
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