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LM25037

UVLO

PGND

AGND

COMP

OUTB

OUTA

VCC

RT1

REF

RES

VIN

VOUT

RT2

RAMP

Isolated

Feedback

LM25037, LM25037-Q1

www.ti.com

SNVS572D –JULY 2008–REVISED MARCH 2013

LM25037/LM25037-Q1 Dual-Mode PWM Controller With Alternating Outputs

Check for Samples: LM25037, LM25037-Q1

FEATURES

DESCRIPTION

The LM25037 PWM controller contains all the

• LM25037-Q1 is an Automotive Grade Product

features necessary to implement balanced double-

that is AEC-Q100 Grade 1 Qualified (-40°C to

ended power converter topologies, such as push-pull,

125°C Operating Junction Temperature)

half-bridge and full-bridge. These double-ended

• Ultra Wide Input Operating Range from 5.5V to

topologies allow for higher efficiencies and greater

75V

power densities compared to common single-ended

topologies such as the flyback and forward. The

• Alternating Outputs for Double-ended

LM25037 can be configured for either voltage mode

Topologies

or current mode control with minimum external

• Current-mode or Feed-forward Voltage-mode

components. Two alternating gate drive outputs are

Control

provided, each capable of 1.2A peak output current.

• Programmable Maximum Duty Cycle Limit

The LM25037 can be configured to operate directly

from the input voltage rail over an ultra-wide range of

• 2.0% Feedback Reference Accuracy

5.5V to 75V. Additional features include

• High Gain-bandwidth Error Amplifier

programmable maximum duty cycle limit, line under-

• Programmable Line Under-voltage Lockout

voltage lockout, cycle-by-cycle current limit and a

(UVLO) with Adjustable Hysteresis

hiccup mode fault protection with adjustable timeout

delay, soft-start and a 2 MHz capable oscillator with

• Versatile Dual Mode Over-current Protection

synchronization capability, precision reference and

with Hiccup Delay Timer

thermal shutdown.

• Programmable Soft-start

• Precision 5V Reference Output

PACKAGE

• Current Sense Leading Edge Blanking

• 16-Lead TSSOP

• Resistor Programmed 2 MHz Capable

Oscillator

• Oscillator Synchronization Capability with Low

Frequency Lockout Protection

Simplified Push-Pull Power Converter

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (31 pages)

PAGE 1
LM25037, LM25037-Q1 www.ti.com SNVS572D – JULY 2008 – REVISED MARCH 2013 LM25037/LM25037-Q1 Dual-Mode PWM Controller With Alternating Outputs Check for Samples: LM25037, LM25037-Q1 FEATURES DESCRIPTION • The LM25037 PWM controller contains all the features necessary to implement balanced doubleended power converter topologies, such as push-pull, half-bridge and full-bridge.
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LM25037, LM25037-Q1 SNVS572D – JULY 2008 – REVISED MARCH 2013 www.ti.com Connection Diagram 1 16 VIN UVLO 2 15 REF COMP 3 14 VCC FB 4 13 OUTA RAMP LM25037 RT2 5 12 OUTB AGND 6 11 PGND RT1 7 10 SS CS 8 9 RES Figure 1. Top View 16-Lead TSSOP Package See PW Package PIN DESCRIPTIONS 2 Pin Name Description Application Information 1 RAMP Pulse width modulator ramp Modulation ramp for the PWM comparator.
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LM25037, LM25037-Q1 www.ti.com SNVS572D – JULY 2008 – REVISED MARCH 2013 PIN DESCRIPTIONS (continued) Pin Name 16 VIN Description Application Information Input voltage source Input to the VCC Start-up regulator. Operating input range is 5.5V to 75V. For power sources outside of this range, the LM25037 can be biased directly at VCC by an external regulator. These devices have limited built-in ESD protection.
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LM25037, LM25037-Q1 SNVS572D – JULY 2008 – REVISED MARCH 2013 www.ti.com Electrical Characteristics (continued) Specifications with standard typeface are for TJ = 25°C, and those with boldface type apply over full operating junction temperature range of −40°C to + 125°C. VVIN = 12V, VVCC = 10V, RRT1 = 30.1 kΩ, RRT2 = 30.1 kΩ, VUVLO = 3V unless otherwise stated.(1)(2) Symbol VREF(UV) Parameter Conditions Min Hysteresis Typ Max 0.
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LM25037, LM25037-Q1 www.ti.com SNVS572D – JULY 2008 – REVISED MARCH 2013 Electrical Characteristics (continued) Specifications with standard typeface are for TJ = 25°C, and those with boldface type apply over full operating junction temperature range of −40°C to + 125°C. VVIN = 12V, VVCC = 10V, RRT1 = 30.1 kΩ, RRT2 = 30.1 kΩ, VUVLO = 3V unless otherwise stated.(1)(2) Symbol Parameter Conditions Min Typ Vcc-0.5 Vcc0.
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LM25037, LM25037-Q1 SNVS572D – JULY 2008 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics Typical Application Circuit Efficiency VVCC and VREF vs VVIN Figure 2. Figure 3. Start-Up Regulator Current (UVLO = 0) VVCC vs IVCC Figure 4. Figure 5. VREF vs IREF Feedback Amplifier Gain/Phase 180 50 150 40 120 30 90 20 60 10 30 0 -10 0 -30 -20 -60 -30 -90 -40 -120 -50 -150 -60 10k 100k 1M FREQUENCY Figure 6.
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LM25037, LM25037-Q1 www.ti.com SNVS572D – JULY 2008 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Oscillator Frequency vs RT1 Dead-Time vs RT2 Figure 8. Figure 9. VFB vs Temperature Oscillator Frequency vs Temperature Figure 10. Figure 11. Dead-Time vs Temperature Soft-Start and Restart Current vs Temperature Figure 12. Figure 13.
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LM25037, LM25037-Q1 SNVS572D – JULY 2008 – REVISED MARCH 2013 www.ti.com Block Diagram 7.7V LDO VCC VIN SHUTDOWN 0.45V UVLO 5V Reference STANDBY 1.25V REF VCC/REF UVLO MODE CONTROL LOGIC THERMAL LIMIT ( 165°C) UVLO HYSTERESIS (22 PA) VCC RT1/SYNC CLK J SET Q K CLR Q DRIVER OSCILLATOR RT2 S OUTA Q VCC R RAMP 1.25V DRIVER OUTB ERROR AMP FB +5V PGND 5k PWM COMP AGND PWM LOGIC 1V SS SS Buffer 2.0V +5V CS 0.
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LM25037, LM25037-Q1 www.ti.com SNVS572D – JULY 2008 – REVISED MARCH 2013 Functional Description The LM25037 PWM controller contains all the features necessary to implement double-ended power converter topologies such as push-pull, half-bridge and full-bridge. The unique architecture allows the modulator to be configured for either voltage-mode or current-mode control. The LM25037 provides two alternative gate driver outputs to drive the primary side power MOSFETs with programmable forced dead-time.
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LM25037, LM25037-Q1 SNVS572D – JULY 2008 – REVISED MARCH 2013 www.ti.com ERROR AMPLIFIER An internal high gain error amplifier is provided within the LM25037. The amplifier’s non-inverting reference is tied to a 1.25V reference. In non-isolated applications the power converter output is connected to the FB pin via the voltage setting resistors and loop compensation is connected between the COMP and FB pins. A typical gain/phase plot is shown in Typical Performance Characteristics.
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LM25037, LM25037-Q1 www.ti.com SNVS572D – JULY 2008 – REVISED MARCH 2013 an overload by leaving the RES pin open circuit. In this configuration, the first detection of current limit condition by the CS pin comparator will initiate a hiccup cycle with SS capacitor fully discharged and a delayed restart. 3. Delayed Hiccup: Connecting a capacitor to the RES pin provides a programmed interval of cycle-by-cycle limiting before initiating a hiccup mode restart, as previously described.
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LM25037, LM25037-Q1 SNVS572D – JULY 2008 – REVISED MARCH 2013 www.ti.com SOFT-START The soft-start circuit allows the regulator to gradually reach a steady state operating point, thereby reducing startup stresses and current surges. When bias is supplied to the LM25037, the SS pin capacitor is discharged by an internal MOSFET. When the UVLO, VCC and REF pins reach their operating thresholds, the SS capacitor is released and charged with a 100 µA current source.
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LM25037, LM25037-Q1 www.ti.com SNVS572D – JULY 2008 – REVISED MARCH 2013 SLOPE PROPORTIONAL TO Vin VIN Vin R FF COMP 1V Gate Drive RAMP C FF CLK LM25037 Figure 17. Feed-Forward Voltage Mode Configuration CURRENT MODE The LM25037 can be configured for current mode control by injecting a signal representative of primary current into the RAMP pin. One way to achieve this is shown in Figure 18. Filter components Rfilter and Cfilter are used to filter leading edge noise spikes.
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LM25037, LM25037-Q1 SNVS572D – JULY 2008 – REVISED MARCH 2013 www.ti.com V REF (5V) R slope RAMP CLK C slope LM 25037 Current Sense R filter cs CLK + LEB Rcs C filter Figure 18. Current Mode Configuration with Slope Compensation CLK CS OUTA OUTB COMP RAMP Slope Compensation OUTPUT OUTA OUTB Figure 19.
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LM25037, LM25037-Q1 www.ti.com RT2 = SNVS572D – JULY 2008 – REVISED MARCH 2013 Dead-Time 5.0 x 10 -12 50 ns
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LM25037, LM25037-Q1 SNVS572D – JULY 2008 – REVISED MARCH 2013 www.ti.com GATE DRIVER OUTPUTS (OUTA & OUTB) The LM25037 provides two alternating gate driver outputs, OUTA and OUTB. The internal gate drivers can each source and sink 1.2A peak each. The maximum duty cycle is inherently limited to less than 50% and is based on the value of RT2 resistor. As an example, if the COMP pin is in a high state, RT1 = 15K and RT2 = 20K then the outputs will operate at maximum duty cycle of 96%.
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LM25037, LM25037-Q1 www.ti.com SNVS572D – JULY 2008 – REVISED MARCH 2013 -1 RFF = FOSC x CFF x In 1 - VRAMP VINmin (3) For example, assuming a VRamp of 1 volt at VINmin (a good compromise of signal range and noise immunity), oscillator frequency, FOSC of 250 kHz, VINmin of 24 Volts, and CFF = 270 pF results in a value for RFF of 348 kΩ. SLOPE PROPORTIONAL TO Vin Vin R FF VIN 1V COMP Gate Drive RAMP CLK C FF LM25037 Figure 21.
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LM25037, LM25037-Q1 SNVS572D – JULY 2008 – REVISED MARCH 2013 www.ti.com Current mode control inherently provides line voltage feed-forward, cycle-by-cycle current limiting and ease of loop compensation as it removes the additional pole due to output inductor. Also, in push-pull and full-bridge converters, current mode control inherently balances volt-second product in both the phases by varying the duty cycle as needed to terminate the cycle at the same peak current for each output phase.
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LM25037, LM25037-Q1 www.ti.com SNVS572D – JULY 2008 – REVISED MARCH 2013 VIN and VCC The voltage applied to the VIN pin, which may be the same as the system voltage applied to the power transformer’s primary (VPWR), can vary in the range from 5.5V to 75V. The current into the VIN pin depends primarily on the gate charge provided by the output drivers, the switching frequency, and any external loads on the VCC and REF pins.
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LM25037, LM25037-Q1 SNVS572D – JULY 2008 – REVISED MARCH 2013 www.ti.com V PWR Current Sense Power Transformer Q1 VIN CS RF CF LM25037 R1 AGND Level Shift OUTA Q2 OUTB Figure 25. Current Sense Using Transformer Power Transformer VPWR Vin OUTA Q1 Q2 OUTB RF CS LM25037 CF R1 Figure 26.
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LM25037, LM25037-Q1 www.ti.com SNVS572D – JULY 2008 – REVISED MARCH 2013 UVLO DIVIDER SELECTION A dedicated comparator connected to the UVLO pin detects an input under-voltage condition. When the UVLO pin voltage is below 0.45V, the LM25037 controller is in a low current shutdown mode. For a UVLO pin voltage greater than 0.45V but less than 1.25V, the controller is in standby mode with VCC and REF regulators active but no switching. Once the UVLO pin voltage is greater than 1.
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LM25037, LM25037-Q1 SNVS572D – JULY 2008 – REVISED MARCH 2013 www.ti.com LM25037 5.0V VIN 22 PA R1 1.25V UVLO STANDBY STANDBY R2 OFF 0.45V SHUTDOWN Figure 28. Remote Standby and Disable Control HICCUP MODE CURRENT LIMIT RESTART (RES) The basic operation of the hiccup mode current limit is described in the functional description. The delay time to the initiation of a hiccup cycle is programmed by the selection of the RES pin capacitor CRES as illustrated in Figure 29.
PAGE 23
LM25037, LM25037-Q1 www.ti.com SNVS572D – JULY 2008 – REVISED MARCH 2013 If CSS = 0.01 µF, t3 is ≊ 400 µs. The time t2 provides a periodic cool-down time for the power converter in the event of a sustained overload or short circuit. This off time results in lower average input current and lower power dissipation within the power components. It is recommended that the ratio of t2 / (t1 + t3) be in the range of 5 to 10 to take advantage of this feature.
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LM25037, LM25037-Q1 SNVS572D – JULY 2008 – REVISED MARCH 2013 www.ti.com Figure 30.
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LM25037, LM25037-Q1 www.ti.com SNVS572D – JULY 2008 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision C (March 2013) to Revision D • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM25037MTX/NOPB TSSOP PW 16 2500 330.0 12.4 6.95 8.3 1.6 8.0 12.0 Q1 LM25037QMTX/NOPB TSSOP PW 16 2500 330.0 12.4 6.95 8.3 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM25037MTX/NOPB TSSOP PW 16 2500 367.0 367.0 35.0 LM25037QMTX/NOPB TSSOP PW 16 2500 367.0 367.0 35.
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