Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - hot swap controller Multi-purpose VSSOP 10 Surface-mount

Power

Good

UVLO/EN

PWRGNDTIMER

PGD

OUT

VIN SENSE GATE

LM25061

OUT

SYS

PGD

GND

LM25061

www.ti.com

SNVS611E –FEBRUARY 2011–REVISED MARCH 2013

LM25061 Positive Low Voltage Power Limiting Hot Swap Controller

Check for Samples: LM25061

FEATURES

APPLICATIONS

• Operating Range: +2.9V to +17V

• Server Backplane Systems

• In-rush Current Limit for Safe Board Insertion • Base Station Power Distribution Systems

into Live Power Sources

• Solid State Circuit Breaker

• Programmable Maximum Power Dissipation in

the External Pass Device PACKAGE

• Adjustable Current Limit

• VSSOP-10

• Circuit Breaker Function for Severe Over-

DESCRIPTION

Current Events

The LM25061 positive hot swap controller provides

• Internal High Side Charge Pump and Gate

intelligent control of the power supply voltage to the

Driver for External N-Channel MOSFET

load during insertion and removal of circuit cards from

• Adjustable Under-Voltage Lockout (UVLO) and

a live system backplane or other "hot" power sources.

Hysteresis

The LM25061 provides in-rush current control to limit

• Adjustable Output Voltage Monitoring and

system voltage droop and transients. The current limit

and power dissipation in the external series pass N-

Hysteresis

Channel MOSFET are programmable, ensuring

• Initial Insertion Timer Allows Ringing and

operation within the Safe Operating Area (SOA). The

Transients to Subside After System

POWER GOOD output indicates when the output

Connection

voltage exceeds a programmable threshold. The

• Programmable Fault Timer Avoids Nuisance

input under-voltage level and hysteresis are

Trips

programmable, as well as the initial insertion delay

time and fault detection time. The LM25061-1 latches

• Active High Open Drain POWER GOOD Output

off after a fault detection, while the LM25061-2

• Available in Latched Fault and Automatic

automatically restarts at a fixed duty cycle. The

Restart Versions

LM25061 is available in a 10 pin VSSOP package.

Typical Application

Figure 1. Positive Power Supply Control

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (29 pages)

PAGE 1
LM25061 www.ti.com SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 LM25061 Positive Low Voltage Power Limiting Hot Swap Controller Check for Samples: LM25061 FEATURES APPLICATIONS • • • • • 1 2 • • • • • • • • • • Operating Range: +2.
PAGE 2
LM25061 SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com Connection Diagram SENSE 1 10 VIN 2 9 UVLO/EN 3 8 PGD FB 4 7 PWR GND 5 6 TIMER GATE OUT Figure 2. Top View 10-Lead VSSOP PIN DESCRIPTIONS Pin # Name Description Applications Information 1 SENSE Current sense input The voltage across the current sense resistor (RS) is measured from VIN to this pin. If the voltage across RS reaches 50mV the load current is limited and the fault timer activates.
PAGE 3
LM25061 www.ti.com SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 Absolute Maximum Ratings (1) (2) (3) VIN to GND (4) -0.3V to 20V SENSE, OUT, PGD to GND -0.3V to 20V UVLO to GND -0.3V to 20V FB to GND -0.3V to 20V VIN to SENSE -0.3V to +0.3V ESD Rating (5) Human Body Model 2kV Storage Temperature -65°C to +150°C Junction Temperature +150°C Lead Temperature (soldering 4 sec) +260°C (1) (2) (3) (4) (5) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
PAGE 4
LM25061 SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com Electrical Characteristics (continued) Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +85°C. Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
PAGE 5
LM25061 www.ti.com SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 Typical Performance Characteristics Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 12V VIN Pin Input Current vs. VIN SENSE Pin Input Current Figure 3. Figure 4. OUT Pin Input Current GATE Pin Voltage Figure 5. Figure 6. GATE Pin Source Current MOSFET Power Dissipation Limit Figure 7. Figure 8.
PAGE 6
LM25061 SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 12V 6 PGD Pin Low Voltage vs. Sink Current Input Current, Enabled vs. Temperature Figure 9. Figure 10. UVLO Threshold vs. Temperature UVLO Hysteresis Current vs. Temperature Figure 11. Figure 12. FB Threshold vs. Temperature FB Hysteresis Current vs. Temperature Figure 13. Figure 14.
PAGE 7
LM25061 www.ti.com SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 12V Current Limit Threshold vs. Temperature Circuit Breaker Threshold vs. Temperature Figure 15. Figure 16. Power Limit Threshold vs. Temperature GATE Output Voltage vs. Temperature Figure 17. Figure 18. GATE Source Current vs. Temperature PGD Low Voltage vs. Temperature Figure 19. Figure 20.
PAGE 8
LM25061 SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com Block Diagram Q1 VSYS VOUT RS CIN CL R3 R1 VIN UVLO/EN SENSE GATE OUT VPGD FB R4 LM25061 R2 Power Good PGD TIMER CT GND RPG PWR RPWR Figure 21.
PAGE 9
LM25061 www.ti.com SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 Functional Description The LM25061 is designed to control the in-rush current to the load upon insertion of a circuit card into a live backplane or other "hot" power source, thereby limiting the voltage sag on the backplane’s supply voltage, and the dV/dt of the voltage applied to the load. Effects on other circuits in the system are minimized, preventing possible unintended resets.
PAGE 10
LM25061 SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com VSYS UVLO V IN POR 5.5 PA TIMER Pin GATE Pin 1.72V 80 PA 2.5 PA 2 mA 260 mA pull-down 2 mA pull-down 20 PA source I LIMIT Load Current Output Voltage (OUT Pin) FB Threshold PGD t1 Insertion Time t2 In- rush Limiting t3 Normal Operation Figure 23. Power Up Sequence (Current Limit only) Gate Control A charge pump provides the voltage at the GATE pin to enhance the N-Channel MOSFET’s gate.
PAGE 11
LM25061 www.ti.com SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 Current Limit The current limit threshold is reached when the voltage across the sense resistor RS (VIN to SENSE) reaches 50 mV. In the current limiting condition, the GATE voltage is controlled to limit the current in MOSFET Q1. While the current limit circuit is active, the fault timer is active as described in the Fault Timer & Restart section.
PAGE 12
LM25061 SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com The LM25061-2 provides an automatic restart sequence which consists of the TIMER pin cycling between 1.72V and 1V seven times after the Fault Timeout Period, as shown in Figure 25. The period of each cycle is determined by the 80 µA charging current, and the 2.5 µA discharge current, and the value of the capacitor CT. When the TIMER pin reaches 0.3V during the eighth high-to-low ramp, the 20 µA current source at the GATE pin turns on Q1.
PAGE 13
LM25061 www.ti.com SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 Power Good Pin The Power Good indicator pin (PGD) is connected to the drain of an internal N-channel MOSFET capable of sustaining 17V in the off-state, and transients up to 20V. An external pull-up resistor is required at PGD to an appropriate voltage to indicate the status to downstream circuitry. The off-state voltage at the PGD pin can be higher or lower than the voltages at VIN and OUT.
PAGE 14
LM25061 SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com POWER LIMIT THRESHOLD The LM25061 determines the power dissipation in the external MOSFET (Q1) by monitoring the drain current (the current in RS), and the VDS of Q1 (SENSE to OUT pins). The resistor at the PWR pin (RPWR) sets the maximum power dissipation for Q1, and is calculated from the following equation: RPWR = 2.
PAGE 15
LM25061 www.ti.com SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 For example, if VSYS = 12V, CL = 1000 µF, and ILIM = 1A, tON calculates to 12 ms. The maximum instantaneous power dissipated in the MOSFET is 12W. This calculation assumes the time from t1 to t2 in Figure 30a is small compared to tON, and the load does not draw any current until after the output voltage has reached its final value, (Figure 28).
PAGE 16
LM25061 SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com VSYS VSYS VDS VDS Drain Current ILIM Drain Current ILIM IP 0 0 VGATE VGATE Gate- to - Source Voltage VGSL VGSL VTH VTH t ON 0 0 t3 t1 t2 a) Current Limit Only t ON 0 0 b) Power Limit and Current Limit Figure 30.
PAGE 17
LM25061 www.ti.com CT = SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 t1 x 5.5 PA = t1 x 3.2 x 10-6 1.72V (7) For example, if the desired insertion delay is 250 ms, CT calculates to 0.8 µF. At the end of the insertion delay, CT is quickly discharged by a 2 mA current sink.
PAGE 18
LM25061 SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com VPWR VIN R1 20 PA LM25061 UVLO/ EN 1.17V TIMER AND GATE LOGIC CONTROL R2 GND Figure 31. Programming the UVLO Thresholds The two resistor values are calculated as follows: • Choose the upper and lower UVLO thresholds (VUVH) and (VUVL). R1 = VUVH - VUVL VUV(HYS) = 20 PA 20 PA (11) 1.17V x R1 R2 = VUVL - 1.17V (12) As an example, assume the application requires the following thresholds: VUVH = 8V, VUVL = 7V.Therefore VUV(HYS) = 1V.
PAGE 19
LM25061 www.ti.com SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 POWER GOOD and FB PINS During turn-on, the Power Good pin (PGD) is high until the voltage at VIN increases above ≊1.6V. PGD then switches low, remaining low as the VIN voltage increases. When the voltage at the FB pin increases above its threshold PGD switches high. PGD switches low when the voltage at the FB pin is below the programmed threshold, or if the UVLO pin is taken below its threshold.
PAGE 20
LM25061 SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com If a delay is required at PGD, suggested circuits are shown in Figure 35. In Figure 35a, capacitor CPG adds delay to the rising edge, but not to the falling edge. In Figure 35b, the rising edge is delayed by RPG1 + RPG2 and CPG, while the falling edge is delayed a lesser amount by RPG2 and CPG.
PAGE 21
LM25061 www.ti.com SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 VPGD VPGD VPGD R PG1 LM25061 LM25061 LM25061 R PG2 Power Good PGD R PG1 R PG1 Power Good PGD CPG GND CPG GND Power Good C PG GND c) Short Delay at Rising Edge and Long Delay at Falling Edge or Equal Delays b) Long delay at rising edge, short delay at falling edge a) Delay Rising Edge Only PGD R PG2 Figure 35.
PAGE 22
LM25061 SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 www.ti.com RS VSYS VOUT Q1 +12V LIVE POWER SOURCE VIN SENSE OUT CL Inductive Load LM25061 GND GND PLUG-IN BOARD Figure 37.
PAGE 23
LM25061 www.ti.com SNVS611E – FEBRUARY 2011 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision D (March 2013) to Revision E • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
PAGE 24
PACKAGE OPTION ADDENDUM www.ti.
PAGE 25
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
PAGE 26
PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM25061PMM-1/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM25061PMM-2/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM25061PMME-1/NOPB VSSOP DGS 10 250 178.0 12.4 5.3 3.4 1.4 8.0 12.
PAGE 27
PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM25061PMM-1/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0 LM25061PMM-2/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0 LM25061PMME-1/NOPB VSSOP DGS 10 250 210.0 185.0 35.0 LM25061PMME-2/NOPB VSSOP DGS 10 250 210.0 185.0 35.0 LM25061PMMX-1/NOPB VSSOP DGS 10 3500 367.0 367.0 35.
PAGE 28
PAGE 29
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.