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LM25085A

PGATE

ISEN

GND

VCC

ADJ

4.5V to 42V

Input

GND

SHUTDOWN

VCC

ADJ

Cff

OUT

FB2

FB1

OUT

GND

VIN

LM25085A

www.ti.com

SNVS601B –JANUARY 2009–REVISED MARCH 2013

LM25085A 42V Constant On-Time PFET Buck Switching Controller with 0.9V Reference

Check for Samples: LM25085A

FEATURES

DESCRIPTION

The LM25085A is a functional variant of the LM25085

• Wide 4.5V to 42V Input Voltage Range

COT PFET Buck Switching Controller. The functional

• Adjustable Current Limit using R

DS(ON)

or a

differences of the LM25085A are: The feedback

Current Sense Resistor

reference voltage is 0.9V, the forced off-time after

• Programmable Switching Frequency to 1MHz

current limit detection is longer, and the soft-start time

is shorter (1.8 ms).

• No Loop Compensation Required

The LM25085A is a high efficiency PFET switching

• Ultra-Fast Transient Response

regulator controller that can be used to quickly and

• Nearly Constant Operating Frequency with

easily develop a small, efficient buck regulator for a

Line and Load Variations

wide range of applications. This high voltage

• Adjustable Output Voltage from 0.9V

controller contains a PFET gate driver and a high

voltage bias regulator which operates over a wide

• Precision ±2% Feedback Reference

4.5V to 42V input range. The constant on-time

• Capable of 100% Duty Cycle Operation

regulation principle requires no loop compensation,

• Internal Soft-Start Timer

simplifies circuit implementation, and results in ultra-

• Integrated High Voltage Bias Regulator

fast load transient response. The operating frequency

remains nearly constant with line and load variations

• Thermal Shutdown

due to the inverse relationship between the input

voltage and the on-time. The PFET architecture

PACKAGE

allows 100% duty cycle operation for a low dropout

• HVSSOP-PowerPAD-8

voltage. Either the R

DS(ON)

of the PFET or an external

sense resistor can be used to sense current for over-

• VSSOP-8

current detection.

• WSON-8 (3 mm x 3 mm)

Typical Application, Basic Step Down Controller

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (30 pages)

PAGE 1
LM25085A www.ti.com SNVS601B – JANUARY 2009 – REVISED MARCH 2013 LM25085A 42V Constant On-Time PFET Buck Switching Controller with 0.9V Reference Check for Samples: LM25085A FEATURES DESCRIPTION • • The LM25085A is a functional variant of the LM25085 COT PFET Buck Switching Controller. The functional differences of the LM25085A are: The feedback reference voltage is 0.9V, the forced off-time after current limit detection is longer, and the soft-start time is shorter (1.8 ms).
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LM25085A SNVS601B – JANUARY 2009 – REVISED MARCH 2013 www.ti.com Connection Diagram Exposed Pad on Bottom Connect to Ground ADJ 1 8 ADJ 1 8 RT 2 7 VCC FB 3 6 PGATE GND 4 5 ISEN VIN RT 2 7 VCC FB 3 6 PGATE GND 4 5 ISEN VIN Figure 1. Top View 8-Lead HVSSOP Figure 2. Top View 8-Lead VSSOP ADJ 1 8 VIN RT 2 7 VCC FB 3 6 PGATE GND 4 5 ISEN Exposed Pad on Bottom Connect to Ground Figure 3. Top View 8-Lead WSON PIN DESCRIPTIONS Pin No.
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LM25085A www.ti.com SNVS601B – JANUARY 2009 – REVISED MARCH 2013 Absolute Maximum Ratings (1) (2) VIN to GND -0.3V to 45V ISEN to GND -0.3V to VIN + 0.3V ADJ to GND -0.3V to VIN + 0.3V RT, FB to GND -0.3V to 7V VIN to VCC, VIN to PGATE -0.3V to 10V ESD Rating (3) Human Body Model 2kV Storage Temperature Range (1) (2) (3) -65°C to +150°C Absolute Maximum Ratings are limits beyond which damage to the device may occur.
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LM25085A SNVS601B – JANUARY 2009 – REVISED MARCH 2013 www.ti.com Electrical Characteristics (continued) Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
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LM25085A www.ti.com SNVS601B – JANUARY 2009 – REVISED MARCH 2013 Typical Performance Characteristics Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 24V. Efficiency (Circuit of Figure 28) Input Operating Current vs. VIN Figure 4. Figure 5. Shutdown Current vs. VIN VCC vs. VIN Figure 6. Figure 7. VCC vs. ICC On-Time vs. RT and VIN Figure 8. Figure 9.
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LM25085A SNVS601B – JANUARY 2009 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 24V. 6 Off-Time vs. VIN and VFB Voltage at the RT Pin Figure 10. Figure 11. ADJ Pin Current vs. VIN Input Operating Current vs. Temperature Figure 12. Figure 13. Shutdown Current vs. Temperature VCC vs. Temperature Figure 14. Figure 15.
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LM25085A www.ti.com SNVS601B – JANUARY 2009 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 24V. On-Time vs. Temperature Minimum On-Time vs. Temperature Figure 16. Figure 17. Off-Time vs. Temperature Current Limit Comparator Offset vs. Temperature Figure 18. Figure 19. ADJ Pin Current vs. Temperature PGATE Driver Output Resistance vs. Temperature Figure 20. Figure 21.
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LM25085A SNVS601B – JANUARY 2009 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 24V. Feedback Reference Voltage vs. Temperature Soft-Start Time vs. Temperature Figure 22. Figure 23. RT Pin Shutdown Threshold vs. Temperature Figure 24.
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LM25085A www.ti.com SNVS601B – JANUARY 2009 – REVISED MARCH 2013 Block Diagram 4.5V to 42V Input VIN GND Negative Bias Regulator VIN CIN 7.7V CBYP LM25085A + - 0.73V RT + CVCC CADJ Thermal Shutdown RT + VCC VIN RADJ VCC UVLO ON Time One-Shot Gate Driver RSEN PGATE Q1 SHUTDOWN VCC 0.9V Soft-Start Gate Driver Control Logic L1 ADJ COUT 40 PA GND + QS - R REGULATION COMPARATOR 1.
PAGE 10
LM25085A SNVS601B – JANUARY 2009 – REVISED MARCH 2013 www.ti.com FUNCTIONAL DESCRIPTION OVERVIEW The LM25085A is a PFET buck (step-down) DC-DC controller using the constant on-time (COT) control principle. The input operating voltage range of the LM25085A is 4.5V to 42V. The use of a PFET in a buck regulator greatly simplifies the gate drive requirements and allows for 100% duty cycle operation to extend the regulation range when operating at low input voltage.
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LM25085A www.ti.com SNVS601B – JANUARY 2009 – REVISED MARCH 2013 ON-TIME TIMER The on-time of the PFET gate drive output (PGATE pin) is determined by the resistor (RT) and the input voltage (VIN), and is calculated from: -7 tON = 1.45 x 10 x (RT + 1.4) (VIN - 1.56V + RT/3167) + 50 ns (3) where RT is in kΩ. The minimum on-time, which occurs at maximum VIN, should not be set less than 150 ns (see CURRENT LIMITING).
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LM25085A SNVS601B – JANUARY 2009 – REVISED MARCH 2013 www.ti.com CURRENT LIMITING The LM25085A current limiting operates by sensing the voltage across either the RDS(ON) of Q1, or a sense resistor, during the on-time and comparing it to the voltage across the resistor RADJ (see Figure 26). The current limit function is much more accurate and stable over temperature when a sense resistor is used. The RDS(ON) of a MOSFET has a wide process variation and a large temperature coefficient.
PAGE 13
LM25085A www.ti.com SNVS601B – JANUARY 2009 – REVISED MARCH 2013 The on-time in Equation 9 is shorter than the normal on-time since the PFET is shut off when the current limit threshold is crossed. If the off-time is not long enough, such that the current decrease (Equation 10) is less than the current increase (Equation 9), the current levels are higher at the start of the next on-time. This results in a further decrease in on-time, since the current limit threshold is crossed sooner.
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LM25085A SNVS601B – JANUARY 2009 – REVISED MARCH 2013 www.ti.com P-CHANNEL MOSFET SELECTION The PFET must be rated for the maximum input voltage, with some margin above that to allow for transients and ringing which can occur on the supply line and the switching node. The gate-to-source voltage (VGS) normally provided to the PFET is 7.7 volts for VIN greater than 8.5V.
PAGE 15
LM25085A www.ti.com SNVS601B – JANUARY 2009 – REVISED MARCH 2013 Applications Information EXTERNAL COMPONENTS The procedure for calculating the external components is illustrated with the following design example. Referring to Block Diagram, the circuit is to be configured for the following specifications: • VOUT = 1.0V • VIN = 4.
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LM25085A Inductor Current SNVS601B – JANUARY 2009 – REVISED MARCH 2013 www.ti.com IPK IOR IOUT SW Node 1/FS Figure 27. Inductor Current Waveform • RSEN, RADJ: To achieve good current limit accuracy and avoid over designing the power stage components, the sense resistor method is used for current limiting in this example. A standard value 10 mΩ resistor is selected for RSEN, resulting in a 50 mV drop at maximum load current, and a maximum 0.25W power dissipation in the resistor.
PAGE 17
LM25085A www.ti.com SNVS601B – JANUARY 2009 – REVISED MARCH 2013 components are determined using the following procedure: Calculate VA = VOUT - (VSW x (1 – (VOUT/VIN(min)))) where VSW is the absolute value of the voltage at the SW node during the off-time, typically 0.5V to 1V depending on the diode D1. Using a typical value of 0.65V, VA calculates to 0.49V.
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LM25085A SNVS601B – JANUARY 2009 – REVISED MARCH 2013 www.ti.com Final Design Example Circuit The final circuit is shown in Figure 28, and its performance is presented in Figure 29 through Figure 32. The measured efficiencies shown in Figure 29 are typical for a buck converter producing a low output voltage (1V). CVCC 4.5V to 24V Input LM25085A VIN VIN 0.47 PF VCC CBYP CIN 1 PF 33 PF GND CADJ 1000 pF ADJ RT 21 k: RADJ RSEN 2.05 k: 0.01: ISEN RT SHUTDOWN L1 6.
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LM25085A www.ti.com SNVS601B – JANUARY 2009 – REVISED MARCH 2013 Figure 30. Frequency vs. VIN (Circuit of Figure 28) Figure 31. Current Limit vs. VIN (Circuit of Figure 28) Figure 32.
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LM25085A SNVS601B – JANUARY 2009 – REVISED MARCH 2013 www.ti.com Alternate Output Ripple Configurations The minimum ripple configuration, using C1, C2 and R3, used in the example circuit Figure 28, results in a low ripple amplitude at VOUT determined mainly by the characteristics of the output capacitor and the ripple current in L1. This configuration allows multiple ceramic capacitors to be used for VOUT if the output voltage is provided to several places on the PC board.
PAGE 21
LM25085A www.ti.com SNVS601B – JANUARY 2009 – REVISED MARCH 2013 LM25085A L1 PGATE Q1 D1 VOUT RFB2 FB R4 COUT GND RFB1 GND Figure 34. Lowest Cost Ripple Generating Configuration PC Board Layout In most applications, the heat sink pad or tab of Q1 is connected to the switch node, i.e. the junction of Q1, L1 and D1. While it is common to extend the PC board pad from under these devices to aid in heat dissipation, the pad size should be limited to minimize EMI radiation from this switching node.
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LM25085A SNVS601B – JANUARY 2009 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision A (March 2013) to Revision B • 22 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 19-Jul-2013 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing LM25085AMM/NOPB VSSOP DGK 8 LM25085AMME/NOPB VSSOP DGK LM25085AMMX/NOPB VSSOP DGK LM25085AMY/NOPB MSOPPower PAD LM25085AMYE/NOPB SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 8 250 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 8 3500 330.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM25085AMM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LM25085AMME/NOPB VSSOP DGK 8 250 210.0 185.0 35.0 LM25085AMMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LM25085AMY/NOPB MSOP-PowerPAD DGN 8 1000 210.0 185.0 35.0 LM25085AMYE/NOPB MSOP-PowerPAD DGN 8 250 210.0 185.0 35.
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MECHANICAL DATA DGN0008A MUY08A (Rev A) BOTTOM VIEW www.ti.
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MECHANICAL DATA NGQ0008A SDA08A (Rev A) www.ti.
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