Datasheet

K =
P
OUT
P
IN
V
OUT
t
t
~7.5 Ps
V
PG
+14%
-14%
-10%
+10%
LM26420
SNVS579F –FEBRUARY 2009–REVISED MARCH 2013 www.ti.com
Figure 42. Power Good Hysterysis Operation
OVER-CURRENT PROTECTION
When the switch current reaches the current limit value, it immediately is turned off. This effectively reduces the
duty cycle and therefore the output voltage dips and continues to droop until the output load matches the peak
current limit inductor current. As the FB voltage drops below 480mV the operating frequency begins to decrease
until it hits full on frequency fold-back which is set to approximately 150kHz for the Y version and 300kHz for the
X version. Frequency fold back helps reduce the thermal stress in the IC by reducing the switching losses and to
prevent runaway of the inductor current when the output is shorted to ground.
It is important to note that when recovering from a over-current condition the converter does not go through the
soft-start process. There may be an over shoot due to the sudden removal of the over-current fault. The
reference voltage at the non-inverting input of the error amplifier always sits at 0.8V during the over-current
condition, therefore when the fault is removed the converter bring the FB voltage back to 0.8V as quickly as
possible. The over-shoot depend on whether there is a load on the output after the removal of the over-current
fault, the size of the inductor, and the amount of capacitance on the output. The smaller the inductor and the
larger the capacitance on the output the smaller the overshoot. Note, over-current protection for each output is
independent.
PCB LAYOUT CONSIDERATIONS
When planning layout there are a few things to consider when trying to achieve a clean, regulated output. The
most important consideration is the close coupling of the GND connections of the input capacitor and the PGND
pin. These ground ends should be close to one another and be connected to the GND plane with at least two
through-holes. Place these components as close to the IC as possible. Next in importance is the location of the
GND connection of the output capacitor, which should be near the GND connections of VIND and PGND. There
should be a continuous ground plane on the bottom layer of a two-layer board except under the switching node
island. The FB pin is a high impedance node and care should be taken to make the FB trace short to avoid noise
pickup and inaccurate regulation. The feedback resistors should be placed as close as possible to the IC, with
the GND of R1 placed as close as possible to the GND of the IC. The V
OUT
trace to R2 should be routed away
from the inductor and any other traces that are switching. High AC currents flow through the V
IN
, SW and V
OUT
traces, so they should be as short and wide as possible. However, making the traces wide increases radiated
noise, so the designer must make this trade-off. Radiated noise can be decreased by choosing a shielded
inductor. The remaining components should also be placed as close as possible to the IC. Please see
Application Note AN-1229 SNVA054 for further considerations and the LM26420 demo board as an example of a
four-layer layout.
Calculating Efficiency, and Junction Temperature
The complete LM26420 DC/DC converter efficiency can be calculated in the following manner.
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