Datasheet

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SS/ON1

SS/ON2

LM2642

PGOOD1

UV_Delay

OUT1

1.3V-27V

OUT2

1.3V-27V

4.5V-30V

LM2642

www.ti.com

SNVS203I –MAY 2002–REVISED APRIL 2013

LM2642 Two-Phase Synchronous Step-Down Switching Controller

Check for Samples: LM2642

FEATURES

DESCRIPTION

The LM2642 consists of two current mode

• Two Synchronous Buck Regulators

synchronous buck regulator controllers with a

• 180° Out of Phase Operation

switching frequency of 300kHz.

• 4.5V to 30V Input Range

The two switching regulator controllers operate 180°

• Power Good Function Monitors Ch.1

out of phase. This feature reduces the input ripple

• 37µA Shutdown Current

RMS current, thereby significantly reducing the

required input capacitance. The two switching

• 0.04% (typical) Line and Load Regulation Error

regulator outputs can also be paralleled to operate as

• Current Mode Control With or Without a Sense

a dual-phase single output regulator.

Resistor

The output of each channel can be independently

• Independent Enable/Soft-start Pins Allow

adjusted from 1.3 to V

• maximum duty cycle. An

Simple Sequential Startup Configuration.

internal 5V rail is also available externally for driving

• Configurable for Single Output Parallel

bootstrap circuitry.

Operation. (See Figure 3).

Current-mode feedback control assures excellent line

• Adjustable Cycle-by-Cycle Current Limit

and load regulation and a wide loop bandwidth for

• Input Under-voltage Lockout

excellent response to fast load transients. Current is

sensed across either the Vds of the top FET or

• Output Over-voltage Latch Protection

across an external current-sense resistor connected

• Output Under-voltage Protection with Delay

in series with the drain of the top FET. Current limit is

• Thermal Shutdown

independently adjustable for each channel.

• Self Discharge of Output Capacitors When the

The LM2642 features analog soft-start circuitry that is

Regulator is OFF

independent of the output load and output

capacitance. This makes the soft-start behavior more

• TSSOP package

predictable and controllable than traditional soft-start

circuits.

APPLICATIONS

A PGOOD1 pin is provided to monitor the dc output

• Embedded Computer Systems

of channel 1. Over-voltage protection is available for

• High End Gaming Systems

both outputs. A UV-Delay pin is also available to

• Set-top Boxes

allow delayed shut off time for the IC during an output

under-voltage event.

• WebPAD

BLOCK DIAGRAM

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (31 pages)

PAGE 1
LM2642 www.ti.com SNVS203I – MAY 2002 – REVISED APRIL 2013 LM2642 Two-Phase Synchronous Step-Down Switching Controller Check for Samples: LM2642 FEATURES DESCRIPTION • • • • • • • The LM2642 consists of two current mode synchronous buck regulator controllers with a switching frequency of 300kHz. 1 2 • • • • • • • • Two Synchronous Buck Regulators 180° Out of Phase Operation 4.5V to 30V Input Range Power Good Function Monitors Ch.1 37µA Shutdown Current 0.
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LM2642 SNVS203I – MAY 2002 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
PAGE 3
LM2642 www.ti.com SNVS203I – MAY 2002 – REVISED APRIL 2013 system. ON/SS1 (Pin 9) Channel 1 enable pin. This pin is internally pulled up to one diode drop above VLIN5. Pulling this pin below 1.2V (open-collector type) turns off Channel 1. If both ON/SS1 and ON/SS2 pins are pulled below 1.2V, the whole chip goes into shut down mode. Adding a capacitor to this pin provides a soft-start feature that minimizes inrush current and output voltage overshoot. ON/SS2 (Pin 10) Channel 2 enable pin.
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LM2642 SNVS203I – MAY 2002 – REVISED APRIL 2013 ABSOLUTE MAXIMUM RATINGS www.ti.com (1) Voltages from the indicated pins to SGND/PGND: VIN, ILIM1, ILIM2, KS1, KS2 −0.3V to 32V SW1, SW2, RSNS1, RSNS2 −0.3 to (VIN + 0.3)V −0.3V to 6V FB1, FB2, VDD1, VDD2 −0.3V to (VLIN5 +0.3)V PGOOD, COMP1, COMP2, UV Delay ON/SS1, ON/SS2 (2) −0.3V to (VLIN5 +0.6)V −0.3V to 7V CBOOT1 to SW1, CBOOT2 to SW2 −0.3V to (VDD+0.3)V LDRV1, LDRV2 HDRV1 to SW1, HDRV2 to SW2 −0.3V HDRV1 to CBOOT1, HDRV2 to CBOOT2 +0.
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LM2642 www.ti.com SNVS203I – MAY 2002 – REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS Unless otherwise specified, VIN = 15V, GND = PGND = 0V, VLIN5 = VDD1 = VDD2. Limits appearing in boldface type apply over the specified operating junction temperature range, (-20°C to +125°C, if not otherwise specified). Specifications appearing in plain type are measured using low duty cycle pulse testing with TA = 25°C (1), (2). Min/Max limits are specified by design, test, or statistical analysis.
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LM2642 SNVS203I – MAY 2002 – REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Unless otherwise specified, VIN = 15V, GND = PGND = 0V, VLIN5 = VDD1 = VDD2. Limits appearing in boldface type apply over the specified operating junction temperature range, (-20°C to +125°C, if not otherwise specified). Specifications appearing in plain type are measured using low duty cycle pulse testing with TA = 25°C (1), (2). Min/Max limits are specified by design, test, or statistical analysis.
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LM2642 www.ti.com SNVS203I – MAY 2002 – REVISED APRIL 2013 VIN + 6V-30V C2 10nF GND 22 ILIM1 VIN C1 1uF IC1 LM2642 KS1 RSNS1 6 UV_DELAY C34 0.1uF HDRV1 SW1 VLIN5 CBOOT1 5 PGOOD1 9 PGOOD1 LDRV1 PGND ON/SS1 FB1 C11 10nF FB2 10 C12 10nF VDD 4R7 C27 1uF VLIN5 7 3 C26 4.7uF R23 20k 12 C20 1nF R24 20k ON/SS2 ILIM2 24 19 C19 1nF R1 13k 28 C5 10uF Q1 26 27 R32 C7 25 0.1uF 4R7 FDS6690A VDD + C6 22uF Vo1 5V/3A L1 8.
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LM2642 SNVS203I – MAY 2002 – REVISED APRIL 2013 www.ti.com VIN+ 4.5V-20V C1 1uF C2 10nF C3 100pF GND VIN R1 R2 11k 100R ILIM1 R6 C4 C6 22uF C5 10uF R7 12m KS1 RSNS1 100pF 100R UV_DELAY Q1 HDRV1 C34 0.1uF VLIN5 R28 220K CBOOT1 L1 4R7 3u6H VDD LDRV1 ON/SS1 ON1/2 ON/SS2 C8 220uF + R10 9k 0.1uF C9 220uF GND D3A R11 20k D4 PGND C11 22nF S1 + C7 Q2 PGOOD1 PGOOD1 Vout 1.
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LM2642 www.ti.com SNVS203I – MAY 2002 – REVISED APRIL 2013 BLOCK DIAGRAM VIN Voltage and Current generator BG SD Disable BG reference Bias Generator Vref Current bias IREF Input Power Supply + + - 5V LDO (Allways ON) VLIN5 From another Ch.
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LM2642 SNVS203I – MAY 2002 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS Softstart Waveforms (ILOAD1 = ILOAD2 = 0A) Power On and PGOOD1 Waveforms (ILOAD1 = ILOAD2 = 0A) VOUT1 2V/div PGOOD1 5V/div VOUT2 2V/div VIN 22V/div ON/SS1=ON/SS2 2V/div VOUT1 2V/div VOUT1 2V/div VOUT2 2V/div VIN 7V/div ON/SS1=ON/SS2 1V/div VIN 10V/div 2ms/div 2ms/div Figure 4. Figure 5.
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LM2642 www.ti.com SNVS203I – MAY 2002 – REVISED APRIL 2013 Ch.2 Load Transient Response 3.3VOUT, 12VIN Load Transient Response Parallel Operation 1.8VOUT, 12VIN Figure 10. Figure 11. Input Supply Current vs Temperature (Shutdown Mode VIN = 15V) Input Supply Current vs VIN Shutdown Mode (25°C) 44 49 42 47 45 43 Iq (uA) Iq (PA) 40 38 41 36 39 34 37 35 5.5 32 -25 -5 15 35 55 75 95 115 135 10.5 15.5 20.5 25.5 30 25.5 30 VIN (V) TEMPERATURE (oC) Figure 12. Figure 13.
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LM2642 SNVS203I – MAY 2002 – REVISED APRIL 2013 www.ti.com FB Reference Voltage vs Temperature Operating Frequency vs Temperature 1.244 320 315 1.242 FREQUENCY (kHz) 310 VREF (V) 1.240 1.238 1.236 305 300 295 290 285 280 1.234 275 1.232 -40 -20 0 20 40 60 80 270 -40 -20 100 120 60 80 Error Amplifier Gain vs Temperature Efficiency vs Load Current Ch.1 = 5V, Ch.2 = Off 100 650.0 90 600.0 550.0 500.0 100 120 VIN=7V VIN=22V 80 70 VIN=12V 60 50 450.0 400.
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LM2642 www.ti.com SNVS203I – MAY 2002 – REVISED APRIL 2013 APPLICATION INFORMATION OPERATION DESCRIPTIONS SOFT START The ON/SS1 pin has dual functionality as both channel enable and soft start control. The soft start block diagram is shown in Figure 22. The LM2642 will remain in shutdown mode while both soft start pins are grounded.In a normal application (with a soft start capacitor connected between the ON/SS1 pin and SGND) soft start functions as follows.
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LM2642 SNVS203I – MAY 2002 – REVISED APRIL 2013 www.ti.com SEQUENTIAL STARTUP Sequential startup can be implemented by simply connecting PGOOD1 to SS/ON2. Once channel 1 has reached 94% of nominal, PGOOD1 will go high, thus enabling SS/ON2. In this mode of operation, channel 2 will be controlled by the state of channel 1. If channel 1 falls out of the PGOOD1 window, channel 2 will be switched off immediately. PGOOD1 OFF 1 UVPG1 UVP ½ (latched) OVP ½ (latched) FBx from other CH. 1.
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LM2642 www.ti.com SNVS203I – MAY 2002 – REVISED APRIL 2013 POWER GOOD A power good pin (PGOOD1) is available to monitor the output status of Channel 1. As shown in Figure 24, the pin connects to the output of an open drain MOSFET, which will remain open while Channel 1 is within operating range. PGOOD1 will go low (low impedance to ground) under the following four conditions: 1. Channel 1 is turned off 2. Channel 1 output falls below 90.3% of nominal (UVPG1) 3. OVP on either channel 4.
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LM2642 SNVS203I – MAY 2002 – REVISED APRIL 2013 www.ti.com CBOOTx HDRVx 0.1uF SWx 4R7 Rsw Figure 25. SW Series Resistor CURRENT SENSING AND LIMITING As shown in Figure 26, the KSx and RSNSx pins are the inputs of the current sense amplifier. Current sensing is accomplished either by sensing the Vds of the top FET or by sensing the voltage across a current sense resistor connected from VIN to the drain of the top FET.
PAGE 17
LM2642 www.ti.com SNVS203I – MAY 2002 – REVISED APRIL 2013 (2) Where Ilim is the load current at which the current limit comparator will be tripped. When sensing current across the top FET, replace Rsns with the Rdson of the FET. This calculated Rlim value specifies that the minimum current limit will not be less than Imax. It is recommended that a 1% tolerance resistor be used. When sensing across the top FET, Rdson will show more variation than a current sense resistor, largely due to temperature.
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LM2642 SNVS203I – MAY 2002 – REVISED APRIL 2013 www.ti.com Vout R2 FBx GND R1 Figure 27. Output Voltage Setting Example: Vnom=5V, Vfb=1.238V, Ifbmax=200nA. (5) Choose 60K (6) The output voltage is limited by the maximum duty cycle as well as the minimum on time. Figure 28 shows the limits for input and output voltages. The recommended maximum output voltage is approximately 1V less than the nominal input voltage. At 30V input, the minimum output is approximately 2.
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LM2642 www.ti.com SNVS203I – MAY 2002 – REVISED APRIL 2013 Where ±δ% is the output voltage regulation window and ±ε% is the output voltage initial accuracy. Example: Vnom = 5V, δ% = 7%, ε% = 3.4%, Vrip = 40mV peak to peak. (8) Since the ripple voltage is included in the calculation of ΔVc_s, the inductor ripple current should not be included in the worst-case load current excursion. That is, the worst-case load current excursion should be simply maximum load current change specification, ΔIc_s.
PAGE 20
LM2642 SNVS203I – MAY 2002 – REVISED APRIL 2013 www.ti.com (13) Lmin = 7µH The actual selection process usually involves several iterations of all of the above steps, from ripple voltage selection, to capacitor selection, to inductance calculations. Both the highest and the lowest input and output voltages and load transient requirements should be considered. If an inductance value larger than Lmin is selected, make sure that the Cmin requirement is not violated.
PAGE 21
LM2642 www.ti.com SNVS203I – MAY 2002 – REVISED APRIL 2013 (18) Where, again, I1 and I2 are the maximum load currents of channel 1 and 2, and D1 and D2 are the duty cycles. This equation should be used when both duty cycles are expected to be higher than 50%. Input capacitors must meet the minimum requirements of voltage and ripple current capacity. The size of the capacitor should then be selected based on hold up time requirements.
PAGE 22
LM2642 SNVS203I – MAY 2002 – REVISED APRIL 2013 www.ti.com (21) Example: Tj_max = 100°C, Ta_max = 60°C, Rqja = 60°C/W, Vin_min = 5.5V, Vnom = 5V, and Iload_max = 3.6A. (22) When using FETs in parallel, the same guidelines apply to the top FET as apply to the bottom FET. LOOP COMPENSATION The general purpose of loop compensation is to meet static and dynamic performance requirements while maintaining stability. Loop gain is what is usually checked to determine small-signal performance.
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LM2642 SNVS203I – MAY 2002 – REVISED APRIL 2013 GAIN (dB) www.ti.com -20 dB/ dec (fp1 is at zero frequency) -20 dB/ dec B fz1 fp2 fz2 FREQUENCY Figure 30. Output-Control Transfer Function The control-output corner frequencies, and thus the desired compensation corner frequencies, can be determined approximately by the following equations: (23) (24) Since fp is determined by the output network, it will shift with loading (Ro) and duty cycle.
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LM2642 SNVS203I – MAY 2002 – REVISED APRIL 2013 www.ti.com The value of Cc1 should be within the range determined by Fpmin/max. A higher value will generally provide a more stable loop, but too high a value will slow the transient response time. The compensation network (Figure 31) will also introduce a low frequency pole which will be close to 0Hz. A second pole should also be placed at fz. This pole can be created with a single capacitor Cc2 and a shorted Rc2 (see Figure 31).
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LM2642 www.ti.com SNVS203I – MAY 2002 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision H (April 2013) to Revision I • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM2642MTCX TSSOP PW 28 2500 330.0 16.4 6.8 10.2 1.6 8.0 16.0 Q1 LM2642MTCX/NOPB TSSOP PW 28 2500 330.0 16.4 6.8 10.2 1.6 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM2642MTCX TSSOP PW 28 2500 367.0 367.0 38.0 LM2642MTCX/NOPB TSSOP PW 28 2500 367.0 367.0 38.
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