Datasheet

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BOOT

SEN

PGND

PWGD

FREQ

SS/TRACK

SGND

EAO

PGND

= 3.3V

OUT

= 1.2V@4A

FB2

FADJ

BOOT

1,2

FB1

1,2

LM2743

PULL-UP

LM2743

www.ti.com

SNVS276G –APRIL 2004–REVISED MARCH 2013

LM2743 Low Voltage N-Channel MOSFET Synchronous Buck Regulator Controller

Check for Samples: LM2743

FEATURES

DESCRIPTION

The LM2743 is a high-speed synchronous buck

• Power Stage Input Voltage from 1V to 16V

regulator controller with an accurate feedback voltage

• Control Stage Input Voltage from 3V to 6V

accuracy of ±2%. It can provide simple down

• Output Voltage Adjustable down to 0.6V

conversion to output voltages as low as 0.6V. Though

the control sections of the IC are rated for 3 to 6V,

• Power Good Flag and Shutdown

the driver sections are designed to accept input

• Output Over-Voltage and Under-Voltage

supply rails as high as 16V. The use of adaptive non-

Detection

overlapping MOSFET gate drivers helps avoid

• ±2% Feedback Voltage Accuracy Over

potential shoot-through problems while maintaining

Temperature

high efficiency. The IC is designed for the more cost-

effective option of driving only N-channel MOSFETs

• Low-Side Adjustable Current Sensing

in both the high-side and low-side positions. It senses

• Adjustable Soft-Start

the low-side switch voltage drop for providing a

• Tracking and Sequencing with Shutdown and

simple, adjustable current limit.

Soft-Start Pins

The fixed-frequency voltage-mode PWM control

• Switching Frequency from 50 kHz to 1 MHz

architecture is adjustable from 50 kHz to 1 MHz with

one external resistor. This wide range of switching

• TSSOP-14 Package

frequency gives the power supply designer the

flexibility to make better tradeoffs between

APPLICATIONS

component size, cost and efficiency.

• 3.3V Buck Regulation

Features include soft-start, input under-voltage

• Cable Modem, DSL and ADSL

lockout (UVLO) and Power Good (based on both

• Laser Jet and Ink Jet Printers

under-voltage and over-voltage detection). In

addition, the shutdown pin of the IC can be used for

• Low Voltage Power Modules

providing startup delay, and the soft-start pin can be

• DSP, ASIC, Core and I/O

used for implementing precise tracking, for the

purpose of sequencing with respect to an external

rail.

Typical Application

Figure 1. Typical Application Circuit

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (38 pages)

PAGE 1
LM2743 www.ti.com SNVS276G – APRIL 2004 – REVISED MARCH 2013 LM2743 Low Voltage N-Channel MOSFET Synchronous Buck Regulator Controller Check for Samples: LM2743 FEATURES DESCRIPTION • • • • • The LM2743 is a high-speed synchronous buck regulator controller with an accurate feedback voltage accuracy of ±2%. It can provide simple down conversion to output voltages as low as 0.6V.
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LM2743 SNVS276G – APRIL 2004 – REVISED MARCH 2013 www.ti.com Connection Diagram 1 2 3 5 6 7 HG LG PGND SGND VCC PWGD ISEN PGND LM2743 4 BOOT SD FREQ FB SS/TRACK EAO 14 13 12 11 10 9 8 Figure 2. 14-Lead Plastic TSSOP θJA = 155°C/W Pin Descriptions BOOT (Pin 1) - Bootstrap pin. This is the supply rail for the gate drivers. When the high-side MOSFET turns on, the voltage on this pin should be at least one gate threshold above the regulator input voltage VIN to properly turn on the MOSFET.
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LM2743 www.ti.com SNVS276G – APRIL 2004 – REVISED MARCH 2013 Absolute Maximum Ratings (1) (2) VCC -0.3 to 7V BOOT Voltage -0.3 to 21V ISEN -0.3 to 9.5V All other pins -0.3 to VCC + 0.3V Junction Temperature 150°C Storage Temperature −65°C to 150°C Soldering Information Lead Temperature (soldering, 10sec) 260°C Infrared or Convection (20sec) 235°C ESD Rating (3) (1) (2) (3) 2 kV Absolute maximum ratings indicate limits beyond which damage to the device may occur.
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LM2743 SNVS276G – APRIL 2004 – REVISED MARCH 2013 www.ti.com Electrical Characteristics(1) (continued) VCC = 3.3V unless otherwise indicated. Typicals and limits appearing in plain type apply for TA= TJ= 25°C. Limits appearing in boldface type apply over full Operating Temperature Range. Datasheet min/max specification limits are specified by design, test, or statistical analysis.
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LM2743 www.ti.com SNVS276G – APRIL 2004 – REVISED MARCH 2013 Typical Performance Characteristics Efficiency (VOUT = 1.2V) VCC = 3.3V, fSW = 300 kHz Efficiency (VOUT = 2.5V) VCC = 3.3V, fSW = 300 kHz 100 100 VIN = 3.3V 90 90 70 80 EFFICIENCY (%) EFFICIENCY (%) 80 VIN = 12V VIN = 5V 60 50 70 VIN = 3.3V 60 VIN = 5V 50 40 40 30 30 20 VIN = 12V 20 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 OUTPUT CURRENT (A) OUTPUT CURRENT (A) Figure 3.
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LM2743 SNVS276G – APRIL 2004 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) BOOT Pin Current vs Temperature for BOOT Voltage = 12V fSW = 300 kHz, FDS6898A FET, No-Load Internal Reference Voltage vs Temperature 24.9 0.2 0.1 24.7 INTERNAL REFERENCE VOLTAGE ('%) BOOT PIN CURRENT (mA) 24.8 24.6 24.5 24.4 24.3 24.2 24.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 24 23.9 -40 -25 -10 5 20 35 50 65 80 95 110125 -0.
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LM2743 www.ti.com SNVS276G – APRIL 2004 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Start-Up (No-Load) VCC = 3.3V, VIN = 5V, VOUT = 1.2V CSS = 12nF, fSW = 300 kHz Start-Up (Full-Load) VCC = 3.3V, VIN = 5V, VOUT = 1.2V IOUT = 4A, CSS = 12nF, fSW = 300 kHz Figure 15. Figure 16. Shutdown (Full-Load) VCC = 3.3V, VIN = 5V, VOUT = 1.2V IOUT = 4A, CSS = 12nF, fSW = 300 kHz Load Transient Response (IOUT = 0A to 4A) VCC = 3.3V, VIN = 5V, VOUT = 1.
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LM2743 SNVS276G – APRIL 2004 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Line Transient Response (VIN = 3V to 9V) VCC = 3.3V, VOUT = 1.2V IOUT = 2A, fSW = 300 kHz Line Transient Response (VIN = 9V to 3V) VCC = 3.3V, VOUT = 1.2V IOUT = 2A, fSW = 300 kHz 100mV/div 100 mV/div VOUT VOUT 5V/div VIN 5V/div VIN 8 100 Ps/DIV 100 Ps/DIV Figure 21. Figure 22.
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LM2743 www.ti.com SNVS276G – APRIL 2004 – REVISED MARCH 2013 Block Diagram VCC SD FREQ CLOCK & RAMP PGND PGND SGND UVLO SHUT DOWN LOGIC BOOT 10 Ps DELAY HG SSDONE PWGD SYNCHRONOUS DRIVER LOGIC OV UV 0.71V LG 0.434V 10 PA SS/TRACK 1VPP PWM LOGIC PWM Soft-Start Comparator + Logic REF 40 PA - + 90 PA ISEN ILIM EA - + VREF = 0.
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LM2743 SNVS276G – APRIL 2004 – REVISED MARCH 2013 www.ti.com APPLICATION INFORMATION THEORY OF OPERATION The LM2743 is a voltage-mode, high-speed synchronous buck regulator with a PWM control scheme. It is designed for use in set-top boxes, thin clients, DSL/Cable modems, and other applications that require high efficiency buck converters. It has output shutdown (SD), input under-voltage lock-out (UVLO) mode and power good (PWGD) flag (based on over-voltage and under-voltage detection).
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LM2743 www.ti.com SNVS276G – APRIL 2004 – REVISED MARCH 2013 Master Power Supply VOUT1 = 5V RT2 1 k: VOUT2 = 1.8V SS/TRACK VSS = 0.65V RT1 150: LM2743 FB RFB2 10 k: VFB RFB1 5 k: Figure 23. Tracking Circuit One way to use the tracking feature is to design the tracking resistor divider so that the master supply’s output voltage (VOUT1) and the LM2743’s output voltage (represented symbolically in Figure 23 as VOUT2, i.e.
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LM2743 SNVS276G – APRIL 2004 – REVISED MARCH 2013 www.ti.com For the example case of VOUT1 = 5V and VOUT2 = 1.8V, with RT1 set to 150Ω as before, RT2 is calculated from the above equation to be 265Ω. A timing diagram for the case of equal slew rates is shown in Figure 25. 5V 1.8V VOUT1 1.8V VOUT2 Figure 25.
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LM2743 www.ti.com SNVS276G – APRIL 2004 – REVISED MARCH 2013 For example, if the master supply output voltage slew rate was 1V/ms and the desired delay time between the startup of the master supply and LM2743 output voltage was 5ms, then the desired SD pin slew rate would be (1.08V/5 ms) = 0.216V/ms. Due to the internal impedance of the SD pin, the maximum recommended value for RS2 is 1kΩ. To achieve the desired slew rate, RS1 would then be 274Ω. A timing diagram for this example is shown in Figure 27.
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LM2743 SNVS276G – APRIL 2004 – REVISED MARCH 2013 www.ti.com MOSFET GATE DRIVERS The LM2743 has two gate drivers designed for driving N-channel MOSFETs in a synchronous mode. Note that unlike most other synchronous controllers, the bootstrap capacitor of the LM2743 provides power not only to the driver of the upper MOSFET, but the lower MOSFET driver too (both drivers are ground referenced, i.e. no floating driver).
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LM2743 www.ti.com SNVS276G – APRIL 2004 – REVISED MARCH 2013 LM2743 VCC 5V LM78L05 D1 BOOT CBOOT VIN + HG VO LG + Figure 30. LM78L05 Feeding Basic Charge Pump Figure 31 shows a second possibility for bootstrapping the MOSFET drives using a doubler. This circuit provides an equal voltage drive of VCC - 3VD + VIN to both the high-side and low-side MOSFET drives. This method should only be used in circuits that use 3.3V for both VCC and VIN. Even with VIN = VCC = 3.0V (10% lower tolerance on 3.
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LM2743 SNVS276G – APRIL 2004 – REVISED MARCH 2013 www.ti.com The Power Good signal is an OR-gated flag which takes into account both output over-voltage and under-voltage conditions. If the feedback pin (FB) voltage is 18% above its nominal value (118% x VFB = 0.708V) or falls 28% below that value (72 %x VFB = 0.42V) the Power Good flag goes low.
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LM2743 www.ti.com SNVS276G – APRIL 2004 – REVISED MARCH 2013 Normal Operation Current Limit ILIM IL D Figure 32. Current Limit Threshold Unlike a high-side MOSFET current sensing scheme, which limits the peaks of inductor current, low-side current sensing is only allowed to limit the current during the converter off-time, when inductor current is falling. Therefore in a typical current limit plot the valleys are normally well defined, but the peaks are variable, according to the duty cycle.
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LM2743 SNVS276G – APRIL 2004 – REVISED MARCH 2013 www.ti.com VOUT 40 PA RCLF RCS - SW ILIM ISEN + Figure 33. Foldback Current Limit Circuit Obtain the RCS with the following equation: PLIM x RDS(ON) = RCS ISEN where ISEN = 40 μA. If the switch node goes above 9.5V the following criterion must be satisfied: VIN ± 9.5V RCS t 10 mA The equation for calculating the foldback resistance value is: RCS x VOUT RCLF = (ILIM x RDS(ON)) ± (ISEN x RCS) SHUTDOWN If the shutdown pin is pulled low, (below 0.
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LM2743 www.ti.com SNVS276G – APRIL 2004 – REVISED MARCH 2013 To calculate the maximum duty cycle use the estimated 'hot' RDS(on) value of the MOSFETs, the minimum input voltage, and maximum load. As shown in Figure 34, the worst case maximum duty cycles of the LM2743 occurs at 125°C junction temperature vs VCC (IC control section voltage).
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LM2743 SNVS276G – APRIL 2004 – REVISED MARCH 2013 www.ti.com Here we have plugged in the values for output current ripple, input voltage, output voltage, switching frequency, and assumed a 40% peak-to-peak output current ripple. This yields an inductance of 1.6 µH. The output inductor must be rated to handle the peak current (also equal to the peak switch current), which is (IOUT + (0.5 x ΔIOUT)) = 4.8A, for a 4A design. The Coilcraft DO3316P-222P is 2.2 µH, is rated to 7.
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LM2743 www.ti.com SNVS276G – APRIL 2004 – REVISED MARCH 2013 where ‘n’ is the number of MOSFETs (if multiple devices have been placed in parallel), VDD is the driving voltage (see MOSFET GATE DRIVERS section) and QGS is the gate charge of the MOSFET. If different types of MOSFETs are used, the ‘n’ term can be ignored and their gate charges simply summed to form a cumulative QG.
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LM2743 SNVS276G – APRIL 2004 – REVISED MARCH 2013 www.ti.com L RL + C O VIN RO + - RC + VRAMP RC2 CC2 RC1 10 k: CC3 CC1 + 10 k: + - VREF Figure 35. Power Stage and Error Amp One popular method for selecting the compensation components is to create Bode plots of gain and phase for the power stage and error amplifier. Combined, they make the overall bandwidth and phase margin of the regulator easy to see.
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LM2743 www.ti.com SNVS276G – APRIL 2004 – REVISED MARCH 2013 20 GAIN (dB) 4 -12 -28 -44 -60 100 1k 10k 100k 1M FREQUENCY (Hz) 0 PHASE (o) -30 -60 -90 -120 -150 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 36. Power Stage Gain and Phase The double pole at 4.5 kHz causes the phase to drop to approximately -130° at around 10 kHz. The ESR zero, at 20.3 kHz, provides a +90° boost that prevents the phase from dropping to -180º.
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LM2743 SNVS276G – APRIL 2004 – REVISED MARCH 2013 1. 2. 3. 4. www.ti.com Increase AEA Check overall bandwidth and phase margin Change VIN to minimum and recheck overall bandwidth and phase margin Change IO to maximum and recheck overall bandwidth and phase margin The process ends when the both bandwidth and the phase margin are sufficiently high. For this example input voltage can vary from 3.0 to 3.
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LM2743 www.ti.com CC2 = CC3 = RC1 = RC2 = SNVS276G – APRIL 2004 – REVISED MARCH 2013 1 AEA x 10,000 1 2S x 10,000 - CC1 = 882 pF x 1 2S x CC2 x fZ1 1 2S x CC3 x fP1 1 1 = 2.73 nF fZ2 fP1 = 39.8 k: = 2.
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LM2743 SNVS276G – APRIL 2004 – REVISED MARCH 2013 www.ti.com The bandwidth and phase margin can be read graphically from Bode plots of HEA are shown in Figure 38. 60 GAIN (dB) 40 20 0 -20 -40 100 1k 10k 100k 1M FREQUENCY (Hz) -60 PHASE (o) -84 -108 -132 -156 -180 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 38. Overall Loop Gain and Phase The bandwidth of this example circuit is 59 kHz, with a phase margin of 60°. EFFICIENCY CALCULATIONS The following is a sample calculation.
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LM2743 www.ti.com SNVS276G – APRIL 2004 – REVISED MARCH 2013 The FDS6898A has a typical turn-on rise time tr and turn-off fall time tf of 15 ns and 16 ns, respectively. The switching losses for this type of dual N-Channel MOSFETs are 0.061W. FET Conduction Loss (PCND) PCND = PCND1 + PCND2 PCND1 = (IOUT)2 x RDS(ON) x k x D PCND2 = (IOUT)2 x RDS(ON) x k x (1-D) RDS(ON) = 13 mΩ and the factor is a constant value (k = 1.3) to account for the increasing RDS(ON) of a FET due to heating.
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LM2743 SNVS276G – APRIL 2004 – REVISED MARCH 2013 www.ti.com Total System Efficiency PTOTAL = PFET + PIC + PGATE + PCAP + PIND POUT K= K= x 100% POUT + PTOTAL 4.8W = 89% 4.8W + 0.6W Example Circuits VCC = VIN= 3.3V D1 RCC CBOOT RPULL-UP VCC HG SD CCC BOOT LM2743 FREQ CSS RCS VOUT = 1.8V@2A L1 ISEN PWGD RFADJ + CIN1,2 Q1 LG SS/TRACK PGND SGND PGND EAO FB RFB2 RC2 CC3 + CO1,2 RFB1 CC1 CC2 RC1 Figure 39. 3.3V to 1.8V @ 2A, fSW = 300kHz Table 1.
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LM2743 www.ti.com SNVS276G – APRIL 2004 – REVISED MARCH 2013 Table 1. Bill of Materials (continued) PART PART NUMBER TYPE PACKAGE DESCRIPTION VENDOR RCC CRCW080510R0F Resistor 805 10.0Ω 1% Vishay RC1 CRCW08055492F Resistor 805 54.9kΩ 1% Vishay RPULL-UP CRCW08051003J Resistor 805 100kΩ 5% Vishay VCC = 5V D1 RCC CBOOT RPULL-UP HG SD BOOT PWGD RFADJ CSS + CIN1,2 Q1 VCC CCC VIN = 5V LM2743 RCS L1 VOUT = 2.
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LM2743 SNVS276G – APRIL 2004 – REVISED MARCH 2013 www.ti.com VCC = 5V D1 RCC CBOOT RPULL-UP HG SD BOOT PWGD RFADJ CSS + CIN1,2 Q1 VCC CCC VIN = 12V RCS L1 VOUT = 3.3V@4A ISEN LM2743 FREQ LG SS/TRACK PGND SGND PGND EAO FB RFB2 RC2 CC3 + CO1,2 RFB1 CC1 CC2 RC1 Figure 41. 12V to 3.3V @ 4A, fSW = 300kHz Table 3.
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LM2743 www.ti.com SNVS276G – APRIL 2004 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision F (March 2013) to Revision G • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 21-Feb-2014 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 15-Apr-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM2743MTCX TSSOP PW 14 2500 330.0 12.4 6.95 8.3 1.6 8.0 12.0 Q1 LM2743MTCX/NOPB TSSOP PW 14 2500 330.0 12.4 6.95 8.3 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 15-Apr-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM2743MTCX TSSOP PW 14 2500 367.0 367.0 35.0 LM2743MTCX/NOPB TSSOP PW 14 2500 367.0 367.0 35.
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