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LM3485

www.ti.com

SNVS178G –JANUARY 2002–REVISED FEBRUARY 2013

Hysteretic PFET Buck Controller

Check for Samples: LM3485

FEATURES

DESCRIPTION

The LM3485 is a high efficiency PFET switching

• Easy to Use Control Methodology

regulator controller that can be used to quickly and

• No Control Loop Compensation Required

easily develop a small, low cost, switching buck

• 4.5V to 35V Wide Input Range

regulator for a wide range of applications. The

hysteretic control architecture provides for simple

• 1.242V to V

Adjustable Output Range

design without any control loop stability concerns

• High Efficiency 93%

using a wide variety of external components. The

• ±1.3% (±2% Over Temp) Internal Reference

PFET architecture also allows for low component

count as well as ultra-low dropout, 100% duty cycle

• 100% Duty Cycle

operation. Another benefit is high efficiency operation

• Maximum Operating Frequency > 1MHz

at light loads without an increase in output ripple.

• Current Limit Protection

Current limit protection is provided by measuring the

• VSSOP-8

voltage across the PFET’s R

DS(ON)

, thus eliminating

the need for a sense resistor. The cycle-by-cycle

APPLICATIONS

current limit can be adjusted with a single resistor,

ensuring safe operation over a range of output

• Set-Top Box

currents.

• DSL or Cable Modem

• PC/IA

• Auto PC

• TFT Monitor

• Battery Powered Portable Applications

• Distributed Power Systems

• Always On Power

Typical Application Circuit

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (23 pages)

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LM3485 www.ti.com SNVS178G – JANUARY 2002 – REVISED FEBRUARY 2013 Hysteretic PFET Buck Controller Check for Samples: LM3485 FEATURES DESCRIPTION • • • • • • • • • • The LM3485 is a high efficiency PFET switching regulator controller that can be used to quickly and easily develop a small, low cost, switching buck regulator for a wide range of applications.
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LM3485 SNVS178G – JANUARY 2002 – REVISED FEBRUARY 2013 www.ti.com Connection Diagram Figure 1. Top View 8-Lead Plastic VSSOP-8 Package Number DGK (S-PDSO-G8) PIN DESCRIPTIONS Pin Name Pin No. Description ISENSE 1 The current sense input pin. This pin should be connected to Drain node of the external PFET. GND 2 Signal ground. NC 3 No connection. FB 4 The feedback input. Connect the FB to a resistor voltage divider between the output and GND for an adjustable output voltage.
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LM3485 www.ti.com SNVS178G – JANUARY 2002 – REVISED FEBRUARY 2013 Electrical Characteristics Specifications in Standard type face are for TJ = 25°C, and in bold type face apply over the full Operating Temperature Range (TJ = −40°C to +125°C). Unless otherwise specified, VIN = 12V, VISNS = VIN − 1V, and VADJ = VIN − 1.1V. Datasheet min/max specification limits are specified by design, test, or statistical analysis.
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LM3485 SNVS178G – JANUARY 2002 – REVISED FEBRUARY 2013 www.ti.com Typical Performance Characteristics Unless otherwise specified, TJ = 25°C Quiescent Current vs Input Voltage (FB = 1.5V) Feedback Voltage vs Temperature 1.255 350 1.250 Tj = -40qC FB VOLTAGE (V) QUIESCENT CURRENT (PA) 400 300 Tj = 125qC 250 Tj = 25qC 200 150 VIN=35V 1.245 VIN=12V 1.240 VIN=4.5V 1.235 1.230 100 4 20 12 28 1.
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LM3485 www.ti.com SNVS178G – JANUARY 2002 – REVISED FEBRUARY 2013 Typical Performance Characteristics (continued) Unless otherwise specified, TJ = 25°C Typical VPGATE vs Time VIN = 9V 10 6.0 8 5.5 TJ =125qC 5.0 TJ = 25qC 4.5 TJ = -40qC CPGATE = 1800 pF 6 VPGATE (V) INPUT VOLTAGE - PGATE VOLTAGE (V) PGATE Voltage vs Input Voltage CPGATE = 1020 pF 4 CPGATE = 540 pF 4.0 CPGATE = 110 pF 2 3.5 0 3.0 12 28 20 INPUT VOLTAGE (V) 4 0 36 150 Operating ON Time vs Output Load Current (VIN = 4.
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LM3485 SNVS178G – JANUARY 2002 – REVISED FEBRUARY 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified, TJ = 25°C Efficiency vs Load Current (VOUT = 3.3V, L = 22µH) 100 Efficiency vs Load Current (VOUT = 5.0V, L = 22µH) 100 VIN = 4.
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LM3485 www.ti.com SNVS178G – JANUARY 2002 – REVISED FEBRUARY 2013 Typical Performance Characteristics (continued) Unless otherwise specified, TJ = 25°C Output Ripple Voltage vs Input Voltage (VOUT = 3.3V, IOUT = 1A, COUT(ESR) = 80mΩ, Cff = 100pF) Operating Frequency vs Output Load Current (L = 22µH, COUT(ESR) = 45mΩ, Cff = 100pF) 400 OPERATING FREQUENCY (kHz) OUTPUT RIPPLE VOLTAGE (mV) 80 L=10PH 60 L=15PH 40 L=22PH 20 0 12VIN / 3.3VOUT 300 12VIN / 5.0VOUT 200 12VIN / 1.242VOUT 4.5VIN / 1.
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LM3485 SNVS178G – JANUARY 2002 – REVISED FEBRUARY 2013 www.ti.com BLOCK DIAGRAM FUNCTIONAL DESCRIPTION OVERVIEW The LM3485 is buck (step-down) DC-DC controller that uses a hysteretic control scheme. The comparator is designed with approximately 10mV of hysteresis. In response to the voltage at the FB pin, the gate drive (PGATE pin) turns the external PFET on or off. When the inductor current is too high, the current limit protection circuit engages and turns the PFET off for approximately 9µs.
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LM3485 www.ti.com SNVS178G – JANUARY 2002 – REVISED FEBRUARY 2013 The LM3485 operates in discontinuous conduction mode at light load current or continuous conduction mode at heavy load current. In discontinuous conduction mode, current through the inductor starts at zero and ramps up to the peak, then ramps down to zero. Next cycle starts when the FB voltage reaches the internal voltage. Until then, the inductor current remains zero. Operating frequency is lower and switching losses reduce.
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LM3485 SNVS178G – JANUARY 2002 – REVISED FEBRUARY 2013 www.ti.com 140 L=22PH PROPOGATION DELAY (ns) 120 L=10PH 100 80 L=4.7PH 60 40 20 0 0 5 10 15 20 25 30 35 INPUT VOLTAGE - OUTPUT VOLTAGE (V) Figure 3. Propagation Delay The operating frequency and output ripple voltage can also be significantly influenced by the speed up capacitor (Cff). Cff is connected in parallel with the high side feedback resistor, R1.
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LM3485 www.ti.com SNVS178G – JANUARY 2002 – REVISED FEBRUARY 2013 Figure 4. Current Sensing by VDS The current limit is activated when the voltage at the ADJ pin exceeds the voltage at the ISENSE pin. The ISENSE comparator triggers the 9µs one shot pulse generator forcing the driver to turn the PFET off. The driver turns the PFET back on after 9µs. If the current has not reduced below the set threshold, the cycle will repeat continuously. A filter capacitor, CADJ, should be placed as shown in Figure 4.
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LM3485 SNVS178G – JANUARY 2002 – REVISED FEBRUARY 2013 www.ti.com One problem with selecting a higher current limit is inrush current during start-up. Increasing the capacitance (CADJ) in parallel with RADJ results in soft-start. CADJ and RADJ create an RC time constant forcing current limit to activate at a lower current. The output voltage will ramp more slowly when using the soft-start functionality.
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LM3485 www.ti.com SNVS178G – JANUARY 2002 – REVISED FEBRUARY 2013 Δi ≤ Iout * 0.386827 * Iout−0.366726 for Iout > 2.0Amps Δi ≤ Iout * 0.3 The inductance can be calculated based upon the desired operating frequency where: VIN - VDS - VOUT D L= x f 'i (7) And VOUT + VD D= VIN - VDS + VD (8) where D is the duty cycle, VD is the diode forward voltage, and VDS is the voltage drop across the PFET. The inductor should be rated to the following: Ipk = (Iout+Δi/2)*1.
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LM3485 SNVS178G – JANUARY 2002 – REVISED FEBRUARY 2013 www.ti.com PROGRAMMING THE CURRENT LIMIT (RADJ) The current limit is determined by connecting a resistor (RADJ) between input voltage and the ADJ pin. RADJ = IIND_PEAK * RDSON/ICL_ADJ (13) where: RDSON : Drain-Source ON resistance of the external PFET ICL_ADJ : 3.0µA minimum IIND_PEAK = ILOAD + IRIPPLE/2 Using the minimum value for ICL_ADJ (3.0µA) ensures that the current limit threshold will be set higher than the peak inductor current.
PAGE 15
LM3485 www.ti.com SNVS178G – JANUARY 2002 – REVISED FEBRUARY 2013 The RDSON is used in determining the current limit resistor value, RADJ. Note that the RDSON has a positive temperature coefficient. At 100°C, the RDSON may be as much as 150% higher than the 25°C value. This increase in RDSON must be considered it when determining RADJ in wide temperature range applications. If the current limit is set based upon 25°C ratings, then false current limiting can occur at high temperature.
PAGE 16
LM3485 SNVS178G – JANUARY 2002 – REVISED FEBRUARY 2013 www.ti.com Figure 8. Top Layer, Typical PCB Layout (3.3V Output) Figure 9. Bottom Layer, Typical PCB Layout (3.3V Output) Figure 10. Silk Screen, Typical PCB Layout (3.3V Output) C1: CIN 22µF/35V EEJL1VD226R (Panasonic) C2: COUT 100µF/6.
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LM3485 www.ti.com SNVS178G – JANUARY 2002 – REVISED FEBRUARY 2013 REVISION HISTORY Changes from Revision F (February 2013) to Revision G • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM3485MM VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM3485MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM3485MMX VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM3485MM VSSOP DGK 8 1000 210.0 185.0 35.0 LM3485MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LM3485MMX VSSOP DGK 8 3500 367.0 367.0 35.0 LM3485MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0 LM3485Q1MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0 LM3485Q1MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.
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