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LM2524D, LM3524D

www.ti.com

SNVS766E –JUNE 2009–REVISED MAY 2013

LM2524D/LM3524D Regulating Pulse Width Modulator

Check for Samples: LM2524D, LM3524D

The LM3524D has a ±1% precision 5V reference.

FEATURES

The current carrying capability of the output drive

• Fully Interchangeable With Standard LM3524

transistors has been raised to 200 mA while reducing

Family

CEsat

and increasing V

breakdown to 60V. The

• ±1% Precision 5V Reference With Thermal

common mode voltage range of the error-amp has

been raised to 5.5V to eliminate the need for a

Shut-Down

resistive divider from the 5V reference.

• Output Current to 200 mA DC

In the LM3524D the circuit bias line has been isolated

• 60V Output Capability

from the shut-down pin. This prevents the oscillator

• Wide Common Mode Input Range for Error-

pulse amplitude and frequency from being disturbed

Amp

by shut-down. Also at high frequencies (≃300 kHz)

• One Pulse per Period (Noise Suppression)

the max. duty cycle per output has been improved to

44% compared to 35% max. duty cycle in other

• Improved Max. Duty Cycle at High Frequencies

3524s.

• Double Pulse Suppression

In addition, the LM3524D can now be synchronized

• Synchronize Through Pin 3

externally, through pin 3. Also a latch has been

added to insure one pulse per period even in noisy

DESCRIPTION

environments. The LM3524D includes double pulse

The LM3524D family is an improved version of the

suppression logic that insures when a shut-down

industry standard LM3524. It has improved

condition is removed the state of the T-flip-flop will

specifications and additional features yet is pin for pin

change only after the first clock pulse has arrived.

compatible with existing 3524 families. New features

This feature prevents the same output from being

reduce the need for additional external circuitry often

pulsed twice in a row, thus reducing the possibility of

required in the original version.

core saturation in push-pull designs.

Connection Diagram

Figure 1. Top View

See Package Number NFG

See Package Number D

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (27 pages)

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LM2524D, LM3524D www.ti.com SNVS766E – JUNE 2009 – REVISED MAY 2013 LM2524D/LM3524D Regulating Pulse Width Modulator Check for Samples: LM2524D, LM3524D FEATURES 1 • 2 • • • • • • • • Fully Interchangeable With Standard LM3524 Family ±1% Precision 5V Reference With Thermal Shut-Down Output Current to 200 mA DC 60V Output Capability Wide Common Mode Input Range for ErrorAmp One Pulse per Period (Noise Suppression) Improved Max.
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LM2524D, LM3524D SNVS766E – JUNE 2009 – REVISED MAY 2013 www.ti.
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LM2524D, LM3524D www.ti.com SNVS766E – JUNE 2009 – REVISED MAY 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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LM2524D, LM3524D SNVS766E – JUNE 2009 – REVISED MAY 2013 www.ti.com Electrical Characteristics(1) (continued) Symbol Parameter Conditions ΔfOSC Freq. Change with VIN VIN = 8 to 40V ΔfOSC Freq. Change with Temp. TA = −55°C to +125°C at 20 kHz RT = 5.6k, CT = 0.01 μF VOSC Output Amplitude (Pin 3) RT = 5.6k, CT = 0.01 μF tPW LM2524D Typ Tested Limit (2) 0.5 1 LM3524D Design Limit (3) 5 Tested Limit (2) 0.5 1.0 Design Limit (3) 2.4 Output Pulse Width (Pin 3) RT = 5.6k, CT = 0.01 μF 0.
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LM2524D, LM3524D www.ti.com SNVS766E – JUNE 2009 – REVISED MAY 2013 Electrical Characteristics(1) (continued) Symbol Parameter Conditions LM2524D Typ Tested Limit (2) 1 0.5 LM3524D Design Limit (3) Design Limit (3) Units Typ Tested Limit (2) 1 0.5 VMin 1.5 VMax SHUT DOWN SECTION VSD High Input Voltage V(Pin 2) − V(Pin 1) ≥ 150 mV 1.
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LM2524D, LM3524D SNVS766E – JUNE 2009 – REVISED MAY 2013 www.ti.com Typical Performance Characteristics 6 Switching Transistor Peak Output Current vs Temperature Maximum Average Power Dissipation (NFG, D Packages) Figure 2. Figure 3. Maximum & Minimum Duty Cycle Threshold Voltage Output Transistor Saturation Voltage Figure 4. Figure 5. Output Transistor Emitter Voltage Reference Transistor Peak Output Current Figure 6. Figure 7.
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LM2524D, LM3524D www.ti.com SNVS766E – JUNE 2009 – REVISED MAY 2013 Typical Performance Characteristics (continued) Standby Current vs Voltage Standby Current vs Temperature Figure 8. Figure 9. Current Limit Sense Voltage Figure 10.
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LM2524D, LM3524D SNVS766E – JUNE 2009 – REVISED MAY 2013 www.ti.
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LM2524D, LM3524D www.ti.com SNVS766E – JUNE 2009 – REVISED MAY 2013 Functional Description Internal Voltage Regulator The LM3524D has an on-chip 5V, 50 mA, short circuit protected voltage regulator. This voltage regulator provides a supply for all internal circuitry of the device and can be used as an external reference. For input voltages of less than 8V the 5V output should be shorted to pin 15, VIN, which disables the 5V regulator.
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LM2524D, LM3524D SNVS766E – JUNE 2009 – REVISED MAY 2013 www.ti.com Figure 13. Error Amplifier The error amplifier is a differential input, transconductance amplifier. Its gain, nominally 86 dB, is set by either feedback or output loading. This output loading can be done with either purely resistive or a combination of resistive and reactive components. A graph of the amplifier's gain vs output load resistance is shown in Figure 14. Figure 14.
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LM2524D, LM3524D www.ti.com SNVS766E – JUNE 2009 – REVISED MAY 2013 Figure 15. The amplifier's inputs have a common-mode input range of 1.5V–5.5V. The on board regulator is useful for biasing the inputs to within this range. Current Limiting The function of the current limit amplifier is to override the error amplifier's output and take control of the pulse width. The output duty cycle drops to about 25% when a current limit sense voltage of 200 mV is applied between the +CL and −CLsense terminals.
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LM2524D, LM3524D SNVS766E – JUNE 2009 – REVISED MAY 2013 www.ti.com Typical Applications Figure 17. Positive Regulator, Step-Up Basic Configuration (IIN(MAX) = 80 mA) (1) Figure 18.
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LM2524D, LM3524D www.ti.com SNVS766E – JUNE 2009 – REVISED MAY 2013 Figure 19. Positive Regulator, Step-Down Basic Configuration (IIN(MAX) = 80 mA) (2) Figure 20.
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LM2524D, LM3524D SNVS766E – JUNE 2009 – REVISED MAY 2013 www.ti.com Figure 21. Boosted Current Polarity Inverter (3) Basic Switching Regulator Theory and Applications The basic circuit of a step-down switching regulator circuit is shown in Figure 22, along with a practical circuit design using the LM3524D in Figure 25. Figure 22. Basic Step-Down Switching Regulator The circuit works as follows: Q1 is used as a switch, which has ON and OFF times controlled by the pulse width modulator.
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LM2524D, LM3524D www.ti.com SNVS766E – JUNE 2009 – REVISED MAY 2013 Figure 23. Relation of Switch Timing to Inductor Current in Step-Down Regulator (4) Neglecting VSAT, VD, and settling ΔIL+ = ΔIL−; (5) where T = Total Period The above shows the relation between VIN, Vo and duty cycle. (6) as Q1 only conducts during tON. (7) The efficiency, η, of the circuit is: (8) ηMAX will be further decreased due to switching losses in Q1.
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LM2524D, LM3524D SNVS766E – JUNE 2009 – REVISED MAY 2013 www.ti.com (10) where: L1 is in Henrys f is switching frequency in Hz Also, see LM1578 data sheet for graphical methods of inductor selection. Calculating Output Filter Capacitor Co Figure 23 shows L1's current with respect to Q1's tON and tOFF times (VA is at the collector of Q1). This curent must flow to the load and Co. Co's current will then be the difference between IL, and Io.
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LM2524D, LM3524D www.ti.com SNVS766E – JUNE 2009 – REVISED MAY 2013 Resistor R3 sets the current limit to: (15) Figure 26 and Figure 27 show a PC board layout and stuffing diagram for the 5V, 1A regulator of Figure 25. The regulator's performance is listed in Table 1. *Mounted to Staver Heatsink No. V5-1. Q1 = BD344 Q2 = 2N5023 L1 = >40 turns No. 22 wire on Ferroxcube No. K300502 Torroid core. Figure 25. 5V, 1 Amp Step-Down Switching Regulator Table 1.
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LM2524D, LM3524D SNVS766E – JUNE 2009 – REVISED MAY 2013 www.ti.com Figure 26. 5V, 1 Amp Switching Regulator, Foil Side Figure 27. Stuffing Diagram, Component Side The Step-Up Switching Regulator Figure 28 shows the basic circuit for a step-up switching regulator. In this circuit Q1 is used as a switch to alternately apply VIN across inductor L1. During the time, tON, Q1 is ON and energy is drawn from VIN and stored in L1; D1 is reverse biased and Io is supplied from the charge stored in Co.
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LM2524D, LM3524D www.ti.com SNVS766E – JUNE 2009 – REVISED MAY 2013 Figure 28. Basic Step-Up Switching Regulator Figure 29. Relation of Switch Timing to Inductor Current in Step-Up Regulator (16) Since ΔIL+ = ΔIL−, VINtON = VotOFF − VINtOFF, and neglecting VSAT and VD1 (17) The above equation shows the relationship between VIN, Vo and duty cycle.
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LM2524D, LM3524D SNVS766E – JUNE 2009 – REVISED MAY 2013 www.ti.com So far it is assumed η = 100%, where the actual efficiency or ηMAX will be somewhat less due to the saturation voltage of Q1 and forward on voltage of D1. The internal power loss due to these voltages is the average IL current flowing, or IIN, through either VSAT or VD1. For VSAT = VD1 = 1V this power loss becomes IIN(DC) (1V).
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LM2524D, LM3524D www.ti.com SNVS766E – JUNE 2009 – REVISED MAY 2013 This holds the output of the error amplifier initially low thus reducing the duty-cycle to a minimum. Without the slow start circuit the inductor may saturate at turn-on because it has to supply high peak currents to charge the output capacitor from 0V. It should also be noted that this circuit has no supply rejection.
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LM2524D, LM3524D SNVS766E – JUNE 2009 – REVISED MAY 2013 www.ti.com REVISION HISTORY Changes from Revision D (May 2013) to Revision E • 22 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 30-Apr-2014 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
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MECHANICAL DATA NFG0016E N0016E N16E (Rev G) www.ti.
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