Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 100 (14x14) 32-Bit 50 MHz I/O number 42

Stellaris

LM3S8962 Microcontroller

DATA SHEET

Texas Instruments Incorporated

DS-LM3S8962-12746.2515

SPMS001H

TEXAS INSTRUMENTS-PRODUCTION DATA

NRND: Not recommended for new designs.

Summary of content (807 pages)

PAGE 1
NRND: Not recommended for new designs. TE X AS I NS TRUM E NTS - P RO DUCTION D ATA ® Stellaris LM3S8962 Microcontroller D ATA SHE E T D S -LM3S 8962 - 1 2 7 4 6 .
PAGE 2
NRND: Not recommended for new designs. Copyright Copyright © 2007-2012 Texas Instruments Incorporated All rights reserved. Stellaris and StellarisWare® are registered trademarks of Texas Instruments Incorporated. ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited. Other names and brands may be claimed as the property of others. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty.
PAGE 3
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table of Contents Revision History ............................................................................................................................. 27 About This Document .................................................................................................................... 34 Audience ........................................................................................................................
PAGE 4
NRND: Not recommended for new designs. Table of Contents 2.5.4 2.5.5 2.5.6 2.5.7 2.6 2.6.1 2.6.2 2.6.3 2.6.4 2.7 2.7.1 2.7.2 2.8 Vector Table .................................................................................................................. 87 Exception Priorities ....................................................................................................... 88 Interrupt Priority Grouping ..............................................................................................
PAGE 5
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 6 Hibernation Module .............................................................................................. 242 6.1 6.2 6.3 6.3.1 6.3.2 6.3.3 6.3.4 6.3.5 6.3.6 6.3.7 6.3.8 6.4 6.4.1 6.4.2 6.4.3 6.4.4 6.4.5 6.5 6.6 Block Diagram ............................................................................................................ Signal Description ..................................................................
PAGE 6
NRND: Not recommended for new designs. Table of Contents 9.3.2 9.3.3 9.4 9.4.1 9.4.2 9.4.3 9.4.4 9.4.5 9.4.6 9.5 9.6 32-Bit Timer Operating Modes ...................................................................................... 16-Bit Timer Operating Modes ...................................................................................... Initialization and Configuration ..................................................................................... 32-Bit One-Shot/Periodic Timer Mode ......
PAGE 7
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 13 Synchronous Serial Interface (SSI) .................................................................... 476 13.1 13.2 13.3 13.3.1 13.3.2 13.3.3 13.3.4 13.4 13.5 13.6 Block Diagram ............................................................................................................ Signal Description .......................................................................................................
PAGE 8
NRND: Not recommended for new designs. Table of Contents 16 Ethernet Controller .............................................................................................. 598 16.1 16.2 16.3 16.3.1 16.3.2 16.3.3 16.3.4 16.4 16.4.1 16.4.2 16.5 16.6 16.7 Block Diagram ............................................................................................................ 598 Signal Description .......................................................................................................
PAGE 9
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 21.1.1 21.1.2 21.1.3 21.1.4 21.2 21.2.1 21.2.2 21.2.3 21.2.4 21.3 Signals by Pin Number ................................................................................................ 718 Signals by Signal Name ............................................................................................... 722 Signals by Function, Except for GPIO ...........................................................................
PAGE 10
NRND: Not recommended for new designs. Table of Contents A.4.5 A.4.6 COMMAND_RUN (0x22) ............................................................................................. 769 COMMAND_RESET (0x25) ......................................................................................... 769 B Register Quick Reference ................................................................................... 771 C Ordering and Contact Information .......................................................
PAGE 11
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller List of Figures Figure 1-1. Figure 2-1. Figure 2-2. Figure 2-3. Figure 2-4. Figure 2-5. Figure 2-6. Figure 2-7. Figure 3-1. Figure 4-1. Figure 4-2. Figure 4-3. Figure 4-4. Figure 4-5. Figure 5-1. Figure 5-2. Figure 5-3. Figure 5-4. Figure 5-5. Figure 6-1. Figure 6-2. Figure 6-3. Figure 7-1. Figure 8-1. Figure 8-2. Figure 8-3. Figure 9-1. Figure 9-2. Figure 9-3. Figure 9-4. Figure 10-1. Figure 11-1. Figure 11-2. Figure 11-3.
PAGE 12
NRND: Not recommended for new designs. Table of Contents Figure 13-8. Figure 13-9. Figure 13-10. Figure 13-11. Figure 13-12. Figure 14-1. Figure 14-2. Figure 14-3. Figure 14-4. Figure 14-5. Figure 14-6. Figure 14-7. Figure 14-8. Figure 14-9. Figure 14-10. Figure 14-11. Figure 14-12. Figure 14-13. Figure 15-1. Figure 15-2. Figure 15-3. Figure 15-4. Figure 16-1. Figure 16-2. Figure 16-3. Figure 16-4. Figure 17-1. Figure 17-2. Figure 17-3. Figure 18-1. Figure 18-2. Figure 18-3. Figure 18-4. Figure 18-5.
PAGE 13
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Figure 23-10. Hibernation Module Timing ................................................................................. 758 Figure 23-11. ADC Input Equivalency Diagram ......................................................................... 759 Figure 23-12. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement ...............................................................................................
PAGE 14
NRND: Not recommended for new designs. Table of Contents List of Tables Table 1. Table 2. Table 2-1. Table 2-2. Table 2-3. Table 2-4. Table 2-5. Table 2-6. Table 2-7. Table 2-8. Table 2-9. Table 2-10. Table 2-11. Table 2-12. Table 2-13. Table 3-1. Table 3-2. Table 3-3. Table 3-4. Table 3-5. Table 3-6. Table 3-7. Table 3-8. Table 3-9. Table 4-1. Table 4-2. Table 4-3. Table 4-4. Table 5-1. Table 5-2. Table 5-3. Table 5-4. Table 5-5. Table 5-6. Table 5-7. Table 5-8. Table 6-1. Table 6-2. Table 6-3. Table 7-1.
PAGE 15
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 8-5. Table 8-6. Table 8-7. Table 8-8. Table 9-1. Table 9-2. Table 9-3. Table 9-4. Table 9-5. Table 10-1. Table 11-1. Table 11-2. Table 11-3. Table 11-4. Table 11-5. Table 12-1. Table 12-2. Table 12-3. Table 13-1. Table 13-2. Table 13-3. Table 14-1. Table 14-2. Table 14-3. Table 14-4. Table 14-5. Table 15-1. Table 15-2. Table 15-3. Table 15-4. Table 15-5. Table 16-1. Table 16-2. Table 16-3. Table 16-4. Table 17-1.
PAGE 16
NRND: Not recommended for new designs. Table of Contents Table 21-4. Table 21-5. Table 21-6. Table 21-7. Table 21-8. Table 21-9. Table 21-10. Table 22-1. Table 22-2. Table 22-3. Table 23-1. Table 23-2. Table 23-3. Table 23-4. Table 23-5. Table 23-6. Table 23-7. Table 23-8. Table 23-9. Table 23-10. Table 23-11. Table 23-12. Table 23-13. Table 23-14. Table 23-15. Table 23-16. Table 23-17. Table 23-18. Table 23-19. Table 23-20. Table 23-21. Table 23-22. Table 23-23. Table 23-24. Table 23-25. Table 23-26.
PAGE 17
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller List of Registers The Cortex-M3 Processor .............................................................................................................
PAGE 18
NRND: Not recommended for new designs. Table of Contents Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: Register 33: Register 34: Register 35: Register 36: Register 37: Register 38: Register 39: Register 40: Register 41: Register 42: Register 43: Register 44: Register 45: Register 46: Register 47: Register 48: Register 49: Register 50: Interrupt 36-39 Priority (PRI9), offset 0x424 ...........................................
PAGE 19
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ....................... 221 Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 ................................... 223 Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 .................................
PAGE 20
NRND: Not recommended for new designs. Table of Contents Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: Register 26: Register 27: Register 28: Register 29: Register 30: Register 31: Register 32: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................
PAGE 21
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 379 Watchdog Interrupt Clear (WDTICR), offset 0x00C ...........................................
PAGE 22
NRND: Not recommended for new designs. Table of Contents Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: Register 17: Register 18: Register 19: Register 20: Register 21: Register 22: Register 23: Register 24: Register 25: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 445 UART Flag (UARTFR), offset 0x018 ....................
PAGE 23
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: Register 12: Register 13: Register 14: Register 15: Register 16: I2C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 531 I2C Master Data (I2CMDR), offset 0x008 .........................................................................
PAGE 24
NRND: Not recommended for new designs. Table of Contents Register 32: Register 33: Register 34: Register 35: Register 36: Register 37: CAN New Data 1 (CANNWDA1), offset 0x120 ................................................................. CAN New Data 2 (CANNWDA2), offset 0x124 ................................................................. CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140 ..................................... CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144 .......
PAGE 25
NRND: Not recommended for new designs.
PAGE 26
NRND: Not recommended for new designs. Table of Contents Quadrature Encoder Interface (QEI) .......................................................................................... 698 Register 1: Register 2: Register 3: Register 4: Register 5: Register 6: Register 7: Register 8: Register 9: Register 10: Register 11: QEI Control (QEICTL), offset 0x000 ................................................................................ QEI Status (QEISTAT), offset 0x004 ......................................
PAGE 27
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Revision History The revision history table notes changes made between the indicated revisions of the LM3S8962 data sheet. Table 1. Revision History Date June 2012 November 2011 Revision Description 12746.2515 ■ 11108 Corrected missing interrupt 9 in "Interrupts" table. ■ Minor data sheet clarifications and corrections. ■ Added module-specific pin tables to each chapter in the new Signal Description sections.
PAGE 28
NRND: Not recommended for new designs. Revision History Table 1. Revision History (continued) Date Revision January 2011 9102 September 2010 7787 Description ■ In Application Interrupt and Reset Control (APINT) register, changed bit name from SYSRESETREQ to SYSRESREQ. ■ Added DEBUG (Debug Priority) bit field to System Handler Priority 3 (SYSPRI3) register. ■ Added "Reset Sources" table to System Control chapter.
PAGE 29
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 1. Revision History (continued) Date Revision June 2010 7393 April 2010 January 2010 7007 6712 Description ■ Corrected base address for SRAM in architectural overview chapter. ■ Clarified system clock operation, adding content to “Clock Control” on page 181. ■ Clarified CAN bit timing examples. ■ In Signal Tables chapter, added table "Connections for Unused Signals.
PAGE 30
NRND: Not recommended for new designs. Revision History Table 1. Revision History (continued) Date Revision October 2009 6462 Description ■ Deleted MAXADCSPD bit field from DCGC0 register as it is not applicable in Deep-Sleep mode. ■ Removed erroneous reference to the WRC bit in the Hibernation chapter. ■ Deleted reset value for 16-bit mode from GPTMTAILR, GPTMTAMATCHR, and GPTMTAR registers because the module resets in 32-bit mode. ■ Clarified PWM source for ADC triggering.
PAGE 31
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 1. Revision History (continued) Date Revision January 2009 4660 November 2008 October 2008 August 2008 July 2008 May 2008 4283 4149 3447 3108 2972 Description ■ Corrected bit type for RELOAD bit field in SysTick Reload Value register; changed to R/W. ■ Clarification added as to what happens when the SSI in slave mode is required to transmit but there is no data in the TX FIFO.
PAGE 32
NRND: Not recommended for new designs. Revision History Table 1. Revision History (continued) Date Revision April 2008 2881 Description ■ The ΘJA value was changed from 55.3 to 34 in the "Thermal Characteristics" table in the Operating Characteristics chapter. ■ Bit 31 of the DC3 register was incorrectly described in prior versions of the data sheet. A reset of 1 indicates that an even CCP pin is present and can be used as a 32-KHz input clock.
PAGE 33
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 1. Revision History (continued) Date Revision Description ■ March 2008 2550 Additional minor data sheet clarifications and corrections. Started tracking revision history.
PAGE 34
NRND: Not recommended for new designs. About This Document About This Document This data sheet provides reference information for the LM3S8962 microcontroller, describing the functional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3 core. Audience This manual is intended for system software developers, hardware designers, and application developers. About This Manual This document is organized into sections that correspond to each major feature.
PAGE 35
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Documentation Conventions This document uses the conventions shown in Table 2 on page 35. Table 2. Documentation Conventions Notation Meaning General Register Notation REGISTER APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On and Brown-Out Reset Control register. If a register name contains a lowercase n, it represents more than one register.
PAGE 36
NRND: Not recommended for new designs. About This Document Table 2. Documentation Conventions (continued) Notation Meaning assert a signal Change the value of the signal from the logically False state to the logically True state. For active High signals, the asserted signal value is 1 (High); for active Low signals, the asserted signal value is 0 (Low). The active polarity (High or Low) is defined by the signal name (see SIGNAL and SIGNAL below).
PAGE 37
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 1 Architectural Overview ® The Stellaris family of microcontrollers—the first ARM® Cortex™-M3 based controllers—brings high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. These pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package with a small footprint.
PAGE 38
NRND: Not recommended for new designs.
PAGE 39
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller – 1.25 DMIPS/MHz ■ JTAG – IEEE 1149.
PAGE 40
NRND: Not recommended for new designs. Architectural Overview • Edge-triggered on rising, falling, or both • Level-sensitive on High or Low values – Bit masking in both read and write operations through address lines – Can initiate an ADC sample sequence – Pins configured as digital inputs are Schmitt-triggered.
PAGE 41
NRND: Not recommended for new designs.
PAGE 42
NRND: Not recommended for new designs. Architectural Overview – Converter uses an internal 3-V reference – Power and ground for the analog circuitry is separate from the digital power and ground ■ UART – Two fully programmable 16C550-type UARTs with IrDA support – Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading – Programmable baud-rate generator allowing speeds up to 3.
PAGE 43
NRND: Not recommended for new designs.
PAGE 44
NRND: Not recommended for new designs.
PAGE 45
NRND: Not recommended for new designs.
PAGE 46
NRND: Not recommended for new designs. Architectural Overview • Velocity-timer expiration • Direction change • Quadrature error detection ■ Power – On-chip Low Drop-Out (LDO) voltage regulator, with programmable output user-adjustable from 2.25 V to 2.75 V – Hibernation module handles the power-up/down 3.
PAGE 47
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller ■ Medical instrumentation ■ Fire and security ■ Power and energy ■ Transportation 1.3 High-Level Block Diagram Figure 1-1 on page 48 depicts the features on the Stellaris LM3S8962 microcontroller.
PAGE 48
NRND: Not recommended for new designs. Architectural Overview Figure 1-1. Stellaris LM3S8962 Microcontroller High-Level Block Diagram JTAG/SWD ARM® Cortex™-M3 (50MHz) System Control and Clocks (w/ Precis. Osc.
PAGE 49
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 1.4 Functional Overview The following sections provide an overview of the features of the LM3S8962 microcontroller. The page number in parenthesis indicates where that feature is discussed in detail. Ordering and support information can be found in “Ordering and Contact Information” on page 797. 1.4.1 ARM Cortex™-M3 1.4.1.
PAGE 50
NRND: Not recommended for new designs. Architectural Overview 1.4.1.5 System Control Block (SCB) (see page 101) The SCB provides system implementation information and system control, including configuration, control, and reporting of system exceptions. 1.4.1.6 Memory Protection Unit (MPU) (see page 101) The MPU supports the standard ARMv7 Protected Memory System Architecture (PMSA) model.
PAGE 51
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller addition, it can capture a running estimate of the velocity of the encoder wheel. The LM3S8962 microcontroller includes two QEI modules, which enables control of two motors at the same time. 1.4.3 Analog Peripherals To handle analog signals, the LM3S8962 microcontroller offers an Analog-to-Digital Converter (ADC). For support of analog signals, the LM3S8962 microcontroller offers one analog comparator. 1.4.3.
PAGE 52
NRND: Not recommended for new designs. Architectural Overview 1.4.4.1 UART (see page 434) A Universal Asynchronous Receiver/Transmitter (UART) is an integrated circuit used for RS-232C serial communications, containing a transmitter (parallel-to-serial converter) and a receiver (serial-to-parallel converter), each clocked separately. The LM3S8962 controller includes two fully programmable 16C550-type UARTs that support data transfer speeds up to 3.125 Mbps.
PAGE 53
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Both the I2C master and slave can generate interrupts. The I2C master generates interrupts when a transmit or receive operation completes (or aborts due to an error). The I2C slave generates interrupts when data has been sent or requested by a master. 1.4.4.4 Controller Area Network (see page 551) Controller Area Network (CAN) is a multicast shared serial-bus standard for connecting electronic control units (ECUs).
PAGE 54
NRND: Not recommended for new designs. Architectural Overview When configured in 32-bit mode, a timer can run as a Real-Time Clock (RTC), one-shot timer or periodic timer. When in 16-bit mode, a timer can run as a one-shot timer or periodic timer, and can extend its precision by using an 8-bit prescaler. A 16-bit timer can also be configured for event capture or Pulse Width Modulation (PWM) generation. 1.4.5.
PAGE 55
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller operation of the JTAG port and TAP controller, please refer to the IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture. The Stellaris JTAG controller works with the ARM JTAG controller built into the Cortex-M3 core. This is implemented by multiplexing the TDO outputs from both JTAG controllers. ARM JTAG instructions select the ARM TDO output while Stellaris JTAG instructions select the Stellaris TDO outputs.
PAGE 56
NRND: Not recommended for new designs. The Cortex-M3 Processor 2 The Cortex-M3 Processor The ARM® Cortex™-M3 processor provides a high-performance, low-cost platform that meets the system requirements of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. Features include: ■ Compact core.
PAGE 57
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller This chapter provides information on the Stellaris implementation of the Cortex-M3 processor, including the programming model, the memory model, the exception model, fault handling, and power management. For technical details on the instruction set, see the Cortex™-M3/M4 Instruction Set Technical User's Manual. 2.
PAGE 58
NRND: Not recommended for new designs. The Cortex-M3 Processor Figure 2-1. CPU Block Diagram Nested Vectored Interrupt Controller Interrupts Sleep ARM Cortex-M3 CM3 Core Debug Instructions Data Trace Port Interface Unit Memory Protection Unit Flash Patch and Breakpoint Instrumentation Data Watchpoint Trace Macrocell and Trace ROM Table Private Peripheral Bus (internal) Adv. Peripheral Bus Bus Matrix Serial Wire JTAG Debug Port Debug Access Port 2.2 Overview 2.2.
PAGE 59
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller The Flash Patch and Breakpoint Unit (FPB) provides up to eight hardware breakpoint comparators that debuggers can use. The comparators in the FPB also provide remap functions of up to eight words in the program code in the CODE memory region. This enables applications stored in a read-only area of Flash memory to be patched in another area of on-chip SRAM or Flash memory.
PAGE 60
NRND: Not recommended for new designs. The Cortex-M3 Processor The programming model interface to the processor. The SCB provides system implementation information and system control, including configuration, control, and reporting of system exceptions (see “System Control Block (SCB)” on page 101). ■ Memory Protection Unit (MPU) Improves system reliability by defining the memory attributes for different memory regions.
PAGE 61
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller the main stack and the process stack, with a pointer for each held in independent registers (see the SP register on page 64). In Thread mode, the CONTROL register (see page 74) controls whether the processor uses the main stack or the process stack. In Handler mode, the processor always uses the main stack. The options for processor operations are shown in Table 2-1 on page 61. Table 2-1.
PAGE 62
NRND: Not recommended for new designs. The Cortex-M3 Processor Table 2-2.
PAGE 63
NRND: Not recommended for new designs.
PAGE 64
NRND: Not recommended for new designs. The Cortex-M3 Processor Register 14: Stack Pointer (SP) The Stack Pointer (SP) is register R13. In Thread mode, the function of this register changes depending on the ASP bit in the Control Register (CONTROL) register. When the ASP bit is clear, this register is the Main Stack Pointer (MSP). When the ASP bit is set, this register is the Process Stack Pointer (PSP). On reset, the ASP bit is clear, and the processor loads the MSP with the value from address 0x0000.0000.
PAGE 65
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 15: Link Register (LR) The Link Register (LR) is register R14, and it stores the return information for subroutines, function calls, and exceptions. LR can be accessed from either privileged or unprivileged mode. EXC_RETURN is loaded into LR on exception entry. See Table 2-10 on page 91 for the values and description. Link Register (LR) Type R/W, reset 0xFFFF.
PAGE 66
NRND: Not recommended for new designs. The Cortex-M3 Processor Register 16: Program Counter (PC) The Program Counter (PC) is register R15, and it contains the current program address. On reset, the processor loads the PC with the value of the reset vector, which is at address 0x0000.0004. Bit 0 of the reset vector is loaded into the THUMB bit of the EPSR at reset and must be 1. The PC register can be accessed in either privileged or unprivileged mode.
PAGE 67
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 17: Program Status Register (PSR) Note: This register is also referred to as xPSR.
PAGE 68
NRND: Not recommended for new designs. The Cortex-M3 Processor Bit/Field Name Type Reset 31 N R/W 0 Description APSR Negative or Less Flag Value Description 1 The previous operation result was negative or less than. 0 The previous operation result was positive, zero, greater than, or equal. The value of this bit is only meaningful when accessing PSR or APSR. 30 Z R/W 0 APSR Zero Flag Value Description 1 The previous operation result was zero. 0 The previous operation result was non-zero.
PAGE 69
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset 26:25 ICI / IT RO 0x0 Description EPSR ICI / IT status These bits, along with bits 15:10, contain the Interruptible-Continuable Instruction (ICI) field for an interrupted load multiple or store multiple instruction or the execution state bits of the IT instruction. When EPSR holds the ICI execution state, bits 26:25 are zero.
PAGE 70
NRND: Not recommended for new designs. The Cortex-M3 Processor Bit/Field Name Type Reset Description 5:0 ISRNUM RO 0x00 IPSR ISR Number This field contains the exception type number of the current Interrupt Service Routine (ISR).
PAGE 71
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 18: Priority Mask Register (PRIMASK) The PRIMASK register prevents activation of all exceptions with programmable priority. Reset, non-maskable interrupt (NMI), and hard fault are the only exceptions with fixed priority. Exceptions should be disabled when they might impact the timing of critical tasks. This register is only accessible in privileged mode.
PAGE 72
NRND: Not recommended for new designs. The Cortex-M3 Processor Register 19: Fault Mask Register (FAULTMASK) The FAULTMASK register prevents activation of all exceptions except for the Non-Maskable Interrupt (NMI). Exceptions should be disabled when they might impact the timing of critical tasks. This register is only accessible in privileged mode. The MSR and MRS instructions are used to access the FAULTMASK register, and the CPS instruction may be used to change the value of the FAULTMASK register.
PAGE 73
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 20: Base Priority Mask Register (BASEPRI) The BASEPRI register defines the minimum priority for exception processing. When BASEPRI is set to a nonzero value, it prevents the activation of all exceptions with the same or lower priority level as the BASEPRI value. Exceptions should be disabled when they might impact the timing of critical tasks. This register is only accessible in privileged mode.
PAGE 74
NRND: Not recommended for new designs. The Cortex-M3 Processor Register 21: Control Register (CONTROL) The CONTROL register controls the stack used and the privilege level for software execution when the processor is in Thread mode. This register is only accessible in privileged mode. Handler mode always uses MSP, so the processor ignores explicit writes to the ASP bit of the CONTROL register when in Handler mode.
PAGE 75
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 2.3.5 Exceptions and Interrupts The Cortex-M3 processor supports interrupts and system exceptions. The processor and the Nested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An exception changes the normal flow of software control. The processor uses Handler mode to handle all exceptions except for reset. See “Exception Entry and Return” on page 89 for more information.
PAGE 76
NRND: Not recommended for new designs. The Cortex-M3 Processor Table 2-4. Memory Map (continued) Start End Description For details, see page ... 0x4000.9000 0x4000.BFFF Reserved - 0x4000.C000 0x4000.CFFF UART0 442 0x4000.D000 0x4000.DFFF UART1 442 0x4000.E000 0x4001.FFFF Reserved - 0x4002.0000 0x4002.0FFF I2C 0 529 0x4002.1000 0x4002.3FFF Reserved - 0x4002.4000 0x4002.4FFF GPIO Port E 301 0x4002.5000 0x4002.5FFF GPIO Port F 301 0x4002.6000 0x4002.
PAGE 77
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 2-4. Memory Map (continued) Start End Description For details, see page ... 0xE004.1000 0xFFFF.FFFF Reserved - 2.4.1 Memory Regions, Types and Attributes The memory map and the programming of the MPU split the memory map into regions. Each region has a defined memory type, and some regions have additional memory attributes. The memory type and attributes determine the behavior of accesses to the region.
PAGE 78
NRND: Not recommended for new designs. The Cortex-M3 Processor Table 2-5. Memory Access Behavior (continued) Address Range Memory Region Memory Type Execute Never (XN) Description 0x2000.0000 - 0x3FFF.FFFF SRAM Normal - This executable region is for data. Code can also be stored here. This region includes bit band and bit band alias areas (see Table 2-6 on page 80). 0x4000.0000 - 0x5FFF.FFFF Peripheral Device XN This region includes bit band and bit band alias areas (see Table 2-7 on page 80).
PAGE 79
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller ■ MPU programming – If the MPU settings are changed and the change must be effective on the very next instruction, use a DSB instruction to ensure the effect of the MPU takes place immediately at the end of context switching. – Use an ISB instruction to ensure the new MPU setting takes effect immediately after programming the MPU region or regions, if the MPU configuration code was accessed using a branch or call.
PAGE 80
NRND: Not recommended for new designs. The Cortex-M3 Processor Table 2-6. SRAM Memory Bit-Banding Regions Address Range Memory Region Instruction and Data Accesses Start End 0x2000.0000 0x2000.FFFF SRAM bit-band region Direct accesses to this memory range behave as SRAM memory accesses, but this region is also bit addressable through bit-band alias. 0x2200.0000 0x221F.FFFF SRAM bit-band alias Data accesses to this region are remapped to bit band region.
PAGE 81
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller ■ The alias word at 0x2200.0000 maps to bit 0 of the bit-band byte at 0x2000.0000: 0x2200.0000 = 0x2200.0000 + (0*32) + (0*4) ■ The alias word at 0x2200.001C maps to bit 7 of the bit-band byte at 0x2000.0000: 0x2200.001C = 0x2200.0000+ (0*32) + (7*4) Figure 2-4. Bit-Band Mapping 32-MB Alias Region 0x23FF.FFFC 0x23FF.FFF8 0x23FF.FFF4 0x23FF.FFF0 0x23FF.FFEC 0x23FF.FFE8 0x23FF.FFE4 0x23FF.FFE0 0x2200.001C 0x2200.
PAGE 82
NRND: Not recommended for new designs. The Cortex-M3 Processor lowest-numbered byte, and the most-significant byte (msbyte) stored at the highest-numbered byte. Figure 2-5 on page 82 illustrates how data is stored. Figure 2-5. Data Storage Memory 7 Register 0 31 2.4.
PAGE 83
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller If the status bit is clear, the read-modify-write completed successfully. If the status bit is set, no write was performed, which indicates that the value returned at step 1 might be out of date. The software must retry the entire read-modify-write sequence. Software can use the synchronization primitives to implement a semaphore as follows: 1.
PAGE 84
NRND: Not recommended for new designs. The Cortex-M3 Processor re-entered errantly. This situation can be avoided by either clearing the interrupt source at the beginning of the interrupt handler or by performing a read or write after the write to clear the interrupt source (and flush the write buffer). See “Nested Vectored Interrupt Controller (NVIC)” on page 99 for more information on exceptions and interrupts. 2.5.1 Exception States Each exception is in one of the following states: ■ Inactive.
PAGE 85
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller ■ Usage Fault. A usage fault is an exception that occurs because of a fault related to instruction execution, such as: – An undefined instruction – An illegal unaligned access – Invalid state on instruction execution – An error on exception return An unaligned address on a word or halfword memory access or division by zero can cause a usage fault when the core is properly configured. ■ SVCall.
PAGE 86
NRND: Not recommended for new designs. The Cortex-M3 Processor Table 2-8. Exception Types (continued) Exception Type a Vector Number Priority Bus Fault 5 programmable Usage Fault 6 7-10 - Vector Address or b Offset Activation c 0x0000.0014 Synchronous when precise and asynchronous when imprecise programmable c 0x0000.0018 Synchronous - c c Reserved SVCall 11 programmable 0x0000.002C Synchronous Debug Monitor 12 programmable 0x0000.0030 Synchronous - 13 - 0x0000.
PAGE 87
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 2-9. Interrupts (continued) 2.5.3 Vector Number Interrupt Number (Bit in Interrupt Registers) Vector Address or Offset Description 38 22 0x0000.0098 Timer 1B 39 23 0x0000.009C Timer 2A 40 24 0x0000.00A0 Timer 2B Analog Comparator 0 41 25 0x0000.00A4 42-43 26-27 - 44 28 0x0000.00B0 System Control 45 29 0x0000.00B4 Flash Memory Control 46 30 0x0000.
PAGE 88
NRND: Not recommended for new designs. The Cortex-M3 Processor Figure 2-6. Vector Table Exception number IRQ number 59 43 . . . 18 2 17 1 16 0 15 -1 14 -2 13 Offset 0x00EC . . . 0x004C 0x0048 0x0044 0x0040 0x003C 0x0038 12 11 Vector IRQ43 . . .
PAGE 89
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller If multiple pending exceptions have the same priority, the pending exception with the lowest exception number takes precedence. For example, if both IRQ[0] and IRQ[1] are pending and have the same priority, then IRQ[0] is processed before IRQ[1]. When the processor is executing an exception handler, the exception handler is preempted if a higher priority exception occurs.
PAGE 90
NRND: Not recommended for new designs. The Cortex-M3 Processor return from the exception handler of the late-arriving exception, the normal tail-chaining rules apply. 2.5.7.1 Exception Entry Exception entry occurs when there is a pending exception with sufficient priority and either the processor is in Thread mode or the new exception is of higher priority than the exception being handled, in which case the new exception preempts the original exception.
PAGE 91
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 2.5.7.2 Exception Return Exception return occurs when the processor is in Handler mode and executes one of the following instructions to load the EXC_RETURN value into the PC: ■ An LDM or POP instruction that loads the PC ■ A BX instruction using any register ■ An LDR instruction with the PC as the destination EXC_RETURN is the value loaded into the LR on exception entry.
PAGE 92
NRND: Not recommended for new designs. The Cortex-M3 Processor 2.6.1 Fault Types Table 2-11 on page 92 shows the types of fault, the handler used for the fault, the corresponding fault status register, and the register bit that indicates the fault has occurred. See page 144 for more information about the fault status registers. Table 2-11.
PAGE 93
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller ■ A fault handler causes a fault with the same or lower priority as the fault it is servicing. This situation happens because the handler for the new fault cannot preempt the currently executing fault handler. ■ An exception handler causes a fault for which the priority is the same as or lower than the currently executing exception. ■ A fault occurs and the handler for that fault is not enabled.
PAGE 94
NRND: Not recommended for new designs. The Cortex-M3 Processor This section describes the mechanisms for entering sleep mode and the conditions for waking up from sleep mode, both of which apply to Sleep mode and Deep-sleep mode. 2.7.1 Entering Sleep Modes This section describes the mechanisms software can use to put the processor into one of the sleep modes. The system can generate spurious wake-up events, for example a debug operation wakes up the processor.
PAGE 95
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller In addition, if the SEVONPEND bit in the SYSCTRL register is set, any new pending interrupt triggers an event and wakes up the processor, even if the interrupt is disabled or has insufficient priority to cause exception entry. For more information about SYSCTRL, see page 133. 2.8 Instruction Set Summary The processor implements a version of the Thumb instruction set. Table 2-13 on page 95 lists the supported instructions.
PAGE 96
NRND: Not recommended for new designs. The Cortex-M3 Processor Table 2-13.
PAGE 97
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 2-13.
PAGE 98
NRND: Not recommended for new designs. Cortex-M3 Peripherals 3 Cortex-M3 Peripherals ® This chapter provides information on the Stellaris implementation of the Cortex-M3 processor peripherals, including: ■ SysTick (see page 98) Provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism.
PAGE 99
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller ■ A variable rate alarm or signal timer—the duration is range-dependent on the reference clock used and the dynamic range of the counter. ■ A simple counter used to measure time to completion and time used. ■ An internal clock source control based on missing/meeting durations.
PAGE 100
NRND: Not recommended for new designs. Cortex-M3 Peripherals The processor automatically stacks its state on exception entry and unstacks this state on exception exit, with no instruction overhead, providing low latency exception handling. 3.1.2.1 Level-Sensitive and Pulse Interrupts The processor supports both level-sensitive and pulse interrupts. Pulse interrupts are also described as edge-triggered interrupts.
PAGE 101
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller – For a pulse interrupt, the state of the interrupt changes to inactive, if the state was pending or to active, if the state was active and pending. 3.1.3 System Control Block (SCB) The System Control Block (SCB) provides system implementation information and system control, including configuration, control, and reporting of the system exceptions. 3.1.
PAGE 102
NRND: Not recommended for new designs. Cortex-M3 Peripherals The processor does not support unaligned accesses to MPU registers. When setting up the MPU, and if the MPU has previously been programmed, disable unused regions to prevent any previous region settings from affecting the new MPU setup. 3.1.4.1 Updating an MPU Region To update the attributes for an MPU region, the MPU Region Number (MPUNUMBER), MPU Region Base Address (MPUBASE) and MPUATTR registers must be updated.
PAGE 103
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller For example, if all of the memory access behavior is intended to take effect immediately after the programming sequence, then a DSB instruction and an ISB instruction should be used. A DSB is required after changing MPU settings, such as at the end of context switch. An ISB is required if the code that programs the MPU region or regions is entered using a branch or call.
PAGE 104
NRND: Not recommended for new designs. Cortex-M3 Peripherals Example of SRD Use Two regions with the same base address overlap. Region one is 128 KB, and region two is 512 KB. To ensure the attributes from region one apply to the first 128 KB region, configure the SRD field for region two to 0x03 to disable the first two subregions, as Figure 3-1 on page 104 shows. Figure 3-1. SRD Use Example Region 2, with subregions Region 1 Base address of both regions 3.1.4.
PAGE 105
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 3-3. TEX, S, C, and B Bit Field Encoding (continued) TEX S C B Memory Type Shareability Other Attributes 1BB 0 A A Normal Not shareable 1BB 1 A A Normal Shareable Cached memory (BB = outer policy, AA = inner policy). See Table 3-4 for the encoding of the AA and BB bits. a. The MPU ignores the value of this bit.
PAGE 106
NRND: Not recommended for new designs. Cortex-M3 Peripherals In current Stellaris microcontroller implementations, the shareability and cache policy attributes do not affect the system behavior. However, using these settings for the MPU regions can make the application code more portable. The values given are for typical situations. 3.1.4.
PAGE 107
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 3-7. Peripherals Register Map (continued) Description See page Offset Name Type Reset 0x414 PRI5 R/W 0x0000.0000 Interrupt 20-23 Priority 123 0x418 PRI6 R/W 0x0000.0000 Interrupt 24-27 Priority 123 0x41C PRI7 R/W 0x0000.0000 Interrupt 28-31 Priority 123 0x420 PRI8 R/W 0x0000.0000 Interrupt 32-35 Priority 123 0x424 PRI9 R/W 0x0000.
PAGE 108
NRND: Not recommended for new designs. Cortex-M3 Peripherals Table 3-7. Peripherals Register Map (continued) Name Type Reset 0xDB4 MPUBASE3 R/W 0x0000.0000 MPU Region Base Address Alias 3 157 0xDB8 MPUATTR3 R/W 0x0000.0000 MPU Region Attribute and Size Alias 3 159 3.3 Description See page Offset System Timer (SysTick) Register Descriptions This section lists and describes the System Timer registers, in numerical order by address offset.
PAGE 109
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 1: SysTick Control and Status Register (STCTRL), offset 0x010 Note: This register can only be accessed from privileged mode. The SysTick STCTRL register enables the SysTick features. SysTick Control and Status Register (STCTRL) Base 0xE000.E000 Offset 0x010 Type R/W, reset 0x0000.
PAGE 110
NRND: Not recommended for new designs. Cortex-M3 Peripherals Bit/Field Name Type Reset 1 INTEN R/W 0 0 ENABLE R/W 0 Description Interrupt Enable Value Description 0 Interrupt generation is disabled. Software can use the COUNT bit to determine if the counter has ever reached 0. 1 An interrupt is generated to the NVIC when SysTick counts to 0. Enable Value Description 0 The counter is disabled. 1 Enables SysTick to operate in a multi-shot way.
PAGE 111
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 2: SysTick Reload Value Register (STRELOAD), offset 0x014 Note: This register can only be accessed from privileged mode. The STRELOAD register specifies the start value to load into the SysTick Current Value (STCURRENT) register when the counter reaches 0. The start value can be between 0x1 and 0x00FF.FFFF.
PAGE 112
NRND: Not recommended for new designs. Cortex-M3 Peripherals Register 3: SysTick Current Value Register (STCURRENT), offset 0x018 Note: This register can only be accessed from privileged mode. The STCURRENT register contains the current value of the SysTick counter. SysTick Current Value Register (STCURRENT) Base 0xE000.E000 Offset 0x018 Type R/WC, reset 0x0000.
PAGE 113
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 4: Interrupt 0-31 Set Enable (EN0), offset 0x100 Note: This register can only be accessed from privileged mode. The EN0 register enables interrupts and shows which interrupts are enabled. Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. See Table 2-9 on page 86 for interrupt assignments. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority.
PAGE 114
NRND: Not recommended for new designs. Cortex-M3 Peripherals Register 5: Interrupt 32-43 Set Enable (EN1), offset 0x104 Note: This register can only be accessed from privileged mode. The EN1 register enables interrupts and shows which interrupts are enabled. Bit 0 corresponds to Interrupt 32; bit 11 corresponds to Interrupt 43. See Table 2-9 on page 86 for interrupt assignments. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority.
PAGE 115
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 6: Interrupt 0-31 Clear Enable (DIS0), offset 0x180 Note: This register can only be accessed from privileged mode. The DIS0 register disables interrupts. Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. See Table 2-9 on page 86 for interrupt assignments. Interrupt 0-31 Clear Enable (DIS0) Base 0xE000.E000 Offset 0x180 Type R/W, reset 0x0000.
PAGE 116
NRND: Not recommended for new designs. Cortex-M3 Peripherals Register 7: Interrupt 32-43 Clear Enable (DIS1), offset 0x184 Note: This register can only be accessed from privileged mode. The DIS1 register disables interrupts. Bit 0 corresponds to Interrupt 32; bit 11 corresponds to Interrupt 43. See Table 2-9 on page 86 for interrupt assignments. Interrupt 32-43 Clear Enable (DIS1) Base 0xE000.E000 Offset 0x184 Type R/W, reset 0x0000.
PAGE 117
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 8: Interrupt 0-31 Set Pending (PEND0), offset 0x200 Note: This register can only be accessed from privileged mode. The PEND0 register forces interrupts into the pending state and shows which interrupts are pending. Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. See Table 2-9 on page 86 for interrupt assignments. Interrupt 0-31 Set Pending (PEND0) Base 0xE000.
PAGE 118
NRND: Not recommended for new designs. Cortex-M3 Peripherals Register 9: Interrupt 32-43 Set Pending (PEND1), offset 0x204 Note: This register can only be accessed from privileged mode. The PEND1 register forces interrupts into the pending state and shows which interrupts are pending. Bit 0 corresponds to Interrupt 32; bit 11 corresponds to Interrupt 43. See Table 2-9 on page 86 for interrupt assignments. Interrupt 32-43 Set Pending (PEND1) Base 0xE000.E000 Offset 0x204 Type R/W, reset 0x0000.
PAGE 119
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 10: Interrupt 0-31 Clear Pending (UNPEND0), offset 0x280 Note: This register can only be accessed from privileged mode. The UNPEND0 register shows which interrupts are pending and removes the pending state from interrupts. Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. See Table 2-9 on page 86 for interrupt assignments. Interrupt 0-31 Clear Pending (UNPEND0) Base 0xE000.
PAGE 120
NRND: Not recommended for new designs. Cortex-M3 Peripherals Register 11: Interrupt 32-43 Clear Pending (UNPEND1), offset 0x284 Note: This register can only be accessed from privileged mode. The UNPEND1 register shows which interrupts are pending and removes the pending state from interrupts. Bit 0 corresponds to Interrupt 32; bit 11 corresponds to Interrupt 43. See Table 2-9 on page 86 for interrupt assignments. Interrupt 32-43 Clear Pending (UNPEND1) Base 0xE000.
PAGE 121
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 12: Interrupt 0-31 Active Bit (ACTIVE0), offset 0x300 Note: This register can only be accessed from privileged mode. The ACTIVE0 register indicates which interrupts are active. Bit 0 corresponds to Interrupt 0; bit 31 corresponds to Interrupt 31. See Table 2-9 on page 86 for interrupt assignments. Caution – Do not manually set or clear the bits in this register. Interrupt 0-31 Active Bit (ACTIVE0) Base 0xE000.
PAGE 122
NRND: Not recommended for new designs. Cortex-M3 Peripherals Register 13: Interrupt 32-43 Active Bit (ACTIVE1), offset 0x304 Note: This register can only be accessed from privileged mode. The ACTIVE1 register indicates which interrupts are active. Bit 0 corresponds to Interrupt 32; bit 11 corresponds to Interrupt 43. See Table 2-9 on page 86 for interrupt assignments. Caution – Do not manually set or clear the bits in this register. Interrupt 32-43 Active Bit (ACTIVE1) Base 0xE000.
PAGE 123
NRND: Not recommended for new designs.
PAGE 124
NRND: Not recommended for new designs. Cortex-M3 Peripherals Bit/Field Name Type Reset 31:29 INTD R/W 0x0 Description Interrupt Priority for Interrupt [4n+3] This field holds a priority value, 0-7, for the interrupt with the number [4n+3], where n is the number of the Interrupt Priority register (n=0 for PRI0, and so on). The lower the value, the greater the priority of the corresponding interrupt. 28:24 reserved RO 0x0 Software should not rely on the value of a reserved bit.
PAGE 125
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 25: Software Trigger Interrupt (SWTRIG), offset 0xF00 Note: Only privileged software can enable unprivileged access to the SWTRIG register. Writing an interrupt number to the SWTRIG register generates a Software Generated Interrupt (SGI). See Table 2-9 on page 86 for interrupt assignments.
PAGE 126
NRND: Not recommended for new designs. Cortex-M3 Peripherals Register 26: CPU ID Base (CPUID), offset 0xD00 Note: This register can only be accessed from privileged mode. The CPUID register contains the ARM® Cortex™-M3 processor part number, version, and implementation information. CPU ID Base (CPUID) Base 0xE000.E000 Offset 0xD00 Type RO, reset 0x411F.
PAGE 127
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 27: Interrupt Control and State (INTCTRL), offset 0xD04 Note: This register can only be accessed from privileged mode. The INCTRL register provides a set-pending bit for the NMI exception, and set-pending and clear-pending bits for the PendSV and SysTick exceptions.
PAGE 128
NRND: Not recommended for new designs. Cortex-M3 Peripherals Bit/Field Name Type Reset 27 UNPENDSV WO 0 Description PendSV Clear Pending Value Description 0 On a write, no effect. 1 On a write, removes the pending state from the PendSV exception. This bit is write only; on a register read, its value is unknown. 26 PENDSTSET R/W 0 SysTick Set Pending Value Description 0 On a read, indicates a SysTick exception is not pending. On a write, no effect.
PAGE 129
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset Description 17:12 VECPEND RO 0x00 Interrupt Pending Vector Number This field contains the exception number of the highest priority pending enabled exception. The value indicated by this field includes the effect of the BASEPRI and FAULTMASK registers, but not any effect of the PRIMASK register.
PAGE 130
NRND: Not recommended for new designs. Cortex-M3 Peripherals Register 28: Vector Table Offset (VTABLE), offset 0xD08 Note: This register can only be accessed from privileged mode. The VTABLE register indicates the offset of the vector table base address from memory address 0x0000.0000. Vector Table Offset (VTABLE) Base 0xE000.E000 Offset 0xD08 Type R/W, reset 0x0000.
PAGE 131
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 29: Application Interrupt and Reset Control (APINT), offset 0xD0C Note: This register can only be accessed from privileged mode. The APINT register provides priority grouping control for the exception model, endian status for data accesses, and reset control of the system. To write to this register, 0x05FA must be written to the VECTKEY field, otherwise the write is ignored.
PAGE 132
NRND: Not recommended for new designs. Cortex-M3 Peripherals Bit/Field Name Type Reset 10:8 PRIGROUP R/W 0x0 Description Interrupt Priority Grouping This field determines the split of group priority from subpriority (see Table 3-8 on page 131 for more information). 7:3 reserved RO 0x0 2 SYSRESREQ WO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
PAGE 133
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 30: System Control (SYSCTRL), offset 0xD10 Note: This register can only be accessed from privileged mode. The SYSCTRL register controls features of entry to and exit from low-power state. System Control (SYSCTRL) Base 0xE000.E000 Offset 0xD10 Type R/W, reset 0x0000.
PAGE 134
NRND: Not recommended for new designs. Cortex-M3 Peripherals Bit/Field Name Type Reset 1 SLEEPEXIT R/W 0 Description Sleep on ISR Exit Value Description 0 When returning from Handler mode to Thread mode, do not sleep when returning to Thread mode. 1 When returning from Handler mode to Thread mode, enter sleep or deep sleep on return from an ISR. Setting this bit enables an interrupt-driven application to avoid returning to an empty main application.
PAGE 135
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 31: Configuration and Control (CFGCTRL), offset 0xD14 Note: This register can only be accessed from privileged mode. The CFGCTRL register controls entry to Thread mode and enables: the handlers for NMI, hard fault and faults escalated by the FAULTMASK register to ignore bus faults; trapping of divide by zero and unaligned accesses; and access to the SWTRIG register by unprivileged software (see page 125).
PAGE 136
NRND: Not recommended for new designs. Cortex-M3 Peripherals Bit/Field Name Type Reset 4 DIV0 R/W 0 Description Trap on Divide by 0 This bit enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0. Value Description 3 UNALIGNED R/W 0 0 Do not trap on divide by 0. A divide by zero returns a quotient of 0. 1 Trap on divide by 0. Trap on Unaligned Access Value Description 0 Do not trap on unaligned halfword and word accesses.
PAGE 137
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 32: System Handler Priority 1 (SYSPRI1), offset 0xD18 Note: This register can only be accessed from privileged mode. The SYSPRI1 register configures the priority level, 0 to 7 of the usage fault, bus fault, and memory management fault exception handlers. This register is byte-accessible. System Handler Priority 1 (SYSPRI1) Base 0xE000.E000 Offset 0xD18 Type R/W, reset 0x0000.
PAGE 138
NRND: Not recommended for new designs. Cortex-M3 Peripherals Register 33: System Handler Priority 2 (SYSPRI2), offset 0xD1C Note: This register can only be accessed from privileged mode. The SYSPRI2 register configures the priority level, 0 to 7 of the SVCall handler. This register is byte-accessible. System Handler Priority 2 (SYSPRI2) Base 0xE000.E000 Offset 0xD1C Type R/W, reset 0x0000.
PAGE 139
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 34: System Handler Priority 3 (SYSPRI3), offset 0xD20 Note: This register can only be accessed from privileged mode. The SYSPRI3 register configures the priority level, 0 to 7 of the SysTick exception and PendSV handlers. This register is byte-accessible. System Handler Priority 3 (SYSPRI3) Base 0xE000.E000 Offset 0xD20 Type R/W, reset 0x0000.
PAGE 140
NRND: Not recommended for new designs. Cortex-M3 Peripherals Register 35: System Handler Control and State (SYSHNDCTRL), offset 0xD24 Note: This register can only be accessed from privileged mode. The SYSHNDCTRL register enables the system handlers, and indicates the pending status of the usage fault, bus fault, memory management fault, and SVC exceptions as well as the active status of the system handlers.
PAGE 141
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset 16 MEM R/W 0 Description Memory Management Fault Enable Value Description 15 SVC R/W 0 0 Disables the memory management fault exception. 1 Enables the memory management fault exception. SVC Call Pending Value Description 0 An SVC call exception is not pending. 1 An SVC call exception is pending. This bit can be modified to change the pending status of the SVC call exception.
PAGE 142
NRND: Not recommended for new designs. Cortex-M3 Peripherals Bit/Field Name Type Reset 10 PNDSV R/W 0 Description PendSV Exception Active Value Description 0 A PendSV exception is not active. 1 A PendSV exception is active. This bit can be modified to change the active status of the PendSV exception, however, see the Caution above before setting this bit. 9 reserved RO 0 Software should not rely on the value of a reserved bit.
PAGE 143
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset 0 MEMA R/W 0 Description Memory Management Fault Active Value Description 0 Memory management fault is not active. 1 Memory management fault is active. This bit can be modified to change the active status of the memory management fault exception, however, see the Caution above before setting this bit.
PAGE 144
NRND: Not recommended for new designs. Cortex-M3 Peripherals Register 36: Configurable Fault Status (FAULTSTAT), offset 0xD28 Note: This register can only be accessed from privileged mode. The FAULTSTAT register indicates the cause of a memory management fault, bus fault, or usage fault.
PAGE 145
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset 25 DIV0 R/W1C 0 Description Divide-by-Zero Usage Fault Value Description 0 No divide-by-zero fault has occurred, or divide-by-zero trapping is not enabled. 1 The processor has executed an SDIV or UDIV instruction with a divisor of 0. When this bit is set, the PC value stacked for the exception return points to the instruction that performed the divide by zero.
PAGE 146
NRND: Not recommended for new designs. Cortex-M3 Peripherals Bit/Field Name Type Reset 17 INVSTAT R/W1C 0 Description Invalid State Usage Fault Value Description 0 A usage fault has not been caused by an invalid state. 1 The processor has attempted to execute an instruction that makes illegal use of the EPSR register.
PAGE 147
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset 12 BSTKE R/W1C 0 Description Stack Bus Fault Value Description 0 No bus fault has occurred on stacking for exception entry. 1 Stacking for an exception entry has caused one or more bus faults. When this bit is set, the SP is still adjusted but the values in the context area on the stack might be incorrect. A fault address is not written to the FAULTADDR register.
PAGE 148
NRND: Not recommended for new designs. Cortex-M3 Peripherals Bit/Field Name Type Reset 8 IBUS R/W1C 0 Description Instruction Bus Error Value Description 0 An instruction bus error has not occurred. 1 An instruction bus error has occurred. The processor detects the instruction bus error on prefetching an instruction, but sets this bit only if it attempts to issue the faulting instruction. When this bit is set, a fault address is not written to the FAULTADDR register.
PAGE 149
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset 3 MUSTKE R/W1C 0 Description Unstack Access Violation Value Description 0 No memory management fault has occurred on unstacking for a return from exception. 1 Unstacking for a return from exception has caused one or more access violations. This fault is chained to the handler. Thus, when this bit is set, the original return stack is still present.
PAGE 150
NRND: Not recommended for new designs. Cortex-M3 Peripherals Register 37: Hard Fault Status (HFAULTSTAT), offset 0xD2C Note: This register can only be accessed from privileged mode. The HFAULTSTAT register gives information about events that activate the hard fault handler. Bits are cleared by writing a 1 to them. Hard Fault Status (HFAULTSTAT) Base 0xE000.E000 Offset 0xD2C Type R/W1C, reset 0x0000.
PAGE 151
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 38: Memory Management Fault Address (MMADDR), offset 0xD34 Note: This register can only be accessed from privileged mode. The MMADDR register contains the address of the location that generated a memory management fault. When an unaligned access faults, the address in the MMADDR register is the actual address that faulted.
PAGE 152
NRND: Not recommended for new designs. Cortex-M3 Peripherals Register 39: Bus Fault Address (FAULTADDR), offset 0xD38 Note: This register can only be accessed from privileged mode. The FAULTADDR register contains the address of the location that generated a bus fault. When an unaligned access faults, the address in the FAULTADDR register is the one requested by the instruction, even if it is not the address of the fault.
PAGE 153
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 40: MPU Type (MPUTYPE), offset 0xD90 Note: This register can only be accessed from privileged mode. The MPUTYPE register indicates whether the MPU is present, and if so, how many regions it supports. MPU Type (MPUTYPE) Base 0xE000.E000 Offset 0xD90 Type RO, reset 0x0000.
PAGE 154
NRND: Not recommended for new designs. Cortex-M3 Peripherals Register 41: MPU Control (MPUCTRL), offset 0xD94 Note: This register can only be accessed from privileged mode. The MPUCTRL register enables the MPU, enables the default memory map background region, and enables use of the MPU when in the hard fault, Non-maskable Interrupt (NMI), and Fault Mask Register (FAULTMASK) escalated handlers.
PAGE 155
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset 2 PRIVDEFEN R/W 0 Description MPU Default Region This bit enables privileged software access to the default memory map. Value Description 0 If the MPU is enabled, this bit disables use of the default memory map. Any memory access to a location not covered by any enabled region causes a fault.
PAGE 156
NRND: Not recommended for new designs. Cortex-M3 Peripherals Register 42: MPU Region Number (MPUNUMBER), offset 0xD98 Note: This register can only be accessed from privileged mode. The MPUNUMBER register selects which memory region is referenced by the MPU Region Base Address (MPUBASE) and MPU Region Attribute and Size (MPUATTR) registers. Normally, the required region number should be written to this register before accessing the MPUBASE or the MPUATTR register.
PAGE 157
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 43: MPU Region Base Address (MPUBASE), offset 0xD9C Register 44: MPU Region Base Address Alias 1 (MPUBASE1), offset 0xDA4 Register 45: MPU Region Base Address Alias 2 (MPUBASE2), offset 0xDAC Register 46: MPU Region Base Address Alias 3 (MPUBASE3), offset 0xDB4 Note: This register can only be accessed from privileged mode.
PAGE 158
NRND: Not recommended for new designs. Cortex-M3 Peripherals Bit/Field Name Type Reset 4 VALID WO 0 Description Region Number Valid Value Description 0 The MPUNUMBER register is not changed and the processor updates the base address for the region specified in the MPUNUMBER register and ignores the value of the REGION field. 1 The MPUNUMBER register is updated with the value of the REGION field and the base address is updated for the region specified in the REGION field.
PAGE 159
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 47: MPU Region Attribute and Size (MPUATTR), offset 0xDA0 Register 48: MPU Region Attribute and Size Alias 1 (MPUATTR1), offset 0xDA8 Register 49: MPU Region Attribute and Size Alias 2 (MPUATTR2), offset 0xDB0 Register 50: MPU Region Attribute and Size Alias 3 (MPUATTR3), offset 0xDB8 Note: This register can only be accessed from privileged mode.
PAGE 160
NRND: Not recommended for new designs. Cortex-M3 Peripherals Bit/Field Name Type Reset Description 31:29 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 28 XN R/W 0 Instruction Access Disable Value Description 0 Instruction fetches are enabled. 1 Instruction fetches are disabled.
PAGE 161
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset 0 ENABLE R/W 0 Description Region Enable Value Description 0 The region is disabled. 1 The region is enabled.
PAGE 162
NRND: Not recommended for new designs. JTAG Interface 4 JTAG Interface The Joint Test Action Group (JTAG) port is an IEEE standard that defines a Test Access Port and Boundary Scan Architecture for digital integrated circuits and provides a standardized serial interface for controlling the associated test logic. The TAP, Instruction Register (IR), and Data Registers (DR) can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing information on the components.
PAGE 163
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 4.1 Block Diagram Figure 4-1. JTAG Module Block Diagram TRST TCK TMS TAP Controller TDI Instruction Register (IR) BYPASS Data Register TDO Boundary Scan Data Register IDCODE Data Register ABORT Data Register DPACC Data Register APACC Data Register Cortex-M3 Debug Port 4.
PAGE 164
NRND: Not recommended for new designs. JTAG Interface Table 4-2. JTAG_SWD_SWO Signals (108BGA) Pin Name Pin Number SWCLK SWDIO a Pin Type Buffer Type Description A9 I TTL JTAG/SWD CLK. B9 I/O TTL JTAG TMS and SWDIO. SWO A10 O TTL JTAG TDO and SWO. TCK A9 I TTL JTAG/SWD CLK. TDI B8 I TTL JTAG TDI. TDO A10 O TTL JTAG TDO and SWO. TMS B9 I/O TTL JTAG TMS and SWDIO. TRST A8 I TTL JTAG TRST. a. The TTL designation indicates the pin has TTL-compatible voltage levels.
PAGE 165
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 4.3.1.1 Test Reset Input (TRST) The TRST pin is an asynchronous active Low input signal for initializing and resetting the JTAG TAP controller and associated JTAG circuitry. When TRST is asserted, the TAP controller resets to the Test-Logic-Reset state and remains there while TRST is asserted. When the TAP controller enters the Test-Logic-Reset state, the JTAG Instruction Register (IR) resets to the default instruction, IDCODE.
PAGE 166
NRND: Not recommended for new designs. JTAG Interface 4.3.1.5 Test Data Output (TDO) The TDO pin provides an output stream of serial information from the IR chain or the DR chains. The value of TDO depends on the current TAP state, the current instruction, and the data in the chain being accessed. In order to save power when the JTAG port is not being used, the TDO pin is placed in an inactive drive state when not actively shifting out data.
PAGE 167
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Figure 4-2. Test Access Port State Machine Test Logic Reset 1 0 Run Test Idle 0 Select DR Scan 1 Select IR Scan 1 0 1 Capture DR 1 Capture IR 0 0 Shift DR Shift IR 0 1 Exit 1 DR Exit 1 IR 1 Pause IR 0 1 Exit 2 DR 0 1 0 Exit 2 IR 1 1 Update DR 4.3.
PAGE 168
NRND: Not recommended for new designs. JTAG Interface 4.3.4.1 GPIO Functionality When the controller is reset with either a POR or RST, the JTAG/SWD port pins default to their JTAG/SWD configurations. The default configuration includes enabling digital functionality (setting GPIODEN to 1), enabling the pull-up resistors (setting GPIOPUR to 1), and enabling the alternate hardware function (setting GPIOAFSEL to 1) for the PB7 and PC[3:0] JTAG/SWD pins.
PAGE 169
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 11. Perform the JTAG-to-SWD switch sequence. 12. Perform the SWD-to-JTAG switch sequence. 13. Release the RST signal. 14. Wait 400 ms. 15. Power-cycle the device. The JTAG-to-SWD and SWD-to-JTAG switch sequences are described in “ARM Serial Wire Debug (SWD)” on page 169.
PAGE 170
NRND: Not recommended for new designs. JTAG Interface 1. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that both JTAG and SWD are in their reset/idle states. 2. Send the 16-bit JTAG-to-SWD switch sequence, 16'hE79E. 3. Send at least 50 TCK/SWCLK cycles with TMS/SWDIO set to 1. This ensures that if SWJ-DP was already in SWD mode, before sending the switch sequence, the SWD goes into the line reset state.
PAGE 171
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 4-4. JTAG Instruction Register Commands 4.5.1.1 IR[3:0] Instruction Description 0000 EXTEST Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD instruction onto the pads. 0001 INTEST Drives the values preloaded into the Boundary Scan Chain by the SAMPLE/PRELOAD instruction into the controller.
PAGE 172
NRND: Not recommended for new designs. JTAG Interface While these samples of the inputs, outputs, and output enables are being shifted out of the Boundary Scan Data Register, new data is being shifted into the Boundary Scan Data Register from TDI. Once the new data has been shifted into the Boundary Scan Data Register, the data is saved in the parallel load registers when the TAP controller enters the Update DR state.
PAGE 173
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 4.5.2 Data Registers The JTAG module contains six Data Registers. These include: IDCODE, BYPASS, Boundary Scan, APACC, DPACC, and ABORT serial Data Register chains. Each of these Data Registers is discussed in the following sections. 4.5.2.1 IDCODE Data Register The format for the 32-bit IDCODE Data Register defined by the IEEE Standard 1149.1 is shown in Figure 4-3 on page 173.
PAGE 174
NRND: Not recommended for new designs. JTAG Interface the EXTEST and INTEST instructions. These instructions either force data out of the controller, with the EXTEST instruction, or into the controller, with the INTEST instruction. Figure 4-5. Boundary Scan Register Format TDI I N O U T O E ... GPIO PB6 4.5.2.4 I N O U T GPIO m O E I N RST I N O U T GPIO m+1 O E ...
PAGE 175
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 5 System Control System control determines the overall operation of the device. It provides information about the device, controls the clocking to the core and individual peripherals, and handles reset detection and reporting. 5.1 Signal Description Table 5-1 on page 175 and Table 5-2 on page 175 list the external signals of the System Control module and describe the function of each.
PAGE 176
NRND: Not recommended for new designs. System Control ■ Local control, such as reset (see “Reset Control” on page 176), power (see “Power Control” on page 180) and clock control (see “Clock Control” on page 181) ■ System control (Run, Sleep, and Deep-Sleep modes); see “System Control” on page 186 5.2.1 Device Identification Several read-only registers provide software with information on the microcontroller, such as version, part number, SRAM size, flash size, and other features.
PAGE 177
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 5.2.2.3 Power-On Reset (POR) Note: The power-on reset also resets the JTAG controller. An external reset does not. The internal Power-On Reset (POR) circuit monitors the power supply voltage (VDD) and generates a reset signal to all of the internal logic including JTAG when the power supply ramp reaches a threshold value (VTH).
PAGE 178
NRND: Not recommended for new designs. System Control To improve noise immunity and/or to delay reset at power up, the RST input may be connected to an RC network as shown in Figure 5-2 on page 178. Figure 5-2. External Circuitry to Extend Power-On Reset VDD Stellaris® RPU RST C1 RPU = 1 kΩ to 100 kΩ C1 = 1 nF to 10 µF If the application requires the use of an external reset switch, Figure 5-3 on page 178 shows the proper circuitry to use. Figure 5-3.
PAGE 179
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller The brown-out reset is equivalent to an assertion of the external RST input and the reset is held active until the proper VDD level is restored. The RESC register can be examined in the reset interrupt handler to determine if a Brown-Out condition was the cause of the reset, thus allowing software to determine what actions are required to recover. The internal Brown-Out Reset timing is shown in Figure 23-7 on page 756. 5.2.2.
PAGE 180
NRND: Not recommended for new designs. System Control 5.2.3 Power Control ® The Stellaris microcontroller provides an integrated LDO regulator that is used to provide power to the majority of the controller's internal logic. For power reduction, the LDO regulator provides software a mechanism to adjust the regulated value, in small increments (VSTEP), over the range of 2.25 V to 2.75 V (inclusive)—or 2.5 V ± 10%.
PAGE 181
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Figure 5-4. Power Architecture VDD VCCPHY GNDPHY VCCPHY Ethernet PHY VCCPHY VCCPHY VDD25 GNDPHY GNDPHY VDD25 VDD25 GNDPHY GND Internal Logic and PLL VDD25 GND GND GND LDO Low-noise LDO +3.3V VDDA VDDA GNDA Analog circuits VDD GND VDD GND VDD I/O Buffers VDD 5.2.4 GNDA GND GND Clock Control System control determines the control of clocks in this part. 5.2.4.
PAGE 182
NRND: Not recommended for new designs. System Control Applications that do not depend on accurate clock sources may use this clock source to reduce system cost. The internal oscillator is the clock source the device uses during and following POR. If the main oscillator is required, software must enable the main oscillator following reset and allow the main oscillator to stabilize before changing the clock reference. ■ Main Oscillator (MOSC).
PAGE 183
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller ■ Clock divisors ■ Crystal input selection Figure 5-5 on page 183 shows the logic for the main clock tree. The peripheral blocks are driven by the system clock signal and can be individually enabled/disabled. The ADC clock signal is automatically divided down to 16 MHz for proper ADC operation. The PWM clock signal is a synchronous divide of the system clock to provide the PWM circuit with more range (set with PWMDIV in RCC).
PAGE 184
NRND: Not recommended for new designs. System Control In the RCC register, the SYSDIV field specifies which divisor is used to generate the system clock from either the PLL output or the oscillator source (depending on how the BYPASS bit in this register is configured). When using the PLL, the VCO frequency of 400 MHz is predivided by 2 before the divisor is applied.
PAGE 185
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 5-6. Examples of Possible System Clock Frequencies Using the SYSDIV2 Field (continued) SYSDIV2 Divisor a Frequency (BYPASS2=0) Frequency (BYPASS2=1) StellarisWare Parameter 0x05 /6 33.33 MHz Clock source frequency/6 SYSCTL_SYSDIV_6 0x06 /7 28.57 MHz Clock source frequency/7 SYSCTL_SYSDIV_7 0x07 /8 25 MHz Clock source frequency/8 SYSCTL_SYSDIV_8 0x08 /9 22.
PAGE 186
NRND: Not recommended for new designs. System Control The modes are programmed using the RCC/RCC2 register fields (see page 198 and page 203). 5.2.4.6 PLL Operation If a PLL configuration is changed, the PLL output frequency is unstable until it reconverges (relocks) to the new setting. The time between the configuration change and relock is TREADY (see Table 23-9 on page 752). During the relock time, the affected PLL is not usable as a clock reference.
PAGE 187
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller a WFI instruction. Any properly configured interrupt event in the system will bring the processor back into Run mode. See “Power Management” on page 93 for more details. The Cortex-M3 processor core and the memory subsystem are not clocked. Peripherals are clocked that are enabled in the DCGCn register when auto-clock gating is enabled (see the RCC register) or the RCGCn register when auto-clock gating is disabled.
PAGE 188
NRND: Not recommended for new designs. System Control 5. Enable use of the PLL by clearing the BYPASS bit in RCC/RCC2. 5.4 Register Map Table 5-7 on page 188 lists the System Control registers, grouped by function. The offset listed is a hexadecimal increment to the register's address, relative to the System Control base address of 0x400F.E000. Note: Spaces in the System Control register space that are not used are reserved for future or internal use.
PAGE 189
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 5-7. System Control Register Map (continued) Name Type Reset 0x120 DCGC0 R/W 0x00000040 Deep Sleep Mode Clock Gating Control Register 0 221 0x124 DCGC1 R/W 0x00000000 Deep Sleep Mode Clock Gating Control Register 1 229 0x128 DCGC2 R/W 0x00000000 Deep Sleep Mode Clock Gating Control Register 2 236 0x144 DSLPCLKCFG R/W 0x0780.0000 Deep Sleep Clock Configuration 205 5.
PAGE 190
NRND: Not recommended for new designs. System Control Register 1: Device Identification 0 (DID0), offset 0x000 This register identifies the version of the microcontroller. Each microcontroller is uniquely identified by the combined values of the CLASS field in the DID0 register and the PARTNO field in the DID1 register. Device Identification 0 (DID0) Base 0x400F.
PAGE 191
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset 15:8 MAJOR RO - Description Major Revision This field specifies the major revision number of the device. The major revision reflects changes to base layers of the design. The major revision number is indicated in the part number as a letter (A for first revision, B for second, and so on).
PAGE 192
NRND: Not recommended for new designs. System Control Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 This register is responsible for controlling reset conditions after initial power-on reset. Brown-Out Reset Control (PBORCTL) Base 0x400F.E000 Offset 0x030 Type R/W, reset 0x0000.
PAGE 193
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 3: LDO Power Control (LDOPCTL), offset 0x034 The VADJ field in this register adjusts the on-chip output voltage (VOUT). LDO Power Control (LDOPCTL) Base 0x400F.E000 Offset 0x034 Type R/W, reset 0x0000.
PAGE 194
NRND: Not recommended for new designs. System Control Register 4: Raw Interrupt Status (RIS), offset 0x050 Central location for system control raw interrupts. These are set and cleared by hardware. Raw Interrupt Status (RIS) Base 0x400F.E000 Offset 0x050 Type RO, reset 0x0000.
PAGE 195
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 5: Interrupt Mask Control (IMC), offset 0x054 Central location for system control interrupt masks. Interrupt Mask Control (IMC) Base 0x400F.E000 Offset 0x054 Type R/W, reset 0x0000.
PAGE 196
NRND: Not recommended for new designs. System Control Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 On a read, this register gives the current masked status value of the corresponding interrupt. All of the bits are R/W1C and this action also clears the corresponding raw interrupt bit in the RIS register (see page 194). Masked Interrupt Status and Clear (MISC) Base 0x400F.E000 Offset 0x058 Type R/W1C, reset 0x0000.
PAGE 197
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 7: Reset Cause (RESC), offset 0x05C This register is set with the reset cause after reset. The bits in this register are sticky and maintain their state across multiple reset sequences, except when an power-on reset is the cause, in which case, all bits other than POR in the RESC register are cleared. Reset Cause (RESC) Base 0x400F.
PAGE 198
NRND: Not recommended for new designs. System Control Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 This register is defined to provide source control and frequency speed. Run-Mode Clock Configuration (RCC) Base 0x400F.E000 Offset 0x060 Type R/W, reset 0x078E.
PAGE 199
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset Description 21 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 20 USEPWMDIV R/W 0 Enable PWM Clock Divisor Use the PWM clock divider as the source for the PWM clock.
PAGE 200
NRND: Not recommended for new designs. System Control Bit/Field Name Type Reset 9:6 XTAL R/W 0xB Description Crystal Value This field specifies the crystal value attached to the main oscillator. The encoding for this field is provided below. Depending on the crystal used, the PLL frequency may not be exactly 400 MHz (see Table 23-10 on page 752 for more information). Value Crystal Frequency (MHz) Not Using the PLL 5:4 OSCSRC R/W 0x1 Crystal Frequency (MHz) Using the PLL 0x0 1.
PAGE 201
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset 0 MOSCDIS R/W 1 Description Main Oscillator Disable 0: Main oscillator is enabled . 1: Main oscillator is disabled (default).
PAGE 202
NRND: Not recommended for new designs. System Control Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 This register provides a means of translating external crystal frequencies into the appropriate PLL settings. This register is initialized during the reset sequence and updated anytime that the XTAL field changes in the Run-Mode Clock Configuration (RCC) register (see page 198).
PAGE 203
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 This register overrides the RCC equivalent register fields, as shown in Table 5-8, when the USERCC2 bit is set, allowing the extended capabilities of the RCC2 register to be used while also providing a means to be backward-compatible to previous parts.
PAGE 204
NRND: Not recommended for new designs. System Control Bit/Field Name Type Reset Description 11 BYPASS2 R/W 1 Bypass PLL When set, bypasses the PLL for the clock source. See Table 5-6 on page 184 for programming guidelines. 10:7 reserved RO 0x0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
PAGE 205
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 This register provides configuration information for the hardware control of Deep Sleep Mode. Deep Sleep Clock Configuration (DSLPCLKCFG) Base 0x400F.E000 Offset 0x144 Type R/W, reset 0x0780.
PAGE 206
NRND: Not recommended for new designs. System Control Register 12: Device Identification 1 (DID1), offset 0x004 This register identifies the device family, part number, temperature range, pin count, and package type. Each microcontroller is uniquely identified by the combined values of the CLASS field in the DID0 register and the PARTNO field in the DID1 register. Device Identification 1 (DID1) Base 0x400F.
PAGE 207
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset Description 12:8 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 7:5 TEMP RO - Temperature Range This field specifies the temperature rating of the device.
PAGE 208
NRND: Not recommended for new designs. System Control Register 13: Device Capabilities 0 (DC0), offset 0x008 This register is predefined by the part and can be used to verify features. Device Capabilities 0 (DC0) Base 0x400F.E000 Offset 0x008 Type RO, reset 0x00FF.
PAGE 209
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 14: Device Capabilities 1 (DC1), offset 0x010 This register provides a list of features available in the system. The Stellaris family uses this register format to indicate the availability of the following family features in the specific device: CANs, PWM, ADC, Watchdog timer, Hibernation module, and debug capabilities. This register also indicates the maximum clock frequency and maximum ADC sample rate.
PAGE 210
NRND: Not recommended for new designs. System Control Bit/Field Name Type Reset 9:8 MAXADCSPD RO 0x2 Description Max ADC Speed Indicates the maximum rate at which the ADC samples data. Value Description 0x2 7 MPU RO 1 500K samples/second MPU Present When set, indicates that the Cortex-M3 Memory Protection Unit (MPU) module is present. See the "Cortex-M3 Peripherals" chapter in the Stellaris Data Sheet for details on the MPU.
PAGE 211
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 15: Device Capabilities 2 (DC2), offset 0x014 This register provides a list of features available in the system. The Stellaris family uses this register format to indicate the availability of the following family features in the specific device: Analog Comparators, General-Purpose Timers, I2Cs, QEIs, SSIs, and UARTs.
PAGE 212
NRND: Not recommended for new designs. System Control Bit/Field Name Type Reset 9 QEI1 RO 1 Description QEI1 Present When set, indicates that QEI module 1 is present. 8 QEI0 RO 1 QEI0 Present When set, indicates that QEI module 0 is present. 7:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
PAGE 213
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 16: Device Capabilities 3 (DC3), offset 0x018 This register provides a list of features available in the system. The Stellaris family uses this register format to indicate the availability of the following family features in the specific device: Analog Comparator I/Os, CCP I/Os, ADC I/Os, and PWM I/Os. Device Capabilities 3 (DC3) Base 0x400F.E000 Offset 0x018 Type RO, reset 0x830F.
PAGE 214
NRND: Not recommended for new designs. System Control Bit/Field Name Type Reset 8 C0O RO 1 Description C0o Pin Present When set, indicates that the analog comparator 0 output pin is present. 7 C0PLUS RO 1 C0+ Pin Present When set, indicates that the analog comparator 0 (+) input pin is present. 6 C0MINUS RO 1 C0- Pin Present When set, indicates that the analog comparator 0 (-) input pin is present. 5 PWM5 RO 1 PWM5 Pin Present When set, indicates that the PWM pin 5 is present.
PAGE 215
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 17: Device Capabilities 4 (DC4), offset 0x01C This register provides a list of features available in the system. The Stellaris family uses this register format to indicate the availability of the following family features in the specific device: Ethernet MAC and PHY, GPIOs, and CCP I/Os.
PAGE 216
NRND: Not recommended for new designs. System Control Bit/Field Name Type Reset 3 GPIOD RO 1 Description GPIO Port D Present When set, indicates that GPIO Port D is present. 2 GPIOC RO 1 GPIO Port C Present When set, indicates that GPIO Port C is present. 1 GPIOB RO 1 GPIO Port B Present When set, indicates that GPIO Port B is present. 0 GPIOA RO 1 GPIO Port A Present When set, indicates that GPIO Port A is present.
PAGE 217
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
PAGE 218
NRND: Not recommended for new designs. System Control Bit/Field Name Type Reset Description 15:10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 9:8 MAXADCSPD R/W 0 ADC Sample Speed This field sets the rate at which the ADC samples data. You cannot set the rate higher than the maximum rate.
PAGE 219
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
PAGE 220
NRND: Not recommended for new designs. System Control Bit/Field Name Type Reset Description 15:10 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 9:8 MAXADCSPD R/W 0 ADC Sample Speed This field sets the rate at which the ADC samples data. You cannot set the rate higher than the maximum rate.
PAGE 221
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
PAGE 222
NRND: Not recommended for new designs. System Control Bit/Field Name Type Reset Description 15:7 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 6 HIB R/W 1 HIB Clock Gating Control This bit controls the clock gating for the Hibernation module. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled.
PAGE 223
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
PAGE 224
NRND: Not recommended for new designs. System Control Bit/Field Name Type Reset 17 TIMER1 R/W 0 Description Timer 1 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault.
PAGE 225
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset 0 UART0 R/W 0 Description UART0 Clock Gating Control This bit controls the clock gating for UART module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault.
PAGE 226
NRND: Not recommended for new designs. System Control Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
PAGE 227
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset 17 TIMER1 R/W 0 Description Timer 1 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault.
PAGE 228
NRND: Not recommended for new designs. System Control Bit/Field Name Type Reset 0 UART0 R/W 0 Description UART0 Clock Gating Control This bit controls the clock gating for UART module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault.
PAGE 229
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
PAGE 230
NRND: Not recommended for new designs. System Control Bit/Field Name Type Reset 17 TIMER1 R/W 0 Description Timer 1 Clock Gating Control This bit controls the clock gating for General-Purpose Timer module 1. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault.
PAGE 231
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset 0 UART0 R/W 0 Description UART0 Clock Gating Control This bit controls the clock gating for UART module 0. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault.
PAGE 232
NRND: Not recommended for new designs. System Control Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
PAGE 233
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset 5 GPIOF R/W 0 Description Port F Clock Gating Control This bit controls the clock gating for Port F. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 GPIOE R/W 0 Port E Clock Gating Control This bit controls the clock gating for Port E.
PAGE 234
NRND: Not recommended for new designs. System Control Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
PAGE 235
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset 5 GPIOF R/W 0 Description Port F Clock Gating Control This bit controls the clock gating for Port F. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 GPIOE R/W 0 Port E Clock Gating Control This bit controls the clock gating for Port E.
PAGE 236
NRND: Not recommended for new designs. System Control Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 This register controls the clock gating logic. Each bit controls a clock enable for a given interface, function, or unit. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled (saving power). If the unit is unclocked, reads or writes to the unit will generate a bus fault.
PAGE 237
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset 5 GPIOF R/W 0 Description Port F Clock Gating Control This bit controls the clock gating for Port F. If set, the unit receives a clock and functions. Otherwise, the unit is unclocked and disabled. If the unit is unclocked, reads or writes to the unit will generate a bus fault. 4 GPIOE R/W 0 Port E Clock Gating Control This bit controls the clock gating for Port E.
PAGE 238
NRND: Not recommended for new designs. System Control Register 27: Software Reset Control 0 (SRCR0), offset 0x040 Writes to this register are masked by the bits in the Device Capabilities 1 (DC1) register. Software Reset Control 0 (SRCR0) Base 0x400F.
PAGE 239
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 28: Software Reset Control 1 (SRCR1), offset 0x044 Writes to this register are masked by the bits in the Device Capabilities 2 (DC2) register. Software Reset Control 1 (SRCR1) Base 0x400F.
PAGE 240
NRND: Not recommended for new designs. System Control Bit/Field Name Type Reset 8 QEI0 R/W 0 Description QEI0 Reset Control Reset control for QEI unit 0. 7:5 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 4 SSI0 R/W 0 SSI0 Reset Control Reset control for SSI unit 0.
PAGE 241
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 29: Software Reset Control 2 (SRCR2), offset 0x048 Writes to this register are masked by the bits in the Device Capabilities 4 (DC4) register. Software Reset Control 2 (SRCR2) Base 0x400F.
PAGE 242
NRND: Not recommended for new designs. Hibernation Module 6 Hibernation Module The Hibernation Module manages removal and restoration of power to provide a means for reducing power consumption. When the processor and peripherals are idle, power can be completely removed with only the Hibernation module remaining powered. Power can be restored based on an external signal, or at a certain time using the built-in Real-Time Clock (RTC).
PAGE 243
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 6.1 Block Diagram Figure 6-1. Hibernation Module Block Diagram HIBCTL.CLK32EN 32.768 kHz XOSC0 Pre-Divider 4.194304 MHz XOSC1 Interrupts HIBIM HIBRIS HIBMIS HIBIC HIBRTCT /128 HIBCTL.CLKSEL Non-Volatile Memory 64 words HIBDATA RTC HIBRTCC HIBRTCLD HIBRTCM0 HIBRTCM1 MATCH0/1 WAKE LOWBAT VDD Low Battery Detect VBAT HIBCTL.LOWBATEN 6.2 Interrupts to CPU Power Sequence Logic HIB HIBCTL.PWRCUT HIBCTL.
PAGE 244
NRND: Not recommended for new designs. Hibernation Module Table 6-2. Hibernate Signals (108BGA) a Pin Name Pin Number Pin Type Buffer Type Description HIB M12 O OD An open-drain output with internal pull-up that indicates the processor is in Hibernate mode. VBAT L12 - Power Power source for the Hibernation module. It is normally connected to the positive terminal of a battery and serves as the battery backup/Hibernation module power-source supply.
PAGE 245
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 6.3.2 Clock Source The Hibernation module must be clocked by an external source, even if the RTC feature is not used. An external oscillator or crystal can be used for this purpose. To use a crystal, a 4.194304-MHz crystal is connected to the XOSC0 and XOSC1 pins. This clock signal is divided by 128 internally to produce the 32.768-kHz clock reference. For an alternate clock source, a 32.
PAGE 246
NRND: Not recommended for new designs. Hibernation Module Figure 6-3. Clock Source Using Dedicated Oscillator Stellaris Microcontroller Regulator or Switch Input Voltage IN OUT VDD EN Clock Source XOSC0 (fEXT_OSC) N.C. XOSC1 HIB WAKE RPU Open drain external wake up circuit Note: 6.3.3 VBAT GND 3V Battery RPU = Pull-up resistor (1 M½). Battery Management The Hibernation module can be independently powered by a battery or an auxiliary power source.
PAGE 247
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller The Hibernation module includes two 32-bit match registers that are compared to the value of the RTC counter. The match registers can be used to wake the processor from hibernation mode, or to generate an interrupt to the processor if it is not in hibernation. The RTC must be enabled with the RTCEN bit of the HIBCTL register. The value of the RTC can be set at any time by writing to the HIBRTCLD register.
PAGE 248
NRND: Not recommended for new designs. Hibernation Module 6.3.8 Interrupts and Status The Hibernation module can generate interrupts when the following conditions occur: ■ Assertion of WAKE pin ■ RTC match ■ Low battery detected All of the interrupts are ORed together before being sent to the interrupt controller, so the Hibernate module can only generate a single interrupt request to the controller at any given time.
PAGE 249
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 1. Write the required RTC match value to one of the HIBRTCMn registers at offset 0x004 or 0x008. 2. Write the required RTC load value to the HIBRTCLD register at offset 0x00C. 3. Set the required RTC match interrupt mask in the RTCALT0 and RTCALT1 bits (bits 1:0) in the HIBIM register at offset 0x014. 4. Write 0x0000.0041 to the HIBCTL register at offset 0x010 to enable the RTC to begin counting. 6.4.
PAGE 250
NRND: Not recommended for new designs. Hibernation Module 2. A cold POR, when both the VDD and VBAT supplies are removed. Any other reset condition is ignored by the Hibernation module. Table 6-3. Hibernation Module Register Map Offset Name 0x000 Reset HIBRTCC RO 0x0000.0000 Hibernation RTC Counter 251 0x004 HIBRTCM0 R/W 0xFFFF.FFFF Hibernation RTC Match 0 252 0x008 HIBRTCM1 R/W 0xFFFF.FFFF Hibernation RTC Match 1 253 0x00C HIBRTCLD R/W 0xFFFF.
PAGE 251
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 This register is the current 32-bit value of the RTC counter. Hibernation RTC Counter (HIBRTCC) Base 0x400F.C000 Offset 0x000 Type RO, reset 0x0000.
PAGE 252
NRND: Not recommended for new designs. Hibernation Module Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 This register is the 32-bit match 0 register for the RTC counter. Hibernation RTC Match 0 (HIBRTCM0) Base 0x400F.C000 Offset 0x004 Type R/W, reset 0xFFFF.
PAGE 253
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 This register is the 32-bit match 1 register for the RTC counter. Hibernation RTC Match 1 (HIBRTCM1) Base 0x400F.C000 Offset 0x008 Type R/W, reset 0xFFFF.
PAGE 254
NRND: Not recommended for new designs. Hibernation Module Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C This register is the 32-bit value loaded into the RTC counter. Hibernation RTC Load (HIBRTCLD) Base 0x400F.C000 Offset 0x00C Type R/W, reset 0xFFFF.
PAGE 255
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 5: Hibernation Control (HIBCTL), offset 0x010 This register is the control register for the Hibernation module. Hibernation Control (HIBCTL) Base 0x400F.C000 Offset 0x010 Type R/W, reset 0x8000.
PAGE 256
NRND: Not recommended for new designs. Hibernation Module Bit/Field Name Type Reset 3 RTCWEN R/W 0 Description RTC Wake-up Enable Value Description 0 Disabled 1 Enabled When set, an RTC match event (RTCM0 or RTCM1) will re-power the device based on the RTC counter value matching the corresponding match register 0 or 1. 2 CLKSEL R/W 0 Hibernation Module Clock Select Value 1 HIBREQ R/W 0 Description 0 Use Divide by 128 output. Use this value for a 4.194304-MHz crystal.
PAGE 257
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 This register is the interrupt mask register for the Hibernation module interrupt sources. Hibernation Interrupt Mask (HIBIM) Base 0x400F.C000 Offset 0x014 Type R/W, reset 0x0000.
PAGE 258
NRND: Not recommended for new designs. Hibernation Module Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 This register is the raw interrupt status for the Hibernation module interrupt sources. Hibernation Raw Interrupt Status (HIBRIS) Base 0x400F.C000 Offset 0x018 Type RO, reset 0x0000.
PAGE 259
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C This register is the masked interrupt status for the Hibernation module interrupt sources. Hibernation Masked Interrupt Status (HIBMIS) Base 0x400F.C000 Offset 0x01C Type RO, reset 0x0000.
PAGE 260
NRND: Not recommended for new designs. Hibernation Module Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 This register is the interrupt write-one-to-clear register for the Hibernation module interrupt sources. Hibernation Interrupt Clear (HIBIC) Base 0x400F.C000 Offset 0x020 Type R/W1C, reset 0x0000.
PAGE 261
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 This register contains the value that is used to trim the RTC clock predivider. It represents the computed underflow value that is used during the trim cycle. It is represented as 0x7FFF ± N clock cycles. Hibernation RTC Trim (HIBRTCT) Base 0x400F.C000 Offset 0x024 Type R/W, reset 0x0000.
PAGE 262
NRND: Not recommended for new designs. Hibernation Module Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C This address space is implemented as a 64x32-bit memory (256 bytes). It can be loaded by the system processor in order to store state information and does not lose power during a power-cut operation as long as a battery is present. Hibernation Data (HIBDATA) Base 0x400F.
PAGE 263
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 7 Internal Memory The LM3S8962 microcontroller comes with 64 KB of bit-banded SRAM and 256 KB of flash memory. The flash controller provides a user-friendly interface, making flash programming a simple task. Flash protection can be applied to the flash memory on a 2-KB block basis. 7.1 Block Diagram Figure 7-1 on page 263 illustrates the Flash functions.
PAGE 264
NRND: Not recommended for new designs. Internal Memory 0x2200.0000 + (0x1000 * 32) + (3 * 4) = 0x2202.000C With the alias address calculated, an instruction performing a read/write to address 0x2202.000C allows direct access to only bit 3 of the byte at address 0x2000.1000. For details about bit-banding, see “Bit-Banding” on page 79. 7.2.2 Flash Memory The flash is organized as a set of 1-KB blocks that can be individually erased.
PAGE 265
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 7-1. Flash Protection Policy Combinations (continued) FMPPEn FMPREn Protection 1 0 The block may be written, erased or executed, but not read. This combination is unlikely to be used. 0 1 Read-only protection. The block may be read or executed but may not be written or erased. This mode is used to lock the block from further modification while allowing any read or execute access. 1 1 No protection.
PAGE 266
NRND: Not recommended for new designs. Internal Memory 7.3.1.1 To program a 32-bit word 1. Write source data to the FMD register. 2. Write the target address to the FMA register. 3. Write the flash write key and the WRITE bit (a value of 0xA442.0001) to the FMC register. 4. Poll the FMC register until the WRITE bit is cleared. 7.3.1.2 To perform an erase of a 1-KB page 1. Write the page address to the FMA register. 2. Write the flash write key and the ERASE bit (a value of 0xA442.
PAGE 267
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 7-2. User-Programmable Flash Memory Resident Registers Register to be Committed 7.4 FMA Value Data Source FMPRE0 0x0000.0000 FMPRE0 FMPRE1 0x0000.0002 FMPRE1 FMPRE2 0x0000.0004 FMPRE2 FMPRE3 0x0000.0006 FMPRE3 FMPPE0 0x0000.0001 FMPPE0 FMPPE1 0x0000.0003 FMPPE1 FMPPE2 0x0000.0005 FMPPE2 FMPPE3 0x0000.0007 FMPPE3 USER_REG0 0x8000.0000 USER_REG0 USER_REG1 0x8000.
PAGE 268
NRND: Not recommended for new designs. Internal Memory Table 7-3. Flash Register Map (continued) Name Type Reset 0x1E4 USER_REG1 R/W 0xFFFF.FFFF User Register 1 282 0x204 FMPRE1 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 1 283 0x208 FMPRE2 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 2 284 0x20C FMPRE3 R/W 0xFFFF.FFFF Flash Memory Protection Read Enable 3 285 0x404 FMPPE1 R/W 0xFFFF.
PAGE 269
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 1: Flash Memory Address (FMA), offset 0x000 During a write operation, this register contains a 4-byte-aligned address and specifies where the data is written. During erase operations, this register contains a 1 KB-aligned address and specifies which page is erased. Note that the alignment requirements must be met by software or the results of the operation are unpredictable. Flash Memory Address (FMA) Base 0x400F.
PAGE 270
NRND: Not recommended for new designs. Internal Memory Register 2: Flash Memory Data (FMD), offset 0x004 This register contains the data to be written during the programming cycle or read during the read cycle. Note that the contents of this register are undefined for a read access of an execute-only block. This register is not used during the erase cycles. Flash Memory Data (FMD) Base 0x400F.D000 Offset 0x004 Type R/W, reset 0x0000.
PAGE 271
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 3: Flash Memory Control (FMC), offset 0x008 When this register is written, the flash controller initiates the appropriate access cycle for the location specified by the Flash Memory Address (FMA) register (see page 269). If the access is a write access, the data contained in the Flash Memory Data (FMD) register (see page 270) is written. This is the final register written and initiates the memory operation.
PAGE 272
NRND: Not recommended for new designs. Internal Memory Bit/Field Name Type Reset 1 ERASE R/W 0 Description Erase a Page of Flash Memory If this bit is set, the page of flash main memory as specified by the contents of FMA is erased. A write of 0 has no effect on the state of this bit. If read, the state of the previous erase access is provided. If the previous erase access is complete, a 0 is returned; otherwise, if the previous erase access is not complete, a 1 is returned.
PAGE 273
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C This register indicates that the flash controller has an interrupt condition. An interrupt is only signaled if the corresponding FCIM register bit is set. Flash Controller Raw Interrupt Status (FCRIS) Base 0x400F.D000 Offset 0x00C Type RO, reset 0x0000.
PAGE 274
NRND: Not recommended for new designs. Internal Memory Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 This register controls whether the flash controller generates interrupts to the controller. Flash Controller Interrupt Mask (FCIM) Base 0x400F.D000 Offset 0x010 Type R/W, reset 0x0000.
PAGE 275
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 This register provides two functions. First, it reports the cause of an interrupt by indicating which interrupt source or sources are signalling the interrupt. Second, it serves as the method to clear the interrupt reporting. Flash Controller Masked Interrupt Status and Clear (FCMISC) Base 0x400F.D000 Offset 0x014 Type R/W1C, reset 0x0000.
PAGE 276
NRND: Not recommended for new designs. Internal Memory 7.6 Flash Register Descriptions (System Control Offset) The remainder of this section lists and describes the Flash Memory registers, in numerical order by address offset. Registers in this section are relative to the System Control base address of 0x400F.E000.
PAGE 277
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 7: USec Reload (USECRL), offset 0x140 Note: Offset is relative to System Control base address of 0x400F.E000 This register is provided as a means of creating a 1-μs tick divider reload value for the flash controller. The internal flash has specific minimum and maximum requirements on the length of time the high voltage write pulse can be applied.
PAGE 278
NRND: Not recommended for new designs. Internal Memory Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 Note: This register is aliased for backwards compatability. Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register.
PAGE 279
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 Note: This register is aliased for backwards compatability. Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register.
PAGE 280
NRND: Not recommended for new designs. Internal Memory Register 10: User Debug (USER_DBG), offset 0x1D0 Note: Offset is relative to System Control base address of 0x400FE000. This register provides a write-once mechanism to disable external debugger access to the device in addition to 27 additional bits of user-defined data. The DBG0 bit (bit 0) is set to 0 from the factory and the DBG1 bit (bit 1) is set to 1, which enables external debuggers.
PAGE 281
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 11: User Register 0 (USER_REG0), offset 0x1E0 Note: Offset is relative to System Control base address of 0x400FE000. This register provides 31 bits of user-defined data that is non-volatile and can only be committed once. Bit 31 indicates that the register is available to be committed and is controlled through hardware to ensure that the register is only committed once.
PAGE 282
NRND: Not recommended for new designs. Internal Memory Register 12: User Register 1 (USER_REG1), offset 0x1E4 Note: Offset is relative to System Control base address of 0x400FE000. This register provides 31 bits of user-defined data that is non-volatile and can only be committed once. Bit 31 indicates that the register is available to be committed and is controlled through hardware to ensure that the register is only committed once. Prior to being committed, bits can only be changed from 1 to 0.
PAGE 283
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPREn registers (if any) provide protection for other 64K blocks.
PAGE 284
NRND: Not recommended for new designs. Internal Memory Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks.
PAGE 285
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C Note: Offset is relative to System Control base address of 0x400FE000. This register stores the read-only protection bits for each 2-KB flash block (FMPPEn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks.
PAGE 286
NRND: Not recommended for new designs. Internal Memory Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). Flash memory up to a total of 64 KB is controlled by this register. Other FMPPEn registers (if any) provide protection for other 64K blocks.
PAGE 287
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks.
PAGE 288
NRND: Not recommended for new designs. Internal Memory Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C Note: Offset is relative to System Control base address of 0x400FE000. This register stores the execute-only protection bits for each 2-KB flash block (FMPREn stores the execute-only bits). This register is loaded during the power-on reset sequence. The factory settings for the FMPREn and FMPPEn registers are a value of 1 for all implemented banks.
PAGE 289
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 8 General-Purpose Input/Outputs (GPIOs) The GPIO module is composed of seven physical GPIO blocks, each corresponding to an individual GPIO port (Port A, Port B, Port C, Port D, Port E, Port F, Port G). The GPIO module supports 5-42 programmable input/output pins, depending on the peripherals being used.
PAGE 290
NRND: Not recommended for new designs. General-Purpose Input/Outputs (GPIOs) Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPDR=0, GPIOPUR=0, and GPIOPCTL=0, with the exception of the four JTAG/SWD pins (shown in the table below). A Power-On-Reset (POR) or asserting RST puts the pins back to their default state. Table 8-1.
PAGE 291
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 8-2. GPIO Pins and Alternate Functions (100LQFP) (continued) IO Pin Number Multiplexed Function PD5 96 PD6 99 Fault PD7 100 IDX0 PE0 72 PWM4 PE1 73 PWM5 PE2 74 PhB1 PE3 75 PhA1 PF0 47 PWM0 PF1 61 IDX1 PF2 60 LED1 PF3 59 LED0 PG0 19 PG1 18 Multiplexed Function PWM1 Table 8-3.
PAGE 292
NRND: Not recommended for new designs. General-Purpose Input/Outputs (GPIOs) Table 8-3. GPIO Pins and Alternate Functions (108BGA) (continued) IO Pin Number Multiplexed Function PD1 G2 CAN0Tx PD2 H2 U1Rx PD3 H1 U1Tx PD4 E1 CCP0 PD5 E2 PD6 F2 Fault PD7 F1 IDX0 PE0 A11 PWM4 PE1 B12 PWM5 PE2 B11 PhB1 PE3 A12 PhA1 PF0 M9 PWM0 PF1 H12 IDX1 PF2 J11 LED1 PF3 J12 LED0 PG0 K1 PG1 K2 Multiplexed Function PWM1 Table 8-4.
PAGE 293
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 8-4. GPIO Signals (100LQFP) (continued) a Pin Name Pin Number Pin Type Buffer Type Description PC5 24 I/O TTL GPIO port C bit 5. PC6 23 I/O TTL GPIO port C bit 6. PC7 22 I/O TTL GPIO port C bit 7. PD0 10 I/O TTL GPIO port D bit 0. PD1 11 I/O TTL GPIO port D bit 1. PD2 12 I/O TTL GPIO port D bit 2. PD3 13 I/O TTL GPIO port D bit 3. PD4 95 I/O TTL GPIO port D bit 4.
PAGE 294
NRND: Not recommended for new designs. General-Purpose Input/Outputs (GPIOs) Table 8-5. GPIO Signals (108BGA) (continued) a Pin Name Pin Number Pin Type Buffer Type Description PC0 A9 I/O TTL GPIO port C bit 0. PC1 B9 I/O TTL GPIO port C bit 1. PC2 B8 I/O TTL GPIO port C bit 2. PC3 A10 I/O TTL GPIO port C bit 3. PC4 L1 I/O TTL GPIO port C bit 4. PC5 M1 I/O TTL GPIO port C bit 5. PC6 M2 I/O TTL GPIO port C bit 6. PC7 L2 I/O TTL GPIO port C bit 7.
PAGE 295
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Figure 8-1.
PAGE 296
NRND: Not recommended for new designs. General-Purpose Input/Outputs (GPIOs) During a write, if the address bit associated with that data bit is set to 1, the value of the GPIODATA register is altered. If it is cleared to 0, it is left unchanged. For example, writing a value of 0xEB to the address GPIODATA + 0x098 would yield as shown in Figure 8-2 on page 296, where u is data unchanged by the write. Figure 8-2.
PAGE 297
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller conditions that are allowed to be passed to the controller. The GPIORIS register indicates that a GPIO pin meets the conditions for an interrupt, but has not necessarily been sent to the controller. In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC.
PAGE 298
NRND: Not recommended for new designs. General-Purpose Input/Outputs (GPIOs) 8.2.6 Identification The identification registers configured at reset allow software to detect and identify the module as a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as well as the GPIOPCellID0-GPIOPCellID3 registers. 8.
PAGE 299
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 8-7. GPIO Interrupt Configuration Example (continued) Register GPIOIBE a Desired Interrupt Event Trigger Pin 2 Bit Value 7 0=single edge 6 5 4 3 2 1 0 X X X X X 0 X X X X X X X 1 X X 0 0 0 0 0 1 0 0 1=both edges GPIOIEV 0=Low level, or negative edge 1=High level, or positive edge GPIOIM 0=masked 1=not masked a. X=Ignored (don’t care bit) 8.
PAGE 300
NRND: Not recommended for new designs. General-Purpose Input/Outputs (GPIOs) The default reset value for the GPIOCR register is 0x0000.00FF for all GPIO pins, with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). To ensure that the JTAG port is not accidentally programmed as a GPIO, these five pins default to non-committable. Because of this, the default reset value of GPIOCR for GPIO Port B is 0x0000.007F while the default reset value of GPIOCR for Port C is 0x0000.00F0. Table 8-8.
PAGE 301
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 8-8. GPIO Register Map (continued) Offset Name 0xFF0 Reset GPIOPCellID0 RO 0x0000.000D GPIO PrimeCell Identification 0 332 0xFF4 GPIOPCellID1 RO 0x0000.00F0 GPIO PrimeCell Identification 1 333 0xFF8 GPIOPCellID2 RO 0x0000.0005 GPIO PrimeCell Identification 2 334 0xFFC GPIOPCellID3 RO 0x0000.00B1 GPIO PrimeCell Identification 3 335 8.
PAGE 302
NRND: Not recommended for new designs. General-Purpose Input/Outputs (GPIOs) Register 1: GPIO Data (GPIODATA), offset 0x000 The GPIODATA register is the data register. In software control mode, values written in the GPIODATA register are transferred onto the GPIO port pins if the respective pins have been configured as outputs through the GPIO Direction (GPIODIR) register (see page 303).
PAGE 303
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 2: GPIO Direction (GPIODIR), offset 0x400 The GPIODIR register is the data direction register. Bits set to 1 in the GPIODIR register configure the corresponding pin to be an output, while bits set to 0 configure the pins to be inputs. All bits are cleared by a reset, meaning all GPIO pins are inputs by default. GPIO Direction (GPIODIR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.
PAGE 304
NRND: Not recommended for new designs. General-Purpose Input/Outputs (GPIOs) Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 The GPIOIS register is the interrupt sense register. Bits set to 1 in GPIOIS configure the corresponding pins to detect levels, while bits set to 0 configure the pins to detect edges. All bits are cleared by a reset. GPIO Interrupt Sense (GPIOIS) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.
PAGE 305
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 The GPIOIBE register is the interrupt both-edges register. When the corresponding bit in the GPIO Interrupt Sense (GPIOIS) register (see page 304) is set to detect edges, bits set to High in GPIOIBE configure the corresponding pin to detect both rising and falling edges, regardless of the corresponding bit in the GPIO Interrupt Event (GPIOIEV) register (see page 306).
PAGE 306
NRND: Not recommended for new designs. General-Purpose Input/Outputs (GPIOs) Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C The GPIOIEV register is the interrupt event register. Bits set to High in GPIOIEV configure the corresponding pin to detect rising edges or high levels, depending on the corresponding bit value in the GPIO Interrupt Sense (GPIOIS) register (see page 304).
PAGE 307
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 The GPIOIM register is the interrupt mask register. Bits set to High in GPIOIM allow the corresponding pins to trigger their individual interrupts and the combined GPIOINTR line. Clearing a bit disables interrupt triggering on that pin. All bits are cleared by a reset. GPIO Interrupt Mask (GPIOIM) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.
PAGE 308
NRND: Not recommended for new designs. General-Purpose Input/Outputs (GPIOs) Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 The GPIORIS register is the raw interrupt status register. Bits read High in GPIORIS reflect the status of interrupt trigger conditions detected (raw, prior to masking), indicating that all the requirements have been met, before they are finally allowed to trigger by the GPIO Interrupt Mask (GPIOIM) register (see page 307).
PAGE 309
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 The GPIOMIS register is the masked interrupt status register. Bits read High in GPIOMIS reflect the status of input lines triggering an interrupt. Bits read as Low indicate that either no interrupt has been generated, or the interrupt is masked. In addition to providing GPIO functionality, PB4 can also be used as an external trigger for the ADC.
PAGE 310
NRND: Not recommended for new designs. General-Purpose Input/Outputs (GPIOs) Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C The GPIOICR register is the interrupt clear register. Writing a 1 to a bit in this register clears the corresponding interrupt edge detection logic register. Writing a 0 has no effect. GPIO Interrupt Clear (GPIOICR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.
PAGE 311
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 The GPIOAFSEL register is the mode control select register. Writing a 1 to any bit in this register selects the hardware control for the corresponding GPIO line. All bits are cleared by a reset, therefore no GPIO line is set to hardware control by default.
PAGE 312
NRND: Not recommended for new designs. General-Purpose Input/Outputs (GPIOs) Bit/Field Name Type Reset 7:0 AFSEL R/W - Description GPIO Alternate Function Select The AFSEL values are defined as follows: Value Description 0 Software control of corresponding GPIO line (GPIO mode). 1 Hardware control of corresponding GPIO line (alternate hardware function). Note: The default reset value for the GPIOAFSEL, GPIOPUR, and GPIODEN registers are 0x0000.
PAGE 313
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 The GPIODR2R register is the 2-mA drive control register. It allows for each GPIO signal in the port to be individually configured without affecting the other pads. When writing a DRV2 bit for a GPIO signal, the corresponding DRV4 bit in the GPIODR4R register and the DRV8 bit in the GPIODR8R register are automatically cleared by hardware.
PAGE 314
NRND: Not recommended for new designs. General-Purpose Input/Outputs (GPIOs) Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 The GPIODR4R register is the 4-mA drive control register. It allows for each GPIO signal in the port to be individually configured without affecting the other pads. When writing the DRV4 bit for a GPIO signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV8 bit in the GPIODR8R register are automatically cleared by hardware.
PAGE 315
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 The GPIODR8R register is the 8-mA drive control register. It allows for each GPIO signal in the port to be individually configured without affecting the other pads. When writing the DRV8 bit for a GPIO signal, the corresponding DRV2 bit in the GPIODR2R register and the DRV4 bit in the GPIODR4R register are automatically cleared by hardware.
PAGE 316
NRND: Not recommended for new designs. General-Purpose Input/Outputs (GPIOs) Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C The GPIOODR register is the open drain control register. Setting a bit in this register enables the open drain configuration of the corresponding GPIO pad. When open drain mode is enabled, the corresponding bit should also be set in the GPIO Digital Enable (GPIODEN) register (see page 320).
PAGE 317
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 The GPIOPUR register is the pull-up control register. When a bit is set to 1, it enables a weak pull-up resistor on the corresponding GPIO signal. Setting a bit in GPIOPUR automatically clears the corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register (see page 318). GPIO Pull-Up Select (GPIOPUR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.
PAGE 318
NRND: Not recommended for new designs. General-Purpose Input/Outputs (GPIOs) Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 The GPIOPDR register is the pull-down control register. When a bit is set to 1, it enables a weak pull-down resistor on the corresponding GPIO signal. Setting a bit in GPIOPDR automatically clears the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register (see page 317). GPIO Pull-Down Select (GPIOPDR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.
PAGE 319
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 The GPIOSLR register is the slew rate control register. Slew rate control is only available when using the 8-mA drive strength option via the GPIO 8-mA Drive Select (GPIODR8R) register (see page 315). GPIO Slew Rate Control Select (GPIOSLR) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.
PAGE 320
NRND: Not recommended for new designs. General-Purpose Input/Outputs (GPIOs) Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C Note: Pins configured as digital inputs are Schmitt-triggered. The GPIODEN register is the digital enable register. By default, with the exception of the GPIO signals used for JTAG/SWD function, all other GPIO signals are configured out of reset to be undriven (tristate).
PAGE 321
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 19: GPIO Lock (GPIOLOCK), offset 0x520 The GPIOLOCK register enables write access to the GPIOCR register (see page 322). Writing 0x1ACC.E551 to the GPIOLOCK register will unlock the GPIOCR register. Writing any other value to the GPIOLOCK register re-enables the locked state. Reading the GPIOLOCK register returns the lock status rather than the 32-bit value that was previously written.
PAGE 322
NRND: Not recommended for new designs. General-Purpose Input/Outputs (GPIOs) Register 20: GPIO Commit (GPIOCR), offset 0x524 The GPIOCR register is the commit register. The value of the GPIOCR register determines which bits of the GPIOAFSEL register are committed when a write to the GPIOAFSEL register is performed. If a bit in the GPIOCR register is a zero, the data being written to the corresponding bit in the GPIOAFSEL register will not be committed and will retain its previous value.
PAGE 323
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset 7:0 CR - - Description GPIO Commit On a bit-wise basis, any bit set allows the corresponding GPIOAFSEL bit to be set to its alternate function. Note: The default register type for the GPIOCR register is RO for all GPIO pins with the exception of the five JTAG/SWD pins (PB7 and PC[3:0]). These five pins are currently the only GPIOs that are protected by the GPIOCR register.
PAGE 324
NRND: Not recommended for new designs. General-Purpose Input/Outputs (GPIOs) Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 4 (GPIOPeriphID4) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.
PAGE 325
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 5 (GPIOPeriphID5) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.
PAGE 326
NRND: Not recommended for new designs. General-Purpose Input/Outputs (GPIOs) Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 6 (GPIOPeriphID6) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.
PAGE 327
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC The GPIOPeriphID4, GPIOPeriphID5, GPIOPeriphID6, and GPIOPeriphID7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 7 (GPIOPeriphID7) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.
PAGE 328
NRND: Not recommended for new designs. General-Purpose Input/Outputs (GPIOs) Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 0 (GPIOPeriphID0) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.
PAGE 329
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 1 (GPIOPeriphID1) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.
PAGE 330
NRND: Not recommended for new designs. General-Purpose Input/Outputs (GPIOs) Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 2 (GPIOPeriphID2) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.
PAGE 331
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC The GPIOPeriphID0, GPIOPeriphID1, GPIOPeriphID2, and GPIOPeriphID3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register, used by software to identify the peripheral. GPIO Peripheral Identification 3 (GPIOPeriphID3) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.
PAGE 332
NRND: Not recommended for new designs. General-Purpose Input/Outputs (GPIOs) Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 0 (GPIOPCellID0) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.
PAGE 333
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 1 (GPIOPCellID1) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.
PAGE 334
NRND: Not recommended for new designs. General-Purpose Input/Outputs (GPIOs) Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 2 (GPIOPCellID2) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.
PAGE 335
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC The GPIOPCellID0, GPIOPCellID1, GPIOPCellID2, and GPIOPCellID3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register. The register is used as a standard cross-peripheral identification system. GPIO PrimeCell Identification 3 (GPIOPCellID3) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.
PAGE 336
NRND: Not recommended for new designs. General-Purpose Timers 9 General-Purpose Timers Programmable timers can be used to count or time external events that drive the Timer input pins. ® The Stellaris General-Purpose Timer Module (GPTM) contains four GPTM blocks (Timer0, Timer1, Timer 2, and Timer 3).
PAGE 337
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller – Input edge time capture ■ 16-bit PWM mode – Simple PWM mode with software-programmable output inversion of the PWM signal 9.1 Block Diagram Note: In Figure 9-1 on page 337, the specific CCP pins available depend on the Stellaris device. See Table 9-1 on page 337 for the available CCPs. Figure 9-1.
PAGE 338
NRND: Not recommended for new designs. General-Purpose Timers 9.2 Signal Description Table 9-2 on page 338 and Table 9-3 on page 338 list the external signals of the GP Timer module and describe the function of each. The GP Timer signals are alternate functions for some GPIO signals and default to be GPIO signals at reset. The column in the table below titled "Pin Assignment" lists the possible GPIO pin placements for these GP Timer signals.
PAGE 339
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller The GPTM is placed into 32-bit mode by writing a 0 (One-Shot/Periodic 32-bit timer mode) or a 1 (RTC mode) to the GPTM Configuration (GPTMCFG) register. In both configurations, certain GPTM registers are concatenated to form pseudo 32-bit registers.
PAGE 340
NRND: Not recommended for new designs. General-Purpose Timers When software writes the TAEN bit inthe GPTMCTL register, the counter starts counting up from its preloaded value of 0x0000.0001. When the current count value matches the preloaded value in the GPTMTAMATCHR register, it rolls over to a value of 0x0000.0000 and continues counting until either a hardware reset, or it is disabled by software (clearing the TAEN bit). When a match occurs, the GPTM asserts the RTCRIS bit in GPTMRIS.
PAGE 341
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 9-4. 16-Bit Timer With Prescaler Configurations (continued) a Prescale #Clock (T c) Max Time Units 11111110 255 334.2336 mS 11111111 256 335.5443 mS a. Tc is the clock period. 9.3.3.2 16-Bit Input Edge Count Mode Note: For rising-edge detection, the input signal must be High for at least two system clock periods following the rising edge.
PAGE 342
NRND: Not recommended for new designs. General-Purpose Timers Figure 9-2. 16-Bit Input Edge Count Mode Example Timer stops, flags asserted Count Timer reload on next cycle Ignored Ignored 0x000A 0x0009 0x0008 0x0007 0x0006 Input Signal 9.3.3.3 16-Bit Input Edge Time Mode Note: For rising-edge detection, the input signal must be High for at least two system clock periods following the rising edge.
PAGE 343
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Figure 9-3. 16-Bit Input Edge Time Mode Example Count 0xFFFF GPTMTnR=X GPTMTnR=Y GPTMTnR=Z Z X Y Time Input Signal 9.3.3.4 16-Bit PWM Mode Note: The prescaler is not available in 16-Bit PWM mode. The GPTM supports a simple PWM generation mode. In PWM mode, the timer is configured as a down-counter with a start value (and thus period) defined by GPTMTnILR.
PAGE 344
NRND: Not recommended for new designs. General-Purpose Timers Figure 9-4. 16-Bit PWM Mode Example Count GPTMTnR=GPTMnMR GPTMTnR=GPTMnMR 0xC350 0x411A Time TnEN set TnPWML = 0 Output Signal TnPWML = 1 9.4 Initialization and Configuration To use the general-purpose timers, the peripheral clock must be enabled by setting the TIMER0, TIMER1, TIMER2, and TIMER3 bits in the RCGC1 register. This section shows module initialization and configuration examples for each of the supported timer modes. 9.4.
PAGE 345
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 7. Poll the TATORIS bit in the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the TATOCINT bit of the GPTM Interrupt Clear Register (GPTMICR). In One-Shot mode, the timer stops counting after step 7 on page 345. To re-enable the timer, repeat the sequence. A timer configured in Periodic mode does not stop counting after it times out. 9.4.
PAGE 346
NRND: Not recommended for new designs. General-Purpose Timers In One-Shot mode, the timer stops counting after step 8 on page 345. To re-enable the timer, repeat the sequence. A timer configured in Periodic mode does not stop counting after it times out. 9.4.4 16-Bit Input Edge Count Mode A timer is configured to Input Edge Count mode by the following sequence: 1. Ensure the timer is disabled (the TnEN bit is cleared) before making any changes. 2.
PAGE 347
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Interrupt Clear (GPTMICR) register. The time at which the event happened can be obtained by reading the GPTM Timern (GPTMTnR) register. In Input Edge Timing mode, the timer continues running after an edge event has been detected, but the timer interval can be changed at any time by writing the GPTMTnILR register. The change takes effect at the next cycle after the write. 9.4.
PAGE 348
NRND: Not recommended for new designs. General-Purpose Timers Table 9-5. Timers Register Map (continued) Name Type Reset 0x00C GPTMCTL R/W 0x0000.0000 GPTM Control 354 0x018 GPTMIMR R/W 0x0000.0000 GPTM Interrupt Mask 357 0x01C GPTMRIS RO 0x0000.0000 GPTM Raw Interrupt Status 359 0x020 GPTMMIS RO 0x0000.0000 GPTM Masked Interrupt Status 360 0x024 GPTMICR W1C 0x0000.0000 GPTM Interrupt Clear 361 0x028 GPTMTAILR R/W 0xFFFF.
PAGE 349
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 1: GPTM Configuration (GPTMCFG), offset 0x000 This register configures the global operation of the GPTM module. The value written to this register determines whether the GPTM is in 32- or 16-bit mode. GPTM Configuration (GPTMCFG) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x000 Type R/W, reset 0x0000.
PAGE 350
NRND: Not recommended for new designs. General-Purpose Timers Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 This register configures the GPTM based on the configuration selected in the GPTMCFG register. When in 16-bit PWM mode, set the TAAMS bit to 0x1, the TACMR bit to 0x0, and the TAMR field to 0x2. GPTM TimerA Mode (GPTMTAMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x004 Type R/W, reset 0x0000.
PAGE 351
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset 1:0 TAMR R/W 0x0 Description GPTM TimerA Mode The TAMR values are defined as follows: Value Description 0x0 Reserved 0x1 One-Shot Timer mode 0x2 Periodic Timer mode 0x3 Capture mode The Timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register (16-or 32-bit). In 16-bit timer configuration, TAMR controls the 16-bit timer modes for TimerA.
PAGE 352
NRND: Not recommended for new designs. General-Purpose Timers Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 This register configures the GPTM based on the configuration selected in the GPTMCFG register. When in 16-bit PWM mode, set the TBAMS bit to 0x1, the TBCMR bit to 0x0, and the TBMR field to 0x2. GPTM TimerB Mode (GPTMTBMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x008 Type R/W, reset 0x0000.
PAGE 353
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset 1:0 TBMR R/W 0x0 Description GPTM TimerB Mode The TBMR values are defined as follows: Value Description 0x0 Reserved 0x1 One-Shot Timer mode 0x2 Periodic Timer mode 0x3 Capture mode The timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register. In 16-bit timer configuration, these bits control the 16-bit timer modes for TimerB.
PAGE 354
NRND: Not recommended for new designs. General-Purpose Timers Register 4: GPTM Control (GPTMCTL), offset 0x00C This register is used alongside the GPTMCFG and GMTMTnMR registers to fine-tune the timer configuration, and to enable other features such as timer stall and the output trigger. The output trigger can be used to initiate transfers on the ADC module. GPTM Control (GPTMCTL) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.
PAGE 355
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset 11:10 TBEVENT R/W 0x0 Description GPTM TimerB Event Mode The TBEVENT values are defined as follows: Value Description 0x0 Positive edge 0x1 Negative edge 0x2 Reserved 0x3 Both edges 9 TBSTALL R/W 0 GPTM Timer B Stall Enable The TBSTALL values are defined as follows: Value Description 0 Timer B continues counting while the processor is halted by the debugger.
PAGE 356
NRND: Not recommended for new designs. General-Purpose Timers Bit/Field Name Type Reset 4 RTCEN R/W 0 Description GPTM RTC Enable The RTCEN values are defined as follows: Value Description 3:2 TAEVENT R/W 0x0 0 RTC counting is disabled. 1 RTC counting is enabled.
PAGE 357
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 This register allows software to enable/disable GPTM controller-level interrupts. Writing a 1 enables the interrupt, while writing a 0 disables it. GPTM Interrupt Mask (GPTMIMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x018 Type R/W, reset 0x0000.
PAGE 358
NRND: Not recommended for new designs. General-Purpose Timers Bit/Field Name Type Reset 3 RTCIM R/W 0 Description GPTM RTC Interrupt Mask The RTCIM values are defined as follows: Value Description 2 CAEIM R/W 0 0 Interrupt is disabled. 1 Interrupt is enabled. GPTM CaptureA Event Interrupt Mask The CAEIM values are defined as follows: Value Description 1 CAMIM R/W 0 0 Interrupt is disabled. 1 Interrupt is enabled.
PAGE 359
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C This register shows the state of the GPTM's internal interrupt signal. These bits are set whether or not the interrupt is masked in the GPTMIMR register. Each bit can be cleared by writing a 1 to its corresponding bit in GPTMICR. GPTM Raw Interrupt Status (GPTMRIS) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.
PAGE 360
NRND: Not recommended for new designs. General-Purpose Timers Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 This register show the state of the GPTM's controller-level interrupt. If an interrupt is unmasked in GPTMIMR, and there is an event that causes the interrupt to be asserted, the corresponding bit is set in this register. All bits are cleared by writing a 1 to the corresponding bit in GPTMICR. GPTM Masked Interrupt Status (GPTMMIS) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.
PAGE 361
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 This register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1 to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers. GPTM Interrupt Clear (GPTMICR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x024 Type W1C, reset 0x0000.
PAGE 362
NRND: Not recommended for new designs. General-Purpose Timers Bit/Field Name Type Reset 3 RTCCINT W1C 0 Description GPTM RTC Interrupt Clear The RTCCINT values are defined as follows: Value Description 2 CAECINT W1C 0 0 The interrupt is unaffected. 1 The interrupt is cleared. GPTM CaptureA Event Interrupt Clear The CAECINT values are defined as follows: Value Description 1 CAMCINT W1C 0 0 The interrupt is unaffected. 1 The interrupt is cleared.
PAGE 363
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 This register is used to load the starting count value into the timer. When GPTM is configured to one of the 32-bit modes, GPTMTAILR appears as a 32-bit register (the upper 16-bits correspond to the contents of the GPTM TimerB Interval Load (GPTMTBILR) register).
PAGE 364
NRND: Not recommended for new designs. General-Purpose Timers Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C This register is used to load the starting count value into TimerB. When the GPTM is configured to a 32-bit mode, GPTMTBILR returns the current value of TimerB and ignores writes. GPTM TimerB Interval Load (GPTMTBILR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x02C Type R/W, reset 0x0000.
PAGE 365
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 This register is used in 32-bit Real-Time Clock mode and 16-bit PWM and Input Edge Count modes. GPTM TimerA Match (GPTMTAMATCHR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x030 Type R/W, reset 0xFFFF.
PAGE 366
NRND: Not recommended for new designs. General-Purpose Timers Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 This register is used in 16-bit PWM and Input Edge Count modes. GPTM TimerB Match (GPTMTBMATCHR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x034 Type R/W, reset 0x0000.
PAGE 367
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 This register allows software to extend the range of the 16-bit timers when operating in one-shot or periodic mode. GPTM TimerA Prescale (GPTMTAPR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x038 Type R/W, reset 0x0000.
PAGE 368
NRND: Not recommended for new designs. General-Purpose Timers Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C This register allows software to extend the range of the 16-bit timers when operating in one-shot or periodic mode. GPTM TimerB Prescale (GPTMTBPR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x03C Type R/W, reset 0x0000.
PAGE 369
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 This register effectively extends the range of GPTMTAMATCHR to 24 bits when operating in 16-bit one-shot or periodic mode. GPTM TimerA Prescale Match (GPTMTAPMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x040 Type R/W, reset 0x0000.
PAGE 370
NRND: Not recommended for new designs. General-Purpose Timers Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 This register effectively extends the range of GPTMTBMATCHR to 24 bits when operating in 16-bit one-shot or periodic mode. GPTM TimerB Prescale Match (GPTMTBPMR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x044 Type R/W, reset 0x0000.
PAGE 371
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 17: GPTM TimerA (GPTMTAR), offset 0x048 This register shows the current value of the TimerA counter in all cases except for Input Edge Count mode. When in this mode, this register contains the number of edges that have occurred. GPTM TimerA (GPTMTAR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x048 Type RO, reset 0xFFFF.
PAGE 372
NRND: Not recommended for new designs. General-Purpose Timers Register 18: GPTM TimerB (GPTMTBR), offset 0x04C This register shows the current value of the TimerB counter in all cases except for Input Edge Count mode. When in this mode, this register contains the number of edges that have occurred. GPTM TimerB (GPTMTBR) Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 Offset 0x04C Type RO, reset 0x0000.
PAGE 373
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 10 Watchdog Timer A watchdog timer can generate nonmaskable interrupts (NMIs) or a reset when a time-out value is reached. The watchdog timer is used to regain control when a system has failed due to a software error or due to the failure of an external device to respond in the expected way.
PAGE 374
NRND: Not recommended for new designs. Watchdog Timer 10.1 Block Diagram Figure 10-1. WDT Module Block Diagram WDTLOAD Control / Clock / Interrupt Generation WDTCTL WDTICR Interrupt WDTRIS 32-Bit Down Counter WDTMIS 0x00000000 WDTLOCK System Clock WDTTEST Comparator WDTVALUE Identification Registers 10.
PAGE 375
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Writing to WDTLOAD does not clear an active interrupt. An interrupt must be specifically cleared by writing to the Watchdog Interrupt Clear (WDTICR) register. The Watchdog module interrupt and reset generation can be enabled or disabled as required. When the interrupt is re-enabled, the 32-bit counter is preloaded with the load register value and not its last state. 10.
PAGE 376
NRND: Not recommended for new designs. Watchdog Timer Table 10-1. Watchdog Timer Register Map (continued) Offset Name 0xFEC Reset WDTPeriphID3 RO 0x0000.0001 Watchdog Peripheral Identification 3 392 0xFF0 WDTPCellID0 RO 0x0000.000D Watchdog PrimeCell Identification 0 393 0xFF4 WDTPCellID1 RO 0x0000.00F0 Watchdog PrimeCell Identification 1 394 0xFF8 WDTPCellID2 RO 0x0000.0005 Watchdog PrimeCell Identification 2 395 0xFFC WDTPCellID3 RO 0x0000.
PAGE 377
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 1: Watchdog Load (WDTLOAD), offset 0x000 This register is the 32-bit interval value used by the 32-bit counter. When this register is written, the value is immediately loaded and the counter restarts counting down from the new value. If the WDTLOAD register is loaded with 0x0000.0000, an interrupt is immediately generated. Watchdog Load (WDTLOAD) Base 0x4000.0000 Offset 0x000 Type R/W, reset 0xFFFF.
PAGE 378
NRND: Not recommended for new designs. Watchdog Timer Register 2: Watchdog Value (WDTVALUE), offset 0x004 This register contains the current count value of the timer. Watchdog Value (WDTVALUE) Base 0x4000.0000 Offset 0x004 Type RO, reset 0xFFFF.
PAGE 379
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 3: Watchdog Control (WDTCTL), offset 0x008 This register is the watchdog control register. The watchdog timer can be configured to generate a reset signal (on second time-out) or an interrupt on time-out. When the watchdog interrupt has been enabled, all subsequent writes to the control register are ignored. The only mechanism that can re-enable writes is a hardware reset. Watchdog Control (WDTCTL) Base 0x4000.
PAGE 380
NRND: Not recommended for new designs. Watchdog Timer Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C This register is the interrupt clear register. A write of any value to this register clears the Watchdog interrupt and reloads the 32-bit counter from the WDTLOAD register. Value for a read or reset is indeterminate. Watchdog Interrupt Clear (WDTICR) Base 0x4000.
PAGE 381
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 This register is the raw interrupt status register. Watchdog interrupt events can be monitored via this register if the controller interrupt is masked. Watchdog Raw Interrupt Status (WDTRIS) Base 0x4000.0000 Offset 0x010 Type RO, reset 0x0000.
PAGE 382
NRND: Not recommended for new designs. Watchdog Timer Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 This register is the masked interrupt status register. The value of this register is the logical AND of the raw interrupt bit and the Watchdog interrupt enable bit. Watchdog Masked Interrupt Status (WDTMIS) Base 0x4000.0000 Offset 0x014 Type RO, reset 0x0000.
PAGE 383
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 7: Watchdog Test (WDTTEST), offset 0x418 This register provides user-enabled stalling when the microcontroller asserts the CPU halt flag during debug. Watchdog Test (WDTTEST) Base 0x4000.0000 Offset 0x418 Type R/W, reset 0x0000.
PAGE 384
NRND: Not recommended for new designs. Watchdog Timer Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 Writing 0x1ACC.E551 to the WDTLOCK register enables write access to all other registers. Writing any other value to the WDTLOCK register re-enables the locked state for register writes to all the other registers. Reading the WDTLOCK register returns the lock status rather than the 32-bit value written. Therefore, when write accesses are disabled, reading the WDTLOCK register returns 0x0000.
PAGE 385
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 4 (WDTPeriphID4) Base 0x4000.0000 Offset 0xFD0 Type RO, reset 0x0000.
PAGE 386
NRND: Not recommended for new designs. Watchdog Timer Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 5 (WDTPeriphID5) Base 0x4000.0000 Offset 0xFD4 Type RO, reset 0x0000.
PAGE 387
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 6 (WDTPeriphID6) Base 0x4000.0000 Offset 0xFD8 Type RO, reset 0x0000.
PAGE 388
NRND: Not recommended for new designs. Watchdog Timer Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 7 (WDTPeriphID7) Base 0x4000.0000 Offset 0xFDC Type RO, reset 0x0000.
PAGE 389
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 0 (WDTPeriphID0) Base 0x4000.0000 Offset 0xFE0 Type RO, reset 0x0000.
PAGE 390
NRND: Not recommended for new designs. Watchdog Timer Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 1 (WDTPeriphID1) Base 0x4000.0000 Offset 0xFE4 Type RO, reset 0x0000.
PAGE 391
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 2 (WDTPeriphID2) Base 0x4000.0000 Offset 0xFE8 Type RO, reset 0x0000.
PAGE 392
NRND: Not recommended for new designs. Watchdog Timer Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC The WDTPeriphIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog Peripheral Identification 3 (WDTPeriphID3) Base 0x4000.0000 Offset 0xFEC Type RO, reset 0x0000.
PAGE 393
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 0 (WDTPCellID0) Base 0x4000.0000 Offset 0xFF0 Type RO, reset 0x0000.
PAGE 394
NRND: Not recommended for new designs. Watchdog Timer Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 1 (WDTPCellID1) Base 0x4000.0000 Offset 0xFF4 Type RO, reset 0x0000.
PAGE 395
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 2 (WDTPCellID2) Base 0x4000.0000 Offset 0xFF8 Type RO, reset 0x0000.
PAGE 396
NRND: Not recommended for new designs. Watchdog Timer Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC The WDTPCellIDn registers are hard-coded and the fields within the register determine the reset value. Watchdog PrimeCell Identification 3 (WDTPCellID3) Base 0x4000.0000 Offset 0xFFC Type RO, reset 0x0000.
PAGE 397
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 11 Analog-to-Digital Converter (ADC) An analog-to-digital converter (ADC) is a peripheral that converts a continuous analog voltage to a discrete digital number. ® The Stellaris ADC module features 10-bit conversion resolution and supports four input channels, plus an internal temperature sensor.
PAGE 398
NRND: Not recommended for new designs. Analog-to-Digital Converter (ADC) Figure 11-1.
PAGE 399
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 11-2. ADC Signals (108BGA) (continued) a Pin Name Pin Number Pin Type Buffer Type ADC3 B2 I Analog Description Analog-to-digital converter input 3. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 11.
PAGE 400
NRND: Not recommended for new designs. Analog-to-Digital Converter (ADC) 11.3.2 Module Control Outside of the sample sequencers, the remainder of the control logic is responsible for tasks such as: ■ Interrupt generation ■ Sequence prioritization ■ Trigger configuration Most of the ADC control logic runs at the ADC clock rate of 14-18 MHz. The internal ADC divider is configured automatically by hardware when the system XTAL is selected. The automatic clock divider configuration targets 16.
PAGE 401
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 11.3.4 Analog-to-Digital Converter The converter itself generates a 10-bit output value for selected analog input. Special analog pads are used to minimize the distortion on the input. An internal 3 V reference is used by the converter resulting in sample values ranging from 0x000 at 0 V input to 0x3FF at 3 V input when in single-ended input mode. 11.3.
PAGE 402
NRND: Not recommended for new designs. Analog-to-Digital Converter (ADC) Figure 11-2. Differential Sampling Range, VIN_ODD = 1.5 V ADC Conversion Result 0x3FF 0x1FF 0V -1.5 V 1.5 V 0V 3.0 V VIN_EVEN 1.5 V DV VIN_ODD = 1.5 V - Input Saturation Figure 11-3. Differential Sampling Range, VIN_ODD = 0.75 V ADC Conversion Result 0x3FF 0x1FF 0x0FF -1.5 V 0V -0.75 V +0.75 V +2.25 V +1.
PAGE 403
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Figure 11-4. Differential Sampling Range, VIN_ODD = 2.25 V ADC Conversion Result 0x3FF 0x2FF 0x1FF 0.75 V -1.5 V 2.25 V 3.0 V 0.75 V 1.5 V VIN_EVEN DV - Input Saturation 11.3.6 Test Modes There is a user-available test mode that allows for loopback operation within the digital portion of the ADC module. This can be useful for debugging software without having to provide actual analog stimulus.
PAGE 404
NRND: Not recommended for new designs. Analog-to-Digital Converter (ADC) Figure 11-5. Internal Temperature Sensor Characteristic 11.4 Initialization and Configuration In order for the ADC module to be used, the PLL must be enabled and using a supported crystal frequency (see the RCC register). Using unsupported frequencies can cause faulty operation in the ADC module. 11.4.1 Module Initialization Initialization of the ADC module is a simple process with very few steps.
PAGE 405
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 4. For each sample in the sample sequence, configure the sample control bits in the corresponding nibble in the ADCSSCTLn register. When programming the last nibble, ensure that the END bit is set. Failure to set the END bit causes unpredictable behavior. 5. If interrupts are to be used, write a 1 to the corresponding MASK bit in the ADCIM register. 6.
PAGE 406
NRND: Not recommended for new designs. Analog-to-Digital Converter (ADC) Table 11-5. ADC Register Map (continued) Offset Name 0x08C Reset ADCSSFSTAT2 RO 0x0000.0100 ADC Sample Sequence FIFO 2 Status 427 0x0A0 ADCSSMUX3 R/W 0x0000.0000 ADC Sample Sequence Input Multiplexer Select 3 431 0x0A4 ADCSSCTL3 R/W 0x0000.0002 ADC Sample Sequence Control 3 432 0x0A8 ADCSSFIFO3 RO - ADC Sample Sequence Result FIFO 3 426 0x0AC ADCSSFSTAT3 RO 0x0000.
PAGE 407
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 1: ADC Active Sample Sequencer (ADCACTSS), offset 0x000 This register controls the activation of the sample sequencers. Each sample sequencer can be enabled or disabled independently. ADC Active Sample Sequencer (ADCACTSS) Base 0x4003.8000 Offset 0x000 Type R/W, reset 0x0000.
PAGE 408
NRND: Not recommended for new designs. Analog-to-Digital Converter (ADC) Register 2: ADC Raw Interrupt Status (ADCRIS), offset 0x004 This register shows the status of the raw interrupt signal of each sample sequencer. These bits may be polled by software to look for interrupt conditions without having to generate controller interrupts. ADC Raw Interrupt Status (ADCRIS) Base 0x4003.8000 Offset 0x004 Type RO, reset 0x0000.
PAGE 409
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 3: ADC Interrupt Mask (ADCIM), offset 0x008 This register controls whether the sample sequencer raw interrupt signals are promoted to controller interrupts. Each raw interrupt signal can be masked independently. ADC Interrupt Mask (ADCIM) Base 0x4003.8000 Offset 0x008 Type R/W, reset 0x0000.
PAGE 410
NRND: Not recommended for new designs. Analog-to-Digital Converter (ADC) Register 4: ADC Interrupt Status and Clear (ADCISC), offset 0x00C This register provides the mechanism for clearing sample sequence interrupt conditions and shows the status of controller interrupts generated by the sample sequencers. When read, each bit field is the logical AND of the respective INR and MASK bits. Sample sequence nterrupts are cleared by setting the corresponding bit position.
PAGE 411
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 5: ADC Overflow Status (ADCOSTAT), offset 0x010 This register indicates overflow conditions in the sample sequencer FIFOs. Once the overflow condition has been handled by software, the condition can be cleared by writing a 1 to the corresponding bit position. ADC Overflow Status (ADCOSTAT) Base 0x4003.8000 Offset 0x010 Type R/W1C, reset 0x0000.
PAGE 412
NRND: Not recommended for new designs. Analog-to-Digital Converter (ADC) Register 6: ADC Event Multiplexer Select (ADCEMUX), offset 0x014 The ADCEMUX selects the event (trigger) that initiates sampling for each sample sequencer. Each sample sequencer can be configured with a unique trigger source. ADC Event Multiplexer Select (ADCEMUX) Base 0x4003.8000 Offset 0x014 Type R/W, reset 0x0000.
PAGE 413
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset 11:8 EM2 R/W 0x0 Description SS2 Trigger Select This field selects the trigger source for Sample Sequencer 2. The valid configurations for this field are: Value Event 0x0 Controller (default) 0x1 Analog Comparator 0 0x2 Reserved 0x3 Reserved 0x4 External (GPIO PB4) 0x5 Timer In addition, the trigger must be enabled with the TnOTE bit in the GPTMCTL register (see page 354).
PAGE 414
NRND: Not recommended for new designs. Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 7:4 EM1 R/W 0x0 Description SS1 Trigger Select This field selects the trigger source for Sample Sequencer 1. The valid configurations for this field are: Value Event 0x0 Controller (default) 0x1 Analog Comparator 0 0x2 Reserved 0x3 Reserved 0x4 External (GPIO PB4) 0x5 Timer In addition, the trigger must be enabled with the TnOTE bit in the GPTMCTL register (see page 354).
PAGE 415
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset 3:0 EM0 R/W 0x0 Description SS0 Trigger Select This field selects the trigger source for Sample Sequencer 0. The valid configurations for this field are: Value Event 0x0 Controller (default) 0x1 Analog Comparator 0 0x2 Reserved 0x3 Reserved 0x4 External (GPIO PB4) 0x5 Timer In addition, the trigger must be enabled with the TnOTE bit in the GPTMCTL register (see page 354).
PAGE 416
NRND: Not recommended for new designs. Analog-to-Digital Converter (ADC) Register 7: ADC Underflow Status (ADCUSTAT), offset 0x018 This register indicates underflow conditions in the sample sequencer FIFOs. The corresponding underflow condition is cleared by writing a 1 to the relevant bit position. ADC Underflow Status (ADCUSTAT) Base 0x4003.8000 Offset 0x018 Type R/W1C, reset 0x0000.
PAGE 417
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 8: ADC Sample Sequencer Priority (ADCSSPRI), offset 0x020 This register sets the priority for each of the sample sequencers. Out of reset, Sequencer 0 has the highest priority, and Sequencer 3 has the lowest priority. When reconfiguring sequence priorities, each sequence must have a unique priority for the ADC to operate properly. ADC Sample Sequencer Priority (ADCSSPRI) Base 0x4003.
PAGE 418
NRND: Not recommended for new designs. Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset Description 1:0 SS0 R/W 0x0 SS0 Priority This field contains a binary-encoded value that specifies the priority encoding of Sample Sequencer 0. A priority encoding of 0 is highest and 3 is lowest. The priorities assigned to the sequencers must be uniquely mapped. The ADC may not operate properly if two or more fields are equal.
PAGE 419
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 9: ADC Processor Sample Sequence Initiate (ADCPSSI), offset 0x028 This register provides a mechanism for application software to initiate sampling in the sample sequencers. Sample sequences can be initiated individually or in any combination. When multiple sequences are triggered simultaneously, the priority encodings in ADCSSPRI dictate execution order. ADC Processor Sample Sequence Initiate (ADCPSSI) Base 0x4003.
PAGE 420
NRND: Not recommended for new designs. Analog-to-Digital Converter (ADC) Register 10: ADC Sample Averaging Control (ADCSAC), offset 0x030 This register controls the amount of hardware averaging applied to conversion results. The final conversion result stored in the FIFO is averaged from 2 AVG consecutive ADC samples at the specified ADC speed. If AVG is 0, the sample is passed directly through without any averaging.
PAGE 421
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 11: ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0), offset 0x040 This register defines the analog input configuration for each sample in a sequence executed with Sample Sequencer 0. This register is 32 bits wide and contains information for eight possible samples. ADC Sample Sequence Input Multiplexer Select 0 (ADCSSMUX0) Base 0x4003.8000 Offset 0x040 Type R/W, reset 0x0000.
PAGE 422
NRND: Not recommended for new designs. Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 17:16 MUX4 R/W 0x0 Description 5th Sample Input Select The MUX4 field is used during the fifth sample of a sequence executed with the sample sequencer. It specifies which of the analog inputs is sampled for the analog-to-digital conversion. 15:14 reserved RO 0 13:12 MUX3 R/W 0x0 Software should not rely on the value of a reserved bit.
PAGE 423
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 12: ADC Sample Sequence Control 0 (ADCSSCTL0), offset 0x044 This register contains the configuration information for each sample for a sequence executed with a sample sequencer. When configuring a sample sequence, the END bit must be set at some point, whether it be after the first sample, last sample, or any sample in between. This register is 32-bits wide and contains information for eight possible samples.
PAGE 424
NRND: Not recommended for new designs. Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 26 IE6 R/W 0 Description 7th Sample Interrupt Enable Same definition as IE7 but used during the seventh sample. 25 END6 R/W 0 7th Sample is End of Sequence Same definition as END7 but used during the seventh sample. 24 D6 R/W 0 7th Sample Diff Input Select Same definition as D7 but used during the seventh sample.
PAGE 425
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset 8 D2 R/W 0 Description 3rd Sample Diff Input Select Same definition as D7 but used during the third sample. 7 TS1 R/W 0 2nd Sample Temp Sensor Select Same definition as TS7 but used during the second sample. 6 IE1 R/W 0 2nd Sample Interrupt Enable Same definition as IE7 but used during the second sample.
PAGE 426
NRND: Not recommended for new designs. Analog-to-Digital Converter (ADC) Register 13: ADC Sample Sequence Result FIFO 0 (ADCSSFIFO0), offset 0x048 Register 14: ADC Sample Sequence Result FIFO 1 (ADCSSFIFO1), offset 0x068 Register 15: ADC Sample Sequence Result FIFO 2 (ADCSSFIFO2), offset 0x088 Register 16: ADC Sample Sequence Result FIFO 3 (ADCSSFIFO3), offset 0x0A8 Important: This register is read-sensitive. See the register description for details.
PAGE 427
NRND: Not recommended for new designs.
PAGE 428
NRND: Not recommended for new designs. Analog-to-Digital Converter (ADC) Register 21: ADC Sample Sequence Input Multiplexer Select 1 (ADCSSMUX1), offset 0x060 Register 22: ADC Sample Sequence Input Multiplexer Select 2 (ADCSSMUX2), offset 0x080 This register defines the analog input configuration for each sample in a sequence executed with Sample Sequencer 1 or 2. These registers are 16-bits wide and contain information for four possible samples.
PAGE 429
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 23: ADC Sample Sequence Control 1 (ADCSSCTL1), offset 0x064 Register 24: ADC Sample Sequence Control 2 (ADCSSCTL2), offset 0x084 These registers contain the configuration information for each sample for a sequence executed with Sample Sequencer 1 or 2. When configuring a sample sequence, the END bit must be set at some point, whether it be after the first sample, last sample, or any sample in between.
PAGE 430
NRND: Not recommended for new designs. Analog-to-Digital Converter (ADC) Bit/Field Name Type Reset 6 IE1 R/W 0 Description 2nd Sample Interrupt Enable Same definition as IE7 but used during the second sample. 5 END1 R/W 0 2nd Sample is End of Sequence Same definition as END7 but used during the second sample. 4 D1 R/W 0 2nd Sample Diff Input Select Same definition as D7 but used during the second sample.
PAGE 431
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 25: ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3), offset 0x0A0 This register defines the analog input configuration for a sample executed with Sample Sequencer 3. This register is 4-bits wide and contains information for one possible sample. See the ADCSSMUX0 register on page 421 for detailed bit descriptions. ADC Sample Sequence Input Multiplexer Select 3 (ADCSSMUX3) Base 0x4003.
PAGE 432
NRND: Not recommended for new designs. Analog-to-Digital Converter (ADC) Register 26: ADC Sample Sequence Control 3 (ADCSSCTL3), offset 0x0A4 This register contains the configuration information for a sample executed with Sample Sequencer 3. The END bit is always set since there is only one sample in this sequencer. This register is 4-bits wide and contains information for one possible sample. See the ADCSSCTL0 register on page 423 for detailed bit descriptions.
PAGE 433
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 27: ADC Test Mode Loopback (ADCTMLB), offset 0x100 This register provides loopback operation within the digital logic of the ADC, which can be useful in debugging software without having to provide actual analog stimulus. This test mode is entered by writing a value of 0x0000.0001 to this register. When data is read from the FIFO in loopback mode, the read-only portion of this register is returned.
PAGE 434
NRND: Not recommended for new designs. Universal Asynchronous Receivers/Transmitters (UARTs) 12 Universal Asynchronous Receivers/Transmitters (UARTs) ® Each Stellaris Universal Asynchronous Receiver/Transmitter (UART) has the following features: ■ Two fully programmable 16C550-type UARTs with IrDA support ■ Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service loading ■ Programmable baud-rate generator allowing speeds up to 3.
PAGE 435
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 12.1 Block Diagram Figure 12-1. UART Module Block Diagram System Clock Interrupt Interrupt Control UARTIFLS UARTIM UARTMIS UARTRIS UARTICR Identification Registers UARTPCellID0 UARTPCellID1 UARTPCellID2 UARTPCellID3 UARTPeriphID0 UARTPeriphID1 UARTPeriphID2 UARTPeriphID3 UARTPeriphID4 UARTPeriphID5 UARTPeriphID6 UARTPeriphID7 12.2 TxFIFO 16 x 8 . . .
PAGE 436
NRND: Not recommended for new designs. Universal Asynchronous Receivers/Transmitters (UARTs) Table 12-1. UART Signals (100LQFP) (continued) a Pin Name Pin Number Pin Type Buffer Type U1Tx 13 O TTL Description UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 12-2. UART Signals (108BGA) a Pin Name Pin Number Pin Type Buffer Type Description U0Rx L3 I TTL UART module 0 receive.
PAGE 437
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 12.3.2 Baud-Rate Generation The baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part. The number formed by these two values is used by the baud-rate generator to determine the bit period. Having a fractional baud-rate divider allows the UART to generate all the standard baud rates.
PAGE 438
NRND: Not recommended for new designs. Universal Asynchronous Receivers/Transmitters (UARTs) The start bit is valid and recognized if UnRx is still low on the eighth cycle of Baud16, otherwise it is ignored. After a valid start bit is detected, successive data bits are sampled on every 16th cycle of Baud16 (that is, one bit period later) according to the programmed length of the data characters. The parity bit is then checked if parity mode was enabled.
PAGE 439
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller The IrDA SIR physical layer specifies a half-duplex communication link, with a minimum 10 ms delay between transmission and reception. This delay must be generated by software because it is not automatically supported by the UART. The delay is required because the infrared receiver electronics might become biased, or even saturated from the optical power coupled from the adjacent transmitter LED.
PAGE 440
NRND: Not recommended for new designs. Universal Asynchronous Receivers/Transmitters (UARTs) not used, the raw interrupt status is always visible via the UART Raw Interrupt Status (UARTRIS) register (see page 460). Interrupts are always cleared (for both the UARTMIS and UARTRIS registers) by setting the corresponding bit in the UART Interrupt Clear (UARTICR) register (see page 462).
PAGE 441
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller ■ FIFOs disabled ■ No interrupts The first thing to consider when programming the UART is the baud-rate divisor (BRD), since the UARTIBRD and UARTFBRD registers must be written before the UARTLCRH register. Using the equation described in “Baud-Rate Generation” on page 437, the BRD can be calculated: BRD = 20,000,000 / (16 * 115,200) = 10.
PAGE 442
NRND: Not recommended for new designs. Universal Asynchronous Receivers/Transmitters (UARTs) Table 12-3. UART Register Map (continued) Name Type Reset 0x028 UARTFBRD R/W 0x0000.0000 UART Fractional Baud-Rate Divisor 451 0x02C UARTLCRH R/W 0x0000.0000 UART Line Control 452 0x030 UARTCTL R/W 0x0000.0300 UART Control 454 0x034 UARTIFLS R/W 0x0000.0012 UART Interrupt FIFO Level Select 456 0x038 UARTIM R/W 0x0000.0000 UART Interrupt Mask 458 0x03C UARTRIS RO 0x0000.
PAGE 443
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 1: UART Data (UARTDR), offset 0x000 Important: This register is read-sensitive. See the register description for details. This register is the data register (the interface to the FIFOs). When FIFOs are enabled, data written to this location is pushed onto the transmit FIFO. If FIFOs are disabled, data is stored in the transmitter holding register (the bottom word of the transmit FIFO).
PAGE 444
NRND: Not recommended for new designs. Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset 9 PE RO 0 Description UART Parity Error This bit is set to 1 when the parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register. In FIFO mode, this error is associated with the character at the top of the FIFO.
PAGE 445
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 The UARTRSR/UARTECR register is the receive status register/error clear register. In addition to the UARTDR register, receive status can also be read from the UARTRSR register. If the status is read from this register, then the status information corresponds to the entry read from UARTDR prior to reading UARTRSR.
PAGE 446
NRND: Not recommended for new designs. Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset 1 PE RO 0 Description UART Parity Error This bit is set to 1 when the parity of the received data character does not match the parity defined by bits 2 and 7 of the UARTLCRH register. This bit is cleared to 0 by a write to UARTECR. 0 FE RO 0 UART Framing Error This bit is set to 1 when the received character does not have a valid stop bit (a valid stop bit is 1).
PAGE 447
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 3: UART Flag (UARTFR), offset 0x018 The UARTFR register is the flag register. After reset, the TXFF, RXFF, and BUSY bits are 0, and TXFE and RXFE bits are 1. UART Flag (UARTFR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x018 Type RO, reset 0x0000.
PAGE 448
NRND: Not recommended for new designs. Universal Asynchronous Receivers/Transmitters (UARTs) Bit/Field Name Type Reset Description 3 BUSY RO 0 UART Busy When this bit is 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty (regardless of whether UART is enabled). 2:0 reserved RO 0 Software should not rely on the value of a reserved bit.
PAGE 449
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 The UARTILPR register is an 8-bit read/write register that stores the low-power counter divisor value used to derive the low-power SIR pulse width clock by dividing down the system clock (SysClk). All the bits are cleared to 0 when reset. The internal IrLPBaud16 clock is generated by dividing down SysClk according to the low-power divisor value written to UARTILPR.
PAGE 450
NRND: Not recommended for new designs. Universal Asynchronous Receivers/Transmitters (UARTs) Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 The UARTIBRD register is the integer part of the baud-rate divisor value. All the bits are cleared on reset. The minimum possible divide ratio is 1 (when UARTIBRD=0), in which case the UARTFBRD register is ignored.
PAGE 451
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 The UARTFBRD register is the fractional part of the baud-rate divisor value. All the bits are cleared on reset. When changing the UARTFBRD register, the new value does not take effect until transmission/reception of the current character is complete. Any changes to the baud-rate divisor must be followed by a write to the UARTLCRH register.
PAGE 452
NRND: Not recommended for new designs. Universal Asynchronous Receivers/Transmitters (UARTs) Register 7: UART Line Control (UARTLCRH), offset 0x02C The UARTLCRH register is the line control register. Serial parameters such as data length, parity, and stop bit selection are implemented in this register. When updating the baud-rate divisor (UARTIBRD and/or UARTIFRD), the UARTLCRH register must also be written. The write strobe for the baud-rate divisor registers is tied to the UARTLCRH register.
PAGE 453
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset 2 EPS R/W 0 Description UART Even Parity Select If this bit is set to 1, even parity generation and checking is performed during transmission and reception, which checks for an even number of 1s in data and parity bits. When cleared to 0, then odd parity is performed, which checks for an odd number of 1s. This bit has no effect when parity is disabled by the PEN bit.
PAGE 454
NRND: Not recommended for new designs. Universal Asynchronous Receivers/Transmitters (UARTs) Register 8: UART Control (UARTCTL), offset 0x030 The UARTCTL register is the control register. All the bits are cleared on reset except for the Transmit Enable (TXE) and Receive Enable (RXE) bits, which are set to 1. To enable the UART module, the UARTEN bit must be set to 1. If software requires a configuration change in the module, the UARTEN bit must be cleared before the configuration changes are written.
PAGE 455
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset 7 LBE R/W 0 Description UART Loop Back Enable If this bit is set to 1, the UnTX path is fed through the UnRX path. 6:3 reserved RO 0 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
PAGE 456
NRND: Not recommended for new designs. Universal Asynchronous Receivers/Transmitters (UARTs) Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 The UARTIFLS register is the interrupt FIFO level select register. You can use this register to define the FIFO level at which the TXRIS and RXRIS bits in the UARTRIS register are triggered. The interrupts are generated based on a transition through a level rather than being based on the level.
PAGE 457
NRND: Not recommended for new designs.
PAGE 458
NRND: Not recommended for new designs. Universal Asynchronous Receivers/Transmitters (UARTs) Register 10: UART Interrupt Mask (UARTIM), offset 0x038 The UARTIM register is the interrupt mask set/clear register. On a read, this register gives the current value of the mask on the relevant interrupt. Writing a 1 to a bit allows the corresponding raw interrupt signal to be routed to the interrupt controller. Writing a 0 prevents the raw interrupt signal from being sent to the interrupt controller.
PAGE 459
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset Description 3:0 reserved RO 0x00 Software should not rely on the value of a reserved bit. To provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation.
PAGE 460
NRND: Not recommended for new designs. Universal Asynchronous Receivers/Transmitters (UARTs) Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C The UARTRIS register is the raw interrupt status register. On a read, this register gives the current raw status value of the corresponding interrupt. A write has no effect. UART Raw Interrupt Status (UARTRIS) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x03C Type RO, reset 0x0000.
PAGE 461
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 The UARTMIS register is the masked interrupt status register. On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect. UART Masked Interrupt Status (UARTMIS) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x040 Type RO, reset 0x0000.
PAGE 462
NRND: Not recommended for new designs. Universal Asynchronous Receivers/Transmitters (UARTs) Register 13: UART Interrupt Clear (UARTICR), offset 0x044 The UARTICR register is the interrupt clear register. On a write of 1, the corresponding interrupt (both raw interrupt and masked interrupt, if enabled) is cleared. A write of 0 has no effect. UART Interrupt Clear (UARTICR) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0x044 Type W1C, reset 0x0000.
PAGE 463
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset 6 RTIC W1C 0 Description Receive Time-Out Interrupt Clear The RTIC values are defined as follows: Value Description 5 TXIC W1C 0 0 No effect on the interrupt. 1 Clears interrupt. Transmit Interrupt Clear The TXIC values are defined as follows: Value Description 4 RXIC W1C 0 0 No effect on the interrupt. 1 Clears interrupt.
PAGE 464
NRND: Not recommended for new designs. Universal Asynchronous Receivers/Transmitters (UARTs) Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 4 (UARTPeriphID4) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0xFD0 Type RO, reset 0x0000.
PAGE 465
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 5 (UARTPeriphID5) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0xFD4 Type RO, reset 0x0000.
PAGE 466
NRND: Not recommended for new designs. Universal Asynchronous Receivers/Transmitters (UARTs) Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 6 (UARTPeriphID6) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0xFD8 Type RO, reset 0x0000.
PAGE 467
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 7 (UARTPeriphID7) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0xFDC Type RO, reset 0x0000.
PAGE 468
NRND: Not recommended for new designs. Universal Asynchronous Receivers/Transmitters (UARTs) Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 0 (UARTPeriphID0) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0xFE0 Type RO, reset 0x0000.
PAGE 469
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 1 (UARTPeriphID1) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0xFE4 Type RO, reset 0x0000.
PAGE 470
NRND: Not recommended for new designs. Universal Asynchronous Receivers/Transmitters (UARTs) Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 2 (UARTPeriphID2) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0xFE8 Type RO, reset 0x0000.
PAGE 471
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC The UARTPeriphIDn registers are hard-coded and the fields within the registers determine the reset values. UART Peripheral Identification 3 (UARTPeriphID3) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0xFEC Type RO, reset 0x0000.
PAGE 472
NRND: Not recommended for new designs. Universal Asynchronous Receivers/Transmitters (UARTs) Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 0 (UARTPCellID0) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0xFF0 Type RO, reset 0x0000.
PAGE 473
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 1 (UARTPCellID1) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0xFF4 Type RO, reset 0x0000.
PAGE 474
NRND: Not recommended for new designs. Universal Asynchronous Receivers/Transmitters (UARTs) Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 2 (UARTPCellID2) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0xFF8 Type RO, reset 0x0000.
PAGE 475
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC The UARTPCellIDn registers are hard-coded and the fields within the registers determine the reset values. UART PrimeCell Identification 3 (UARTPCellID3) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 Offset 0xFFC Type RO, reset 0x0000.
PAGE 476
NRND: Not recommended for new designs. Synchronous Serial Interface (SSI) 13 Synchronous Serial Interface (SSI) ® The Stellaris Synchronous Serial Interface (SSI) is a master or slave interface for synchronous serial communication with peripheral devices that have either Freescale SPI, MICROWIRE, or Texas Instruments synchronous serial interfaces.
PAGE 477
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller default to be GPIO signals at reset., with the exception of the SSI0Clk, SSI0Fss, SSI0Rx, and SSI0Tx pins which default to the SSI function. The column in the table below titled "Pin Assignment" lists the possible GPIO pin placements for the SSI signals. The AFSEL bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 311) should be set to choose the SSI function.
PAGE 478
NRND: Not recommended for new designs. Synchronous Serial Interface (SSI) 13.3.2 FIFO Operation 13.3.2.1 Transmit FIFO The common transmit FIFO is a 16-bit wide, 8-locations deep, first-in, first-out memory buffer. The CPU writes data to the FIFO by writing the SSI Data (SSIDR) register (see page 493), and data is stored in the FIFO until it is read out by the transmission logic.
PAGE 479
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller ■ Freescale SPI ■ MICROWIRE For all three formats, the serial clock (SSIClk) is held inactive while the SSI is idle, and SSIClk transitions at the programmed frequency only during active transmission or reception of data. The idle state of SSIClk is utilized to provide a receive timeout indication that occurs when the receive FIFO still contains data after a timeout period.
PAGE 480
NRND: Not recommended for new designs. Synchronous Serial Interface (SSI) Figure 13-3. TI Synchronous Serial Frame Format (Continuous Transfer) SSIClk SSIFss SSITx/SSIRx MSB LSB 4 to 16 bits 13.3.4.2 Freescale SPI Frame Format The Freescale SPI interface is a four-wire interface where the SSIFss signal behaves as a slave select.
PAGE 481
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Figure 13-5.
PAGE 482
NRND: Not recommended for new designs. Synchronous Serial Interface (SSI) Figure 13-6. Freescale SPI Frame Format with SPO=0 and SPH=1 SSIClk SSIFss SSIRx Q MSB Q LSB Q 4 to 16 bits SSITx LSB MSB Note: Q is undefined.
PAGE 483
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Figure 13-8.
PAGE 484
NRND: Not recommended for new designs. Synchronous Serial Interface (SSI) Figure 13-9. Freescale SPI Frame Format with SPO=1 and SPH=1 SSIClk SSIFss SSIRx Q MSB LSB Q 4 to 16 bits MSB SSITx Note: LSB Q is undefined.
PAGE 485
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller MICROWIRE format is very similar to SPI format, except that transmission is half-duplex instead of full-duplex, using a master-slave message passing technique. Each serial transmission begins with an 8-bit control word that is transmitted from the SSI to the off-chip slave device. During this transmission, no incoming data is received by the SSI.
PAGE 486
NRND: Not recommended for new designs. Synchronous Serial Interface (SSI) Figure 13-12 on page 486 illustrates these setup and hold time requirements. With respect to the SSIClk rising edge on which the first bit of receive data is to be sampled by the SSI slave, SSIFss must have a setup of at least two times the period of SSIClk on which the SSI operates. With respect to the SSIClk rising edge previous to this edge, SSIFss must have a hold of at least one SSIClk period. Figure 13-12.
PAGE 487
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller ■ 1 Mbps bit rate ■ 8 data bits Assuming the system clock is 20 MHz, the bit rate calculation would be: FSSIClk = FSysClk / (CPSDVSR * (1 + SCR)) 1x106 = 20x106 / (CPSDVSR * (1 + SCR)) In this case, if CPSDVSR=2, SCR must be 9. The configuration sequence would be as follows: 1. Ensure that the SSE bit in the SSICR1 register is disabled. 2. Write the SSICR1 register with a value of 0x0000.0000. 3.
PAGE 488
NRND: Not recommended for new designs. Synchronous Serial Interface (SSI) Table 13-3. SSI Register Map (continued) Offset Name 0xFD0 Reset SSIPeriphID4 RO 0x0000.0000 SSI Peripheral Identification 4 502 0xFD4 SSIPeriphID5 RO 0x0000.0000 SSI Peripheral Identification 5 503 0xFD8 SSIPeriphID6 RO 0x0000.0000 SSI Peripheral Identification 6 504 0xFDC SSIPeriphID7 RO 0x0000.0000 SSI Peripheral Identification 7 505 0xFE0 SSIPeriphID0 RO 0x0000.
PAGE 489
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 1: SSI Control 0 (SSICR0), offset 0x000 SSICR0 is control register 0 and contains bit fields that control various functions within the SSI module. Functionality such as protocol mode, clock rate, and data size are configured in this register. SSI Control 0 (SSICR0) SSI0 base: 0x4000.8000 Offset 0x000 Type R/W, reset 0x0000.
PAGE 490
NRND: Not recommended for new designs.
PAGE 491
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 2: SSI Control 1 (SSICR1), offset 0x004 SSICR1 is control register 1 and contains bit fields that control various functions within the SSI module. Master and slave mode functionality is controlled by this register. SSI Control 1 (SSICR1) SSI0 base: 0x4000.8000 Offset 0x004 Type R/W, reset 0x0000.
PAGE 492
NRND: Not recommended for new designs. Synchronous Serial Interface (SSI) Bit/Field Name Type Reset 1 SSE R/W 0 Description SSI Synchronous Serial Port Enable Setting this bit enables SSI operation. The SSE values are defined as follows: Value Description 0 SSI operation disabled. 1 SSI operation enabled. Note: 0 LBM R/W 0 This bit must be set to 0 before any control registers are reprogrammed. SSI Loopback Mode Setting this bit enables Loopback Test mode.
PAGE 493
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 3: SSI Data (SSIDR), offset 0x008 Important: This register is read-sensitive. See the register description for details. SSIDR is the data register and is 16-bits wide. When SSIDR is read, the entry in the receive FIFO (pointed to by the current FIFO read pointer) is accessed.
PAGE 494
NRND: Not recommended for new designs. Synchronous Serial Interface (SSI) Register 4: SSI Status (SSISR), offset 0x00C SSISR is a status register that contains bits that indicate the FIFO fill status and the SSI busy status. SSI Status (SSISR) SSI0 base: 0x4000.8000 Offset 0x00C Type RO, reset 0x0000.
PAGE 495
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset 0 TFE R0 1 Description SSI Transmit FIFO Empty The TFE values are defined as follows: Value Description 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty.
PAGE 496
NRND: Not recommended for new designs. Synchronous Serial Interface (SSI) Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 SSICPSR is the clock prescale register and specifies the division factor by which the system clock must be internally divided before further use. The value programmed into this register must be an even number between 2 and 254. The least-significant bit of the programmed number is hard-coded to zero.
PAGE 497
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 The SSIIM register is the interrupt mask set or clear register. It is a read/write register and all bits are cleared to 0 on reset. On a read, this register gives the current value of the mask on the relevant interrupt. A write of 1 to the particular bit sets the mask, enabling the interrupt to be read. A write of 0 clears the corresponding mask.
PAGE 498
NRND: Not recommended for new designs. Synchronous Serial Interface (SSI) Bit/Field Name Type Reset 0 RORIM R/W 0 Description SSI Receive Overrun Interrupt Mask The RORIM values are defined as follows: Value Description 0 RX FIFO overrun interrupt is masked. 1 RX FIFO overrun interrupt is not masked.
PAGE 499
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 The SSIRIS register is the raw interrupt status register. On a read, this register gives the current raw status value of the corresponding interrupt prior to masking. A write has no effect. SSI Raw Interrupt Status (SSIRIS) SSI0 base: 0x4000.8000 Offset 0x018 Type RO, reset 0x0000.
PAGE 500
NRND: Not recommended for new designs. Synchronous Serial Interface (SSI) Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C The SSIMIS register is the masked interrupt status register. On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect. SSI Masked Interrupt Status (SSIMIS) SSI0 base: 0x4000.8000 Offset 0x01C Type RO, reset 0x0000.
PAGE 501
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 The SSIICR register is the interrupt clear register. On a write of 1, the corresponding interrupt is cleared. A write of 0 has no effect. SSI Interrupt Clear (SSIICR) SSI0 base: 0x4000.8000 Offset 0x020 Type W1C, reset 0x0000.
PAGE 502
NRND: Not recommended for new designs. Synchronous Serial Interface (SSI) Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 4 (SSIPeriphID4) SSI0 base: 0x4000.8000 Offset 0xFD0 Type RO, reset 0x0000.
PAGE 503
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 5 (SSIPeriphID5) SSI0 base: 0x4000.8000 Offset 0xFD4 Type RO, reset 0x0000.
PAGE 504
NRND: Not recommended for new designs. Synchronous Serial Interface (SSI) Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 6 (SSIPeriphID6) SSI0 base: 0x4000.8000 Offset 0xFD8 Type RO, reset 0x0000.
PAGE 505
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 7 (SSIPeriphID7) SSI0 base: 0x4000.8000 Offset 0xFDC Type RO, reset 0x0000.
PAGE 506
NRND: Not recommended for new designs. Synchronous Serial Interface (SSI) Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 0 (SSIPeriphID0) SSI0 base: 0x4000.8000 Offset 0xFE0 Type RO, reset 0x0000.
PAGE 507
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 1 (SSIPeriphID1) SSI0 base: 0x4000.8000 Offset 0xFE4 Type RO, reset 0x0000.
PAGE 508
NRND: Not recommended for new designs. Synchronous Serial Interface (SSI) Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 2 (SSIPeriphID2) SSI0 base: 0x4000.8000 Offset 0xFE8 Type RO, reset 0x0000.
PAGE 509
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC The SSIPeriphIDn registers are hard-coded and the fields within the register determine the reset value. SSI Peripheral Identification 3 (SSIPeriphID3) SSI0 base: 0x4000.8000 Offset 0xFEC Type RO, reset 0x0000.
PAGE 510
NRND: Not recommended for new designs. Synchronous Serial Interface (SSI) Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset value. SSI PrimeCell Identification 0 (SSIPCellID0) SSI0 base: 0x4000.8000 Offset 0xFF0 Type RO, reset 0x0000.
PAGE 511
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset value. SSI PrimeCell Identification 1 (SSIPCellID1) SSI0 base: 0x4000.8000 Offset 0xFF4 Type RO, reset 0x0000.
PAGE 512
NRND: Not recommended for new designs. Synchronous Serial Interface (SSI) Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset value. SSI PrimeCell Identification 2 (SSIPCellID2) SSI0 base: 0x4000.8000 Offset 0xFF8 Type RO, reset 0x0000.
PAGE 513
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC The SSIPCellIDn registers are hard-coded, and the fields within the register determine the reset value. SSI PrimeCell Identification 3 (SSIPCellID3) SSI0 base: 0x4000.8000 Offset 0xFFC Type RO, reset 0x0000.
PAGE 514
NRND: Not recommended for new designs. Inter-Integrated Circuit (I2C) Interface 14 Inter-Integrated Circuit (I2C) Interface The Inter-Integrated Circuit (I2C) bus provides bi-directional data transfer through a two-wire design (a serial data line SDA and a serial clock line SCL), and interfaces to external I2C devices such as serial memory (RAMs and ROMs), networking devices, LCDs, tone generators, and so on.
PAGE 515
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 14.1 Block Diagram Figure 14-1. I2C Block Diagram I2CSCL I2C Control Interrupt I2CMSA I2CSOAR I2CMCS I2CSCSR I2CMDR I2CSDR I2CMTPR I2CSIM I2CMIMR I2CSRIS I2CMRIS I2CSMIS I2CMMIS I2CSICR I2C Master Core I2CSCL I2C I/O Select I2CSDA I2CSCL I2C Slave Core I2CMICR I2CSDA I2CMCR 14.
PAGE 516
NRND: Not recommended for new designs. Inter-Integrated Circuit (I2C) Interface Figure 14-2. I2C Bus Configuration RPUP SCL SDA I2C Bus I2CSCL I2CSDA StellarisTM 14.3.1 RPUP SCL SDA 3rd Party Device with I2C Interface SCL SDA 3rd Party Device with I2C Interface I2C Bus Functional Overview The I2C bus uses only two signals: SDA and SCL, named I2CSDA and I2CSCL on Stellaris microcontrollers. SDA is the bi-directional serial data line and SCL is the bi-directional serial clock line.
PAGE 517
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Figure 14-4. Complete Data Transfer with a 7-Bit Address SDA MSB SCL 1 2 LSB R/S ACK 7 8 9 MSB 1 2 Slave address 7 LSB ACK 8 9 Data The first seven bits of the first byte make up the slave address (see Figure 14-5 on page 517). The eighth bit determines the direction of the message.
PAGE 518
NRND: Not recommended for new designs. Inter-Integrated Circuit (I2C) Interface arbitration scheme takes place on the SDA line, while SCL is High. During arbitration, the first of the competing master devices to place a '1' (High) on SDA while another master transmits a '0' (Low) will switch off its data output stage and retire until the bus is idle again. Arbitration can take place over several bits.
PAGE 519
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 14.3.3 Interrupts The I2C can generate interrupts when the following conditions are observed: ■ Master transaction completed ■ Master arbitration lost ■ Master transaction error ■ Slave transaction received ■ Slave transaction requested There is a separate interrupt signal for the I2C master and I2C slave modules.
PAGE 520
NRND: Not recommended for new designs. Inter-Integrated Circuit (I2C) Interface 14.3.5.1 I2C Master Command Sequences The figures that follow show the command sequences available for the I2C master.
PAGE 521
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Figure 14-7.
PAGE 522
NRND: Not recommended for new designs. Inter-Integrated Circuit (I2C) Interface Figure 14-8.
PAGE 523
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Figure 14-9.
PAGE 524
NRND: Not recommended for new designs. Inter-Integrated Circuit (I2C) Interface Figure 14-10.
PAGE 525
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Figure 14-11.
PAGE 526
NRND: Not recommended for new designs. Inter-Integrated Circuit (I2C) Interface Figure 14-12. Master Burst SEND after Burst RECEIVE Idle Master operates in Master Receive mode STOP condition is not generated Write Slave Address to I2CMSA Write ---0-011 to I2CMCS Master operates in Master Transmit mode Repeated START condition is generated with changing data direction Idle 14.3.5.2 I2C Slave Command Sequences Figure 14-13 on page 527 presents the command sequence available for the I2C slave.
PAGE 527
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Figure 14-13. Slave Command Sequence Idle Write OWN Slave Address to I2CSOAR Write -------1 to I2CSCSR Read I2CSCSR NO TREQ bit=1? YES Write data to I2CSDR 14.4 NO RREQ bit=1? FBR is also valid YES Read data from I2CSDR Initialization and Configuration The following example shows how to configure the I2C module to send a single byte as a master. This assumes the system clock is 20 MHz. 1.
PAGE 528
NRND: Not recommended for new designs. Inter-Integrated Circuit (I2C) Interface TPR = (System Clock / (2 * (SCL_LP + SCL_HP) * SCL_CLK)) - 1; TPR = (20MHz / (2 * (6 + 4) * 100000)) - 1; TPR = 9 Write the I2CMTPR register with the value of 0x0000.0009. 6. Specify the slave address of the master and that the next operation will be a Send by writing the I2CMSA register with a value of 0x0000.0076. This sets the slave address to 0x3B. 7.
PAGE 529
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 14-4. Inter-Integrated Circuit (I2C) Interface Register Map (continued) Offset Description See page Name Type Reset 0x800 I2CSOAR R/W 0x0000.0000 I2C Slave Own Address 543 0x804 I2CSCSR RO 0x0000.0000 I2C Slave Control/Status 544 0x808 I2CSDR R/W 0x0000.0000 I2C Slave Data 546 0x80C I2CSIMR R/W 0x0000.0000 I2C Slave Interrupt Mask 547 0x810 I2CSRIS RO 0x0000.
PAGE 530
NRND: Not recommended for new designs. Inter-Integrated Circuit (I2C) Interface Register 1: I2C Master Slave Address (I2CMSA), offset 0x000 This register consists of eight bits: seven address bits (A6-A0), and a Receive/Send bit, which determines if the next operation is a Receive (High), or Send (Low). I2C Master Slave Address (I2CMSA) I2C 0 base: 0x4002.0000 Offset 0x000 Type R/W, reset 0x0000.
PAGE 531
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 2: I2C Master Control/Status (I2CMCS), offset 0x004 This register accesses four control bits when written, and accesses seven status bits when read. The status register consists of seven bits, which when read determine the state of the I2C bus controller. The control register consists of four bits: the RUN, START, STOP, and ACK bits. The START bit causes the generation of the START, or REPEATED START condition.
PAGE 532
NRND: Not recommended for new designs. Inter-Integrated Circuit (I2C) Interface Bit/Field Name Type Reset 3 DATACK RO 0 Description Acknowledge Data This bit specifies the result of the last data operation. If set, the transmitted data was not acknowledged; otherwise, the data was acknowledged. 2 ADRACK RO 0 Acknowledge Address This bit specifies the result of the last address operation. If set, the transmitted address was not acknowledged; otherwise, the address was acknowledged.
PAGE 533
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset 0 RUN WO 0 Description I2C Master Enable When set, allows the master to send or receive data. See field decoding in Table 14-5 on page 533. Table 14-5. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) Current I2CMSA[0] State R/S Idle I2CMCS[3:0] ACK STOP START RUN 1 0 X a 0 1 0 X 1 1 1 START condition followed by a SEND and STOP condition (master remains in Idle state).
PAGE 534
NRND: Not recommended for new designs. Inter-Integrated Circuit (I2C) Interface Table 14-5. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) (continued) Current I2CMSA[0] State R/S I2CMCS[3:0] Description ACK STOP START RUN X 0 0 0 1 RECEIVE operation with negative ACK (master remains in Master Receive state). X X 1 0 0 STOP condition (master goes to Idle state). X 0 1 0 1 RECEIVE followed by STOP condition (master goes to Idle state).
PAGE 535
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 3: I2C Master Data (I2CMDR), offset 0x008 Important: This register is read-sensitive. See the register description for details. This register contains the data to be transmitted when in the Master Transmit state, and the data received when in the Master Receive state. I2C Master Data (I2CMDR) I2C 0 base: 0x4002.0000 Offset 0x008 Type R/W, reset 0x0000.
PAGE 536
NRND: Not recommended for new designs. Inter-Integrated Circuit (I2C) Interface Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C This register specifies the period of the SCL clock. Caution – Take care not to set bit 7 when accessing this register as unpredictable behavior can occur. I2C Master Timer Period (I2CMTPR) I2C 0 base: 0x4002.0000 Offset 0x00C Type R/W, reset 0x0000.
PAGE 537
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010 This register controls whether a raw interrupt is promoted to a controller interrupt. I2C Master Interrupt Mask (I2CMIMR) I2C 0 base: 0x4002.0000 Offset 0x010 Type R/W, reset 0x0000.
PAGE 538
NRND: Not recommended for new designs. Inter-Integrated Circuit (I2C) Interface Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 This register specifies whether an interrupt is pending. I2C Master Raw Interrupt Status (I2CMRIS) I2C 0 base: 0x4002.0000 Offset 0x014 Type RO, reset 0x0000.
PAGE 539
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 This register specifies whether an interrupt was signaled. I2C Master Masked Interrupt Status (I2CMMIS) I2C 0 base: 0x4002.0000 Offset 0x018 Type RO, reset 0x0000.
PAGE 540
NRND: Not recommended for new designs. Inter-Integrated Circuit (I2C) Interface Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C This register clears the raw interrupt. I2C Master Interrupt Clear (I2CMICR) I2C 0 base: 0x4002.0000 Offset 0x01C Type WO, reset 0x0000.
PAGE 541
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 9: I2C Master Configuration (I2CMCR), offset 0x020 This register configures the mode (Master or Slave) and sets the interface for test mode loopback. I2C Master Configuration (I2CMCR) I2C 0 base: 0x4002.0000 Offset 0x020 Type R/W, reset 0x0000.
PAGE 542
NRND: Not recommended for new designs. Inter-Integrated Circuit (I2C) Interface 14.7 Register Descriptions (I2C Slave) The remainder of this section lists and describes the I2C slave registers, in numerical order by address offset. See also “Register Descriptions (I2C Master)” on page 529.
PAGE 543
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 10: I2C Slave Own Address (I2CSOAR), offset 0x800 This register consists of seven address bits that identify the Stellaris I2C device on the I2C bus. I2C Slave Own Address (I2CSOAR) I2C 0 base: 0x4002.0000 Offset 0x800 Type R/W, reset 0x0000.
PAGE 544
NRND: Not recommended for new designs. Inter-Integrated Circuit (I2C) Interface Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x804 This register accesses one control bit when written, and three status bits when read. The read-only Status register consists of three bits: the FBR, RREQ, and TREQ bits. The First Byte Received (FBR) bit is set only after the Stellaris device detects its own slave address and receives the first data byte from the I2C master.
PAGE 545
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Writes I2C Slave Control/Status (I2CSCSR) I2C 0 base: 0x4002.0000 Offset 0x804 Type WO, reset 0x0000.
PAGE 546
NRND: Not recommended for new designs. Inter-Integrated Circuit (I2C) Interface Register 12: I2C Slave Data (I2CSDR), offset 0x808 Important: This register is read-sensitive. See the register description for details. This register contains the data to be transmitted when in the Slave Transmit state, and the data received when in the Slave Receive state. I2C Slave Data (I2CSDR) I2C 0 base: 0x4002.0000 Offset 0x808 Type R/W, reset 0x0000.
PAGE 547
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x80C This register controls whether a raw interrupt is promoted to a controller interrupt. I2C Slave Interrupt Mask (I2CSIMR) I2C 0 base: 0x4002.0000 Offset 0x80C Type R/W, reset 0x0000.
PAGE 548
NRND: Not recommended for new designs. Inter-Integrated Circuit (I2C) Interface Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x810 This register specifies whether an interrupt is pending. I2C Slave Raw Interrupt Status (I2CSRIS) I2C 0 base: 0x4002.0000 Offset 0x810 Type RO, reset 0x0000.
PAGE 549
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x814 This register specifies whether an interrupt was signaled. I2C Slave Masked Interrupt Status (I2CSMIS) I2C 0 base: 0x4002.0000 Offset 0x814 Type RO, reset 0x0000.
PAGE 550
NRND: Not recommended for new designs. Inter-Integrated Circuit (I2C) Interface Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x818 This register clears the raw interrupt. A read of this register returns no meaningful data. I2C Slave Interrupt Clear (I2CSICR) I2C 0 base: 0x4002.0000 Offset 0x818 Type WO, reset 0x0000.
PAGE 551
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 15 Controller Area Network (CAN) Module Controller Area Network (CAN) is a multicast, shared serial bus standard for connecting electronic control units (ECUs). CAN was specifically designed to be robust in electromagnetically-noisy environments and can utilize a differential balanced line like RS-485 or a more robust twisted-pair wire.
PAGE 552
NRND: Not recommended for new designs. Controller Area Network (CAN) Module 15.1 Block Diagram Figure 15-1.
PAGE 553
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 15-1. Controller Area Network Signals (100LQFP) Pin Name Pin Number CAN0Rx CAN0Tx a Pin Type Buffer Type Description 10 I TTL CAN module 0 receive. 11 O TTL CAN module 0 transmit. a. The TTL designation indicates the pin has TTL-compatible voltage levels. Table 15-2. Controller Area Network Signals (108BGA) a Pin Name Pin Number Pin Type Buffer Type Description CAN0Rx G1 I TTL CAN module 0 receive.
PAGE 554
NRND: Not recommended for new designs. Controller Area Network (CAN) Module The protocol controller transfers and receives the serial data from the CAN bus and passes the data on to the message handler. The message handler then loads this information into the appropriate message object based on the current filtering and identifiers in the message object memory. The message handler is also responsible for generating interrupts based on events on the CAN bus.
PAGE 555
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller (CANIFnCRQ) register. The whole message (including all arbitration bits, data-length code, and eight data bytes) is stored in the message object. If the Identifier Mask (the MSK bits in the CAN IFn Mask 1 and CAN IFn Mask 2 (CANIFnMSKn) registers) is used, the arbitration bits that are masked to "don't care" may be overwritten in the message object.
PAGE 556
NRND: Not recommended for new designs. Controller Area Network (CAN) Module 1.
PAGE 557
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller ■ Set the EOB bit for a single message object; ■ Set the DLC[3:0] field to specify the size of the data frame. Take care during this configuration not to set the NEWDAT, MSGLST, INTPND or TXRQST bits. 7. Load the data to be transmitted into the CAN IFn Data (CANIFnDA1, CANIFnDA2, CANIFnDB1, CANIFnDB2) or (CANIFnDATAA and CANIFnDATAB) registers. Byte 0 of the CAN data frame is stored in DATA[7:0] in the CANIFnDA1 register. 8.
PAGE 558
NRND: Not recommended for new designs. Controller Area Network (CAN) Module are all stored into the corresponding message object. In this manner, the data bytes are connected with the identifier even if arbitration masks are used. The NEWDAT bit of the CANIFnMCTL register is set to indicate that new data has been received. The CPU should clear this bit when it reads the message object to indicate to the controller that the message has been received, and the buffer is free to receive more messages.
PAGE 559
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 15.3.10 Configuring a Receive Message Object The following steps illustrate how to configure a receive message object. 1. Program the CAN IFn Command Mask (CANIFnCMASK) register as described in the “Configuring a Transmit Message Object” on page 555 section, except that the WRNRD bit is set to specify a write to the message RAM. 2.
PAGE 560
NRND: Not recommended for new designs. Controller Area Network (CAN) Module CANIFnMSKn register to filter which frames are received. The MXTD bit in the CANIFnMSK2 register should be set if only 29-bit extended identifiers are expected by this message object. 15.3.11 Handling of Received Message Objects The CPU may read a received message any time via the CAN Interface registers because the data consistency is guaranteed by the message handler state machine.
PAGE 561
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 15.3.11.3 Reading from a FIFO Buffer When the CPU transfers the contents of a message object from a FIFO buffer by writing its number to the CANIFnCRQ, the TXRQST and CLRINTPND bits in the CANIFnCMSK register should be set such that the NEWDAT and INTPEND bits in the CANIFnMCTL register are cleared after the read.
PAGE 562
NRND: Not recommended for new designs. Controller Area Network (CAN) Module Figure 15-3.
PAGE 563
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 15.3.12 Handling of Interrupts If several interrupts are pending, the CAN Interrupt (CANINT) register points to the pending interrupt with the highest priority, disregarding their chronological order. The status interrupt has the highest priority. Among the message interrupts, the message object's interrupt with the lowest message number has the highest priority.
PAGE 564
NRND: Not recommended for new designs. Controller Area Network (CAN) Module or active error flag), the bit is rerouted internally so that the CAN Controller monitors this dominant bit, although the CAN bus remains in recessive state. 15.3.13.2 Loopback Mode Loopback mode is useful for self-test functions.
PAGE 565
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller ■ CANnTX drives a high value The last two functions, combined with the readable CAN receive pin CANnRX, can be used to check the physical layer of the CAN bus. The Transmit Control function is enabled by programming the TX[1:0] field in the CANTST register. The three test functions for the CANnTX signal interfere with all CAN protocol functions.
PAGE 566
NRND: Not recommended for new designs. Controller Area Network (CAN) Module A given bit rate may be met by different bit-time configurations, but for the proper function of the CAN network, the physical delay times and the oscillator's tolerance range have to be considered. Figure 15-4. CAN Bit Time Nominal CAN Bit Time a b TSEG1 Sync Prop TSEG2 Phase1 c 1 Time Quantum q) (tq Phase2 Sample Point a. TSEG1 = Prop + Phase1 b. TSEG2 = Phase2 c. Phase1 = Phase2 or Phase1 + 1 = Phase2 a Table 15-3.
PAGE 567
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller [Sync + Prop + Phase1 + Phase2] × tq The data in the CANBIT register is the configuration input of the CAN protocol controller. The baud rate prescaler (configured by the BRP field) defines the length of the time quantum, the basic time unit of the bit time; the bit timing logic (configured by TSEG1, TSEG2, and SJW) defines the number of time quanta in the bit time.
PAGE 568
NRND: Not recommended for new designs.
PAGE 569
NRND: Not recommended for new designs.
PAGE 570
NRND: Not recommended for new designs.
PAGE 571
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 15-5. CAN Register Map (continued) Description See page Offset Name Type Reset 0x020 CANIF1CRQ R/W 0x0000.0001 CAN IF1 Command Request 583 0x024 CANIF1CMSK R/W 0x0000.0000 CAN IF1 Command Mask 584 0x028 CANIF1MSK1 R/W 0x0000.FFFF CAN IF1 Mask 1 586 0x02C CANIF1MSK2 R/W 0x0000.FFFF CAN IF1 Mask 2 587 0x030 CANIF1ARB1 R/W 0x0000.0000 CAN IF1 Arbitration 1 588 0x034 CANIF1ARB2 R/W 0x0000.
PAGE 572
NRND: Not recommended for new designs. Controller Area Network (CAN) Module 15.5 CAN Register Descriptions The remainder of this section lists and describes the CAN registers, in numerical order by address offset. There are two sets of Interface Registers that are used to access the Message Objects in the Message RAM: CANIF1x and CANIF2x. The function of the two sets are identical and are used to queue transactions.
PAGE 573
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 1: CAN Control (CANCTL), offset 0x000 This control register initializes the module and enables test mode and interrupts. The bus-off recovery sequence (see CAN Specification Rev. 2.0) cannot be shortened by setting or clearing INIT. If the device goes bus-off, it sets INIT, stopping all bus activities.
PAGE 574
NRND: Not recommended for new designs. Controller Area Network (CAN) Module Bit/Field Name Type Reset 2 SIE R/W 0 Description Status Interrupt Enable 0: Disabled. No status interrupt is generated. 1: Enabled. An interrupt is generated when a message has successfully been transmitted or received, or a CAN bus error has been detected. A change in the TXOK, RXOK or LEC bits in the CANSTS register generates an interrupt. 1 IE R/W 0 CAN Interrupt Enable 0: Interrupts disabled.
PAGE 575
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 2: CAN Status (CANSTS), offset 0x004 Important: This register is read-sensitive. See the register description for details. The status register contains information for interrupt servicing such as Bus-Off, error count threshold, and error types. The LEC field holds the code that indicates the type of the last error to occur on the CAN bus.
PAGE 576
NRND: Not recommended for new designs. Controller Area Network (CAN) Module Bit/Field Name Type Reset 4 RXOK R/W 0 Description Received a Message Successfully 0: Since this bit was last cleared, no message has been successfully received. 1: Since this bit was last cleared, a message has been successfully received, independent of the result of the acceptance filtering. This bit is never cleared by the CAN module.
PAGE 577
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 3: CAN Error Counter (CANERR), offset 0x008 This register contains the error counter values, which can be used to analyze the cause of an error. CAN Error Counter (CANERR) CAN0 base: 0x4004.0000 Offset 0x008 Type RO, reset 0x0000.
PAGE 578
NRND: Not recommended for new designs. Controller Area Network (CAN) Module Register 4: CAN Bit Timing (CANBIT), offset 0x00C This register is used to program the bit width and bit quantum. Values are programmed to the system clock frequency. This register is write-enabled by setting the CCE and INIT bits in the CANCTL register. See “Bit Time and Bit Rate” on page 565 for more information. CAN Bit Timing (CANBIT) CAN0 base: 0x4004.0000 Offset 0x00C Type R/W, reset 0x0000.
PAGE 579
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 5: CAN Interrupt (CANINT), offset 0x010 This register indicates the source of the interrupt. If several interrupts are pending, the CAN Interrupt (CANINT) register points to the pending interrupt with the highest priority, disregarding the order in which the interrupts occurred. An interrupt remains pending until the CPU has cleared it.
PAGE 580
NRND: Not recommended for new designs. Controller Area Network (CAN) Module Register 6: CAN Test (CANTST), offset 0x014 This is the test mode register for self-test and external pin access. It is write-enabled by setting the TEST bit in the CANCTL register. Different test functions may be combined, however, CAN transfers will be affected if the TX bits in this register are not zero. CAN Test (CANTST) CAN0 base: 0x4004.0000 Offset 0x014 Type R/W, reset 0x0000.
PAGE 581
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset Description 3 SILENT R/W 0 Silent Mode Do not transmit data; monitor the bus. Also known as Bus Monitor mode. 0: Disabled. 1: Enabled. 2 BASIC R/W 0 Basic Mode 0: Disabled. 1: Use CANIF1 registers as transmit buffer, and use CANIF2 registers as receive buffer. 1:0 reserved RO 0x0 Software should not rely on the value of a reserved bit.
PAGE 582
NRND: Not recommended for new designs. Controller Area Network (CAN) Module Register 7: CAN Baud Rate Prescaler Extension (CANBRPE), offset 0x018 This register is used to further divide the bit time set with the BRP bit in the CANBIT register. It is write-enabled by setting the CCE bit in the CANCTL register. CAN Baud Rate Prescaler Extension (CANBRPE) CAN0 base: 0x4004.0000 Offset 0x018 Type R/W, reset 0x0000.
PAGE 583
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 8: CAN IF1 Command Request (CANIF1CRQ), offset 0x020 Register 9: CAN IF2 Command Request (CANIF2CRQ), offset 0x080 A message transfer is started as soon as there is a write of the message object number to the MNUM field when the TXRQST bit in the CANIF1MCTL register is set.
PAGE 584
NRND: Not recommended for new designs. Controller Area Network (CAN) Module Register 10: CAN IF1 Command Mask (CANIF1CMSK), offset 0x024 Register 11: CAN IF2 Command Mask (CANIF2CMSK), offset 0x084 Reading the Command Mask registers provides status for various functions. Writing to the Command Mask registers specifies the transfer direction and selects which buffer registers are the source or target of the data transfer.
PAGE 585
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset 3 CLRINTPND R/W 0 Description Clear Interrupt Pending Bit If WRNRD is set, this bit controls whether the INTPND bit in the CANIFnMCTL register is changed. 0: The INTPND bit in the message object remains unchanged. 1: The INTPND bit is cleared in the message object.
PAGE 586
NRND: Not recommended for new designs. Controller Area Network (CAN) Module Register 12: CAN IF1 Mask 1 (CANIF1MSK1), offset 0x028 Register 13: CAN IF2 Mask 1 (CANIF2MSK1), offset 0x088 The mask information provided in this register accompanies the data (CANIFnDAn), arbitration information (CANIFnARBn), and control information (CANIFnMCTL) to the message object in the message RAM. The mask is used with the ID bit in the CANIFnARBn register for acceptance filtering.
PAGE 587
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 14: CAN IF1 Mask 2 (CANIF1MSK2), offset 0x02C Register 15: CAN IF2 Mask 2 (CANIF2MSK2), offset 0x08C This register holds extended mask information that accompanies the CANIFnMSK1 register. CAN IF1 Mask 2 (CANIF1MSK2) CAN0 base: 0x4004.0000 Offset 0x02C Type R/W, reset 0x0000.
PAGE 588
NRND: Not recommended for new designs. Controller Area Network (CAN) Module Register 16: CAN IF1 Arbitration 1 (CANIF1ARB1), offset 0x030 Register 17: CAN IF2 Arbitration 1 (CANIF2ARB1), offset 0x090 These registers hold the identifiers for acceptance filtering. CAN IF1 Arbitration 1 (CANIF1ARB1) CAN0 base: 0x4004.0000 Offset 0x030 Type R/W, reset 0x0000.
PAGE 589
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 18: CAN IF1 Arbitration 2 (CANIF1ARB2), offset 0x034 Register 19: CAN IF2 Arbitration 2 (CANIF2ARB2), offset 0x094 These registers hold information for acceptance filtering. CAN IF1 Arbitration 2 (CANIF1ARB2) CAN0 base: 0x4004.0000 Offset 0x034 Type R/W, reset 0x0000.
PAGE 590
NRND: Not recommended for new designs. Controller Area Network (CAN) Module Bit/Field Name Type Reset Description 12:0 ID R/W 0x000 Message Identifier This bit field is used with the ID field in the CANIFnARB2 register to create the message identifier. When using a 29-bit identifier, ID[15:0] of the CANIFnARB1 register are [15:0] of the ID, while these bits, ID[12:0], are [28:16] of the ID. When using an 11-bit identifier, ID[12:2] are used for bits [10:0] of the ID.
PAGE 591
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 20: CAN IF1 Message Control (CANIF1MCTL), offset 0x038 Register 21: CAN IF2 Message Control (CANIF2MCTL), offset 0x098 This register holds the control information associated with the message object to be sent to the Message RAM. CAN IF1 Message Control (CANIF1MCTL) CAN0 base: 0x4004.0000 Offset 0x038 Type R/W, reset 0x0000.
PAGE 592
NRND: Not recommended for new designs. Controller Area Network (CAN) Module Bit/Field Name Type Reset 11 TXIE R/W 0 Description Transmit Interrupt Enable 0: The INTPND bit in the CANIFnMCTL register is unchanged after a successful transmission of a frame. 1: The INTPND bit in the CANIFnMCTL register is set after a successful transmission of a frame. 10 RXIE R/W 0 Receive Interrupt Enable 0: The INTPND bit in the CANIFnMCTL register is unchanged after a successful reception of a frame.
PAGE 593
NRND: Not recommended for new designs.
PAGE 594
NRND: Not recommended for new designs. Controller Area Network (CAN) Module Register 30: CAN Transmission Request 1 (CANTXRQ1), offset 0x100 Register 31: CAN Transmission Request 2 (CANTXRQ2), offset 0x104 The CANTXRQ1 and CANTXRQ2 registers hold the TXRQST bits of the 32 message objects. By reading out these bits, the CPU can check which message object has a transmission request pending.
PAGE 595
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 32: CAN New Data 1 (CANNWDA1), offset 0x120 Register 33: CAN New Data 2 (CANNWDA2), offset 0x124 The CANNWDA1 and CANNWDA2 registers hold the NEWDAT bits of the 32 message objects. By reading these bits, the CPU can check which message object has its data portion updated.
PAGE 596
NRND: Not recommended for new designs. Controller Area Network (CAN) Module Register 34: CAN Message 1 Interrupt Pending (CANMSG1INT), offset 0x140 Register 35: CAN Message 2 Interrupt Pending (CANMSG2INT), offset 0x144 The CANMSG1INT and CANMSG2INT registers hold the INTPND bits of the 32 message objects. By reading these bits, the CPU can check which message object has an interrupt pending.
PAGE 597
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 36: CAN Message 1 Valid (CANMSG1VAL), offset 0x160 Register 37: CAN Message 2 Valid (CANMSG2VAL), offset 0x164 The CANMSG1VAL and CANMSG2VAL registers hold the MSGVAL bits of the 32 message objects. By reading these bits, the CPU can check which message object is valid. The message value of a specific message object can be changed with the CANIFnMCTL register.
PAGE 598
NRND: Not recommended for new designs. Ethernet Controller 16 Ethernet Controller ® The Stellaris Ethernet Controller consists of a fully integrated media access controller (MAC) and network physical (PHY) interface. The Ethernet Controller conforms to IEEE 802.3 specifications and fully supports 10BASE-T and 100BASE-TX standards. The Stellaris Ethernet Controller module has the following features: ■ Conforms to the IEEE 802.3-2002 specification – 10BASE-T/100BASE-TX IEEE-802.3 compliant.
PAGE 599
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Figure 16-1. Ethernet Controller Ethernet Media Controller Physical Access Layer Entity Controller ARM Cortex M3 MAC (Layer 2) Magnetics RJ45 PHY (Layer 1) Figure 16-2 on page 599 shows more detail of the internal structure of the Ethernet Controller and how the register set relates to various functions. Figure 16-2.
PAGE 600
NRND: Not recommended for new designs. Ethernet Controller Table 16-1. Ethernet Signals (100LQFP) a Pin Name Pin Number Pin Type Buffer Type Description ERBIAS 41 I Analog 12.4-kΩ resistor (1% precision) used internally for Ethernet PHY. GNDPHY 42 85 86 - Power GND of the Ethernet PHY. LED0 59 O TTL Ethernet LED 0. LED1 60 O TTL Ethernet LED 1. MDIO 58 I/O TTL MDIO of the Ethernet PHY. RXIN 37 I Analog RXIN of the Ethernet PHY.
PAGE 601
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 16.3 Functional Description Note: A 12.4-kΩ resistor should be connected between the ERBIAS and ground. The 12.4-kΩ resistor should have a 1% tolerance and should be located in close proximity to the ERBIAS pin. Power dissipation in the resistor is low, so a chip resistor of any geometry may be used. The functional description of the Ethernet Controller is discussed in the following sections. 16.3.
PAGE 602
NRND: Not recommended for new designs. Ethernet Controller value of the Length/Type field is greater than 1500 decimal. The definition of the Type field is specified in the IEEE 802.3 standard. The first of the two octets in this field is most significant. ■ Data The data field is a sequence of octets that is at least 46 in length, up to 1500 in length. Full data transparency is provided so any values can appear in this field. A minimum frame size of 46 octets is required to meet the IEEE standard.
PAGE 603
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 16-3.
PAGE 604
NRND: Not recommended for new designs. Ethernet Controller 16.3.1.4 Ethernet Reception Options The Ethernet Controller RX FIFO should be cleared during software initialization. The receiver should first be disabled by clearing the RXEN bit in the Ethernet MAC Receive Control (MACRCTL) register, then the FIFO can be cleared by setting the RSTFIFO bit in the MACRCTL register. The receiver automatically rejects frames that contain bad CRC values in the FCS field.
PAGE 605
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller and XTALNPHY pins. Alternatively, an external 25-MHz clock input can be connected to the XTALPPHY pin. In this mode of operation, a crystal is not required and the XTALNPHY pin must be tied to ground. 16.3.3.2 Auto-Negotiation The Ethernet Controller supports the auto-negotiation functions of Clause 28 of the IEEE 802.3 standard for 10/100 Mbps operation over copper wiring. This function is controlled via register settings.
PAGE 606
NRND: Not recommended for new designs. Ethernet Controller 16.3.3.6 LED Indicators The Ethernet Controller supports two LED signals that can be used to indicate various states of operation. These signals are mapped to the LED0 and LED1 pins. By default, these pins are configured as GPIO signals (PF3 and PF2). For the PHY layer to drive these signals, they must be reconfigured to their alternate function. See “General-Purpose Input/Outputs (GPIOs)” on page 289 for additional details.
PAGE 607
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Figure 16-4. Interface to an Ethernet Jack Stellaris Microcontroller PF2/LED1 PF3/LED0 MDIO TXOP 60 59 PF2/LED1 PF3/LED0 +3.3V 10/100BASE-T Ethernet Jack P2 58 R3 +3.3V +3.3V R4 49.9 10K R5 49.9 C2 10pF C3 10pF 43 12 11 R6 330 C4 3 G+ G- 1CT: 1 +3.3V TX+ 1 TX- 2 5 TXON RXIP 0.1UF 46 RX+ 3 4 4 7 40 C5 5 RX- 6 1CT: 1 +3.3V 7 6 8 RXIN 0.1UF 37 +3.3V R8 49.9 R9 49.9 C6 10pF C7 10pF R7 8 +3.
PAGE 608
NRND: Not recommended for new designs. Ethernet Controller 4. Program the MACRCTL register to flush the receive FIFO and reject frames with bad FCS using a value of 0x18. 5. Enable both the Transmitter and Receive by setting the LSB in both the MACTCTL and MACRCTL registers. 6. To transmit a frame, write the frame into the TX FIFO using the Ethernet MAC Data (MACDATA) register. Then set the NEWTX bit in the Ethernet Mac Transmission Request (MACTR) register to initiate the transmit process.
PAGE 609
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 16-4. Ethernet Register Map (continued) Description See page Offset Name Type Reset 0x024 MACMDV R/W 0x0000.0080 Ethernet MAC Management Divider 623 0x02C MACMTXD R/W 0x0000.0000 Ethernet MAC Management Transmit Data 624 0x030 MACMRXD R/W 0x0000.0000 Ethernet MAC Management Receive Data 625 0x034 MACNP RO 0x0000.0000 Ethernet MAC Number of Packets 626 0x038 MACTR R/W 0x0000.
PAGE 610
NRND: Not recommended for new designs. Ethernet Controller Register 1: Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK), offset 0x000 The MACRIS/MACIACK register is the interrupt status and acknowledge register. On a read, this register gives the current status value of the corresponding interrupt prior to masking. On a write, setting any bit clears the corresponding interrupt status bit. Reads Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK) Base 0x4004.
PAGE 611
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset 2 TXEMP RO 0 Description Transmit FIFO Empty When set, indicates that the packet was transmitted and that the TX FIFO is empty. 1 TXER RO 0 Transmit Error When set, indicates that an error was encountered on the transmitter.
PAGE 612
NRND: Not recommended for new designs. Ethernet Controller Bit/Field Name Type Reset 2 TXEMP W1C 0 Description Clear Transmit FIFO Empty Setting this bit clears the TXEMP interrupt in the MACRIS register. 1 TXER W1C 0 Clear Transmit Error Setting this bit clears the TXER interrupt in the MACRIS register and resets the TX FIFO write pointer. 0 RXINT W1C 0 Clear Packet Received Setting this bit clears the RXINT interrupt in the MACRIS register.
PAGE 613
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 2: Ethernet MAC Interrupt Mask (MACIM), offset 0x004 This register allows software to enable/disable Ethernet MAC interrupts. Clearing a bit disables the interrupt, while setting the bit enables it. Ethernet MAC Interrupt Mask (MACIM) Base 0x4004.8000 Offset 0x004 Type R/W, reset 0x0000.
PAGE 614
NRND: Not recommended for new designs. Ethernet Controller Register 3: Ethernet MAC Receive Control (MACRCTL), offset 0x008 This register configures the receiver and controls the types of frames that are received. It is important to note that when the receiver is enabled, all valid frames with a broadcast address of FF-FF-FF-FF-FF-FF in the Destination Address field are received and stored in the RX FIFO, even if the AMUL bit is not set. Ethernet MAC Receive Control (MACRCTL) Base 0x4004.
PAGE 615
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 4: Ethernet MAC Transmit Control (MACTCTL), offset 0x00C This register configures the transmitter and controls the frames that are transmitted. Ethernet MAC Transmit Control (MACTCTL) Base 0x4004.8000 Offset 0x00C Type R/W, reset 0x0000.
PAGE 616
NRND: Not recommended for new designs. Ethernet Controller Register 5: Ethernet MAC Data (MACDATA), offset 0x010 Important: This register is read-sensitive. See the register description for details. This register enables software to access the TX and RX FIFOs. Reads from this register return the data stored in the RX FIFO from the location indicated by the read pointer. The read pointer is then auto incremented to the next RX FIFO location.
PAGE 617
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Writes Ethernet MAC Data (MACDATA) Base 0x4004.8000 Offset 0x010 Type WO, reset 0x0000.
PAGE 618
NRND: Not recommended for new designs. Ethernet Controller Register 6: Ethernet MAC Individual Address 0 (MACIA0), offset 0x014 This register enables software to program the first four bytes of the hardware MAC address of the Network Interface Card (NIC). (The last two bytes are in MACIA1). The 6-byte Individual Address is compared against the incoming Destination Address fields to determine whether the frame should be received. Ethernet MAC Individual Address 0 (MACIA0) Base 0x4004.
PAGE 619
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 7: Ethernet MAC Individual Address 1 (MACIA1), offset 0x018 This register enables software to program the last two bytes of the hardware MAC address of the Network Interface Card (NIC). (The first four bytes are in MACIA0). The 6-byte IAR is compared against the incoming Destination Address fields to determine whether the frame should be received. Ethernet MAC Individual Address 1 (MACIA1) Base 0x4004.
PAGE 620
NRND: Not recommended for new designs. Ethernet Controller Register 8: Ethernet MAC Threshold (MACTHR), offset 0x01C In order to increase the transmission rate, it is possible to program the Ethernet Controller to begin transmission of the next frame prior to the completion of the transmission of the current frame. Note: Extreme care must be used when implementing this function.
PAGE 621
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset Description 5:0 THRESH R/W 0x3F Threshold Value The THRESH bits represent the early transmit threshold. Once the amount of data in the TX FIFO exceeds the value represented by the above equation, transmission of the packet begins.
PAGE 622
NRND: Not recommended for new designs. Ethernet Controller Register 9: Ethernet MAC Management Control (MACMCTL), offset 0x020 This register enables software to control the transfer of data to and from the MII Management registers in the Ethernet PHY layer. The address, name, type, reset configuration, and functional description of each of these registers can be found in Table 16-4 on page 608 and in “MII Management Register Descriptions” on page 628.
PAGE 623
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 10: Ethernet MAC Management Divider (MACMDV), offset 0x024 This register enables software to set the clock divider for the Management Data Clock (MDC). This clock is used to synchronize read and write transactions between the system and the MII Management registers.
PAGE 624
NRND: Not recommended for new designs. Ethernet Controller Register 11: Ethernet MAC Management Transmit Data (MACMTXD), offset 0x02C This register holds the next value to be written to the MII Management registers. Ethernet MAC Management Transmit Data (MACMTXD) Base 0x4004.8000 Offset 0x02C Type R/W, reset 0x0000.
PAGE 625
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 12: Ethernet MAC Management Receive Data (MACMRXD), offset 0x030 This register holds the last value read from the MII Management registers. Ethernet MAC Management Receive Data (MACMRXD) Base 0x4004.8000 Offset 0x030 Type R/W, reset 0x0000.
PAGE 626
NRND: Not recommended for new designs. Ethernet Controller Register 13: Ethernet MAC Number of Packets (MACNP), offset 0x034 This register holds the number of frames that are currently in the RX FIFO. When NPR is 0, there are no frames in the RX FIFO, and the RXINT bit is clear. When NPR is any other value, at least one frame is in the RX FIFO, and the RXINT bit in the MACRIS register is set. Note: The FCS bytes are not included in the NPR value.
PAGE 627
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 14: Ethernet MAC Transmission Request (MACTR), offset 0x038 This register enables software to initiate the transmission of the frame currently located in the TX FIFO. Once the frame has been transmitted from the TX FIFO or a transmission error has been encountered, the NEWTX bit is automatically cleared. Ethernet MAC Transmission Request (MACTR) Base 0x4004.8000 Offset 0x038 Type R/W, reset 0x0000.
PAGE 628
NRND: Not recommended for new designs. Ethernet Controller Register 15: Ethernet MAC Timer Support (MACTS), offset 0x03C This register enables software to enable highly precise timing on the transmission and reception of frames. To enable this function, set the TSEN bit. Ethernet MAC Timer Support (MACTS) Base 0x4004.8000 Offset 0x03C Type R/W, reset 0x0000.
PAGE 629
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 16: Ethernet PHY Management Register 0 – Control (MR0), address 0x00 This register enables software to configure the operation of the PHY layer. The default settings of these registers are designed to initialize the Ethernet Controller to a normal operational mode without configuration. Ethernet PHY Management Register 0 – Control (MR0) Base 0x4004.
PAGE 630
NRND: Not recommended for new designs. Ethernet Controller Bit/Field Name Type Reset 8 DUPLEX R/W 1 Description Set Duplex Mode Value Description 7 COLT R/W 0 1 Enables the Full-Duplex mode of operation. This bit can be set by software in a manual configuration process or by the auto-negotiation process. 0 Enables the Half-Duplex mode of operation. Collision Test When set, this bit enables the Collision Test mode of operation.
PAGE 631
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 17: Ethernet PHY Management Register 1 – Status (MR1), address 0x01 This register enables software to determine the capabilities of the PHY layer and perform its initialization and operation appropriately. Ethernet PHY Management Register 1 – Status (MR1) Base 0x4004.
PAGE 632
NRND: Not recommended for new designs. Ethernet Controller Bit/Field Name Type Reset Description 2 LINK RO 0 Link Made When set, this bit indicates that a valid link has been established by the Ethernet Controller. 1 JAB RC 0 Jabber Condition When set, this bit indicates that a jabber condition has been detected by the Ethernet Controller. This bit remains set until it is read, even if the jabber condition no longer exists.
PAGE 633
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 18: Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2), address 0x02 This register, along with MR3, provides a 32-bit value indicating the manufacturer, model, and revision information. Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2) Base 0x4004.
PAGE 634
NRND: Not recommended for new designs. Ethernet Controller Register 19: Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3), address 0x03 This register, along with MR2, provides a 32-bit value indicating the manufacturer, model, and revision information. Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3) Base 0x4004.
PAGE 635
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 20: Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4), address 0x04 This register provides the advertised abilities of the Ethernet Controller used during auto-negotiation. Bits 8:5 represent the Technology Ability Field bits. This field can be overwritten by software to auto-negotiate to an alternate common technology.
PAGE 636
NRND: Not recommended for new designs. Ethernet Controller Bit/Field Name Type Reset 5 A0 R/W 1 Description Technology Ability Field[0] When set, this bit indicates that the Ethernet Controller supports the 10BASE-T half-duplex signaling protocol. If software wants to ensure that this mode is not used, this bit can be cleared and auto-negotiation re-initiated with the RANEG bit in the MR0 register..
PAGE 637
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 21: Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability (MR5), address 0x05 This register provides the advertised abilities of the link partner’s Ethernet Controller that are received and stored during auto-negotiation. Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability (MR5) Base 0x4004.
PAGE 638
NRND: Not recommended for new designs. Ethernet Controller Register 22: Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6), address 0x06 This register enables software to determine the auto-negotiation and next page capabilities of the Ethernet Controller and the link partner after auto-negotiation. Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6) Base 0x4004.
PAGE 639
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 23: Ethernet PHY Management Register 16 – Vendor-Specific (MR16), address 0x10 This register enables software to configure the operation of vendor-specific modes of the Ethernet Controller. Ethernet PHY Management Register 16 – Vendor-Specific (MR16) Base 0x4004.
PAGE 640
NRND: Not recommended for new designs. Ethernet Controller Bit/Field Name Type Reset 5 APOL R/W 0 Description Auto-Polarity Disable When set, this bit disables the Ethernet Controller’s auto-polarity function. If this bit is clear, the Ethernet Controller automatically inverts the received signal due to a wrong polarity connection during auto-negotiation when in 10BASE-T mode. 4 RVSPOL R/W 0 Receive Data Polarity This bit indicates whether the receive data pulses are being inverted.
PAGE 641
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 24: Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17), address 0x11 This register provides the means for controlling and observing the events which trigger a PHY layer interrupt in the MACRIS register. This register can also be used in a polling mode via the Media Independent Interface as a means to observe key events within the PHY layer via one register address.
PAGE 642
NRND: Not recommended for new designs. Ethernet Controller Bit/Field Name Type Reset 6 RXER_INT RC 0 Description Receive Error Interrupt When set, this bit indicates that a receive error has been detected by the Ethernet Controller. 5 PRX_INT RC 0 Page Receive Interrupt When set, this bit indicates that a new page has been received from the link partner during auto-negotiation.
PAGE 643
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 25: Ethernet PHY Management Register 18 – Diagnostic (MR18), address 0x12 This register enables software to diagnose the results of the previous auto-negotiation. Ethernet PHY Management Register 18 – Diagnostic (MR18) Base 0x4004.
PAGE 644
NRND: Not recommended for new designs. Ethernet Controller Register 26: Ethernet PHY Management Register 19 – Transceiver Control (MR19), address 0x13 This register enables software to set the gain of the transmit output to compensate for transformer loss. Ethernet PHY Management Register 19 – Transceiver Control (MR19) Base 0x4004.
PAGE 645
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 27: Ethernet PHY Management Register 23 – LED Configuration (MR23), address 0x17 This register enables software to select the source that causes the LED1 and LED0 signals to toggle. Ethernet PHY Management Register 23 – LED Configuration (MR23) Base 0x4004.
PAGE 646
NRND: Not recommended for new designs. Ethernet Controller Register 28: Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24), address 0x18 This register enables software to control the behavior of the MDI/MDIX mux and its switching capabilities. Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24) Base 0x4004.
PAGE 647
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 17 Analog Comparator An analog comparator is a peripheral that compares two analog voltages, and provides a logical output that signals the comparison result. Note: Not all comparators have the option to drive an output pin.
PAGE 648
NRND: Not recommended for new designs. Analog Comparator bit in the GPIO Alternate Function Select (GPIOAFSEL) register (page 311) should be set to choose the Analog Comparator function. The positive and negative input signal are configured by clearing the DEN bit in the GPIO Digital Enable (GPIODEN) register. For more information on configuring GPIOs, see “General-Purpose Input/Outputs (GPIOs)” on page 289. Table 17-1.
PAGE 649
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller A comparator is configured through two status/control registers (ACCTL and ACSTAT ). The internal reference is configured through one control register (ACREFCTL). Interrupt status and control is configured through three registers (ACMIS, ACRIS, and ACINTEN). Typically, the comparator output is used internally to generate controller interrupts.
PAGE 650
NRND: Not recommended for new designs. Analog Comparator Table 17-3. Internal Reference Voltage and ACREFCTL Field Values (continued) ACREFCTL Register EN Bit Value RNG Bit Value RNG=0 EN=1 Output Reference Voltage Based on VREF Field Value Total resistance in ladder is 31 R. The range of internal reference in this mode is 0.85-2.448 V. RNG=1 Total resistance in ladder is 23 R. The range of internal reference for this mode is 0-2.152 V. 17.
PAGE 651
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 17-4. Analog Comparators Register Map Name Type Reset 0x000 ACMIS R/W1C 0x0000.0000 Analog Comparator Masked Interrupt Status 652 0x004 ACRIS RO 0x0000.0000 Analog Comparator Raw Interrupt Status 653 0x008 ACINTEN R/W 0x0000.0000 Analog Comparator Interrupt Enable 654 0x010 ACREFCTL R/W 0x0000.0000 Analog Comparator Reference Voltage Control 655 0x020 ACSTAT0 RO 0x0000.
PAGE 652
NRND: Not recommended for new designs. Analog Comparator Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x000 This register provides a summary of the interrupt status (masked) of the comparator. Analog Comparator Masked Interrupt Status (ACMIS) Base 0x4003.C000 Offset 0x000 Type R/W1C, reset 0x0000.
PAGE 653
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x004 This register provides a summary of the interrupt status (raw) of the comparator. Analog Comparator Raw Interrupt Status (ACRIS) Base 0x4003.C000 Offset 0x004 Type RO, reset 0x0000.
PAGE 654
NRND: Not recommended for new designs. Analog Comparator Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x008 This register provides the interrupt enable for the comparator. Analog Comparator Interrupt Enable (ACINTEN) Base 0x4003.C000 Offset 0x008 Type R/W, reset 0x0000.
PAGE 655
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x010 This register specifies whether the resistor ladder is powered on as well as the range and tap. Analog Comparator Reference Voltage Control (ACREFCTL) Base 0x4003.C000 Offset 0x010 Type R/W, reset 0x0000.
PAGE 656
NRND: Not recommended for new designs. Analog Comparator Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x020 This register specifies the current output value of the comparator. Analog Comparator Status 0 (ACSTAT0) Base 0x4003.C000 Offset 0x020 Type RO, reset 0x0000.
PAGE 657
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 6: Analog Comparator Control 0 (ACCTL0), offset 0x024 This register configures the comparator’s input and output. Analog Comparator Control 0 (ACCTL0) Base 0x4003.C000 Offset 0x024 Type R/W, reset 0x0000.
PAGE 658
NRND: Not recommended for new designs. Analog Comparator Bit/Field Name Type Reset 6:5 TSEN R/W 0x0 Description Trigger Sense The TSEN field specifies the sense of the comparator output that generates an ADC event.
PAGE 659
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 18 Pulse Width Modulator (PWM) Pulse width modulation (PWM) is a powerful technique for digitally encoding analog signal levels. High-resolution counters are used to generate a square wave, and the duty cycle of the square wave is modulated to encode an analog signal. Typical applications include switching power supplies and motor control. ® The Stellaris PWM module consists of three PWM generator blocks and a control block.
PAGE 660
NRND: Not recommended for new designs. Pulse Width Modulator (PWM) ■ Flexible output control block with PWM output enable of each PWM signal – PWM output enable of each PWM signal – Optional output inversion of each PWM signal (polarity control) – Optional fault handling for each PWM signal – Synchronization of timers in the PWM generator blocks – Interrupt status summary of the PWM generator blocks ■ Can initiate an ADC sample sequence 18.
PAGE 661
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Figure 18-2. PWM Module Block Diagram PWM Generator Block Interrupts / Triggers Interrupt and Trigger Generator Control PWMnINTEN PWMnRIS PWMnISC PWMnCTL PWMn_Fault load dir PWMnLOAD PWMnCOUNT Signal Generator Comparators 18.
PAGE 662
NRND: Not recommended for new designs. Pulse Width Modulator (PWM) Table 18-2. PWM Signals (108BGA) (continued) a Pin Name Pin Number Pin Type Buffer Type Description PWM3 D12 O TTL PWM 3. This signal is controlled by PWM Generator 1. PWM4 A11 O TTL PWM 4. This signal is controlled by PWM Generator 2. PWM5 B12 O TTL PWM 5. This signal is controlled by PWM Generator 2. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 18.3 Functional Description 18.3.
PAGE 663
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Figure 18-3. PWM Count-Down Mode Load CompA CompB Zero Load Zero A B Dir BDown ADown Figure 18-4. PWM Count-Up/Down Mode Load CompA CompB Zero Load Zero A B Dir BUp AUp 18.3.3 BDown ADown PWM Signal Generator The PWM generator takes these pulses (qualified by the direction signal), and generates two PWM signals.
PAGE 664
NRND: Not recommended for new designs. Pulse Width Modulator (PWM) Figure 18-5. PWM Generation Example In Count-Up/Down Mode Load CompA CompB Zero PWMA PWMB In this example, the first generator is set to drive High on match A up, drive Low on match A down, and ignore the other four events. The second generator is set to drive High on match B up, drive Low on match B down, and ignore the other four events.
PAGE 665
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 18.3.6 Synchronization Methods There is a global reset capability that can synchronously reset any or all of the counters in the PWM generators. If multiple PWM generators are configured with the same counter load value, this can be used to guarantee that they also have the same count value (this does imply that the PWM generators must be configured before they are synchronized).
PAGE 666
NRND: Not recommended for new designs. Pulse Width Modulator (PWM) 1. Enable the PWM clock by writing a value of 0x0010.0000 to the RCGC0 register in the System Control module. 2. Enable the clock to the appropriate GPIO module via the RCGC2 register in the System Control module. 3. In the GPIO module, enable the appropriate pins for their alternate function using the GPIOAFSEL register. 4.
PAGE 667
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 18-3. PWM Register Map Description See page Offset Name Type Reset 0x000 PWMCTL R/W 0x0000.0000 PWM Master Control 669 0x004 PWMSYNC R/W 0x0000.0000 PWM Time Base Sync 670 0x008 PWMENABLE R/W 0x0000.0000 PWM Output Enable 671 0x00C PWMINVERT R/W 0x0000.0000 PWM Output Inversion 672 0x010 PWMFAULT R/W 0x0000.0000 PWM Output Fault 673 0x014 PWMINTEN R/W 0x0000.
PAGE 668
NRND: Not recommended for new designs. Pulse Width Modulator (PWM) Table 18-3. PWM Register Map (continued) Name Type Reset 0x0A8 PWM1DBCTL R/W 0x0000.0000 PWM1 Dead-Band Control 695 0x0AC PWM1DBRISE R/W 0x0000.0000 PWM1 Dead-Band Rising-Edge Delay 696 0x0B0 PWM1DBFALL R/W 0x0000.0000 PWM1 Dead-Band Falling-Edge-Delay 697 0x0C0 PWM2CTL R/W 0x0000.0000 PWM2 Control 678 0x0C4 PWM2INTEN R/W 0x0000.0000 PWM2 Interrupt and Trigger Enable 680 0x0C8 PWM2RIS RO 0x0000.
PAGE 669
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 1: PWM Master Control (PWMCTL), offset 0x000 This register provides master control over the PWM generation blocks. PWM Master Control (PWMCTL) Base 0x4002.8000 Offset 0x000 Type R/W, reset 0x0000.
PAGE 670
NRND: Not recommended for new designs. Pulse Width Modulator (PWM) Register 2: PWM Time Base Sync (PWMSYNC), offset 0x004 This register provides a method to perform synchronization of the counters in the PWM generation blocks. Writing a bit in this register to 1 causes the specified counter to reset back to 0; writing multiple bits resets multiple counters simultaneously. The bits auto-clear after the reset has occurred; reading them back as zero indicates that the synchronization has completed.
PAGE 671
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 3: PWM Output Enable (PWMENABLE), offset 0x008 This register provides a master control of which generated PWM signals are output to device pins. By disabling a PWM output, the generation process can continue (for example, when the time bases are synchronized) without driving PWM signals to the pins.
PAGE 672
NRND: Not recommended for new designs. Pulse Width Modulator (PWM) Register 4: PWM Output Inversion (PWMINVERT), offset 0x00C This register provides a master control of the polarity of the PWM signals on the device pins. The PWM signals generated by the PWM generator are active High; they can optionally be made active Low via this register. Disabled PWM channels are also passed through the output inverter (if so configured) so that inactive channels maintain the correct polarity.
PAGE 673
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 5: PWM Output Fault (PWMFAULT), offset 0x010 This register controls the behavior of the PWM outputs in the presence of fault conditions. Both the fault inputs and debug events are considered fault conditions. On a fault condition, each PWM signal can be passed through unmodified or driven Low.
PAGE 674
NRND: Not recommended for new designs. Pulse Width Modulator (PWM) Register 6: PWM Interrupt Enable (PWMINTEN), offset 0x014 This register controls the global interrupt generation capabilities of the PWM module. The events that can cause an interrupt are the fault input and the individual interrupts from the PWM generators. PWM Interrupt Enable (PWMINTEN) Base 0x4002.8000 Offset 0x014 Type R/W, reset 0x0000.
PAGE 675
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 7: PWM Raw Interrupt Status (PWMRIS), offset 0x018 This register provides the current set of interrupt sources that are asserted, regardless of whether they cause an interrupt to be asserted to the controller. The fault interrupt is latched on detection; it must be cleared through the PWM Interrupt Status and Clear (PWMISC) register (see page 676).
PAGE 676
NRND: Not recommended for new designs. Pulse Width Modulator (PWM) Register 8: PWM Interrupt Status and Clear (PWMISC), offset 0x01C This register provides a summary of the interrupt status of the individual PWM generator blocks. A bit set to 1 indicates that the corresponding generator block is asserting an interrupt. The individual interrupt status registers in each block must be consulted to determine the reason for the interrupt, and used to clear the interrupt.
PAGE 677
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 9: PWM Status (PWMSTATUS), offset 0x020 This register provides the status of the FAULT input signal. PWM Status (PWMSTATUS) Base 0x4002.8000 Offset 0x020 Type RO, reset 0x0000.
PAGE 678
NRND: Not recommended for new designs. Pulse Width Modulator (PWM) Register 10: PWM0 Control (PWM0CTL), offset 0x040 Register 11: PWM1 Control (PWM1CTL), offset 0x080 Register 12: PWM2 Control (PWM2CTL), offset 0x0C0 These registers configure the PWM signal generation blocks (PWM0CTL controls the PWM generator 0 block, and so on). The Register Update mode, Debug mode, Counting mode, and Block Enable mode are all controlled via these registers.
PAGE 679
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset 1 Mode R/W 0 Description Counter Mode The mode for the counter. When not set, the counter counts down from the load value to 0 and then wraps back to the load value (Count-Down mode). When set, the counter counts up from 0 to the load value, back down to 0, and then repeats (Count-Up/Down mode). 0 Enable R/W 0 PWM Block Enable Master enable for the PWM generation block.
PAGE 680
NRND: Not recommended for new designs. Pulse Width Modulator (PWM) Register 13: PWM0 Interrupt and Trigger Enable (PWM0INTEN), offset 0x044 Register 14: PWM1 Interrupt and Trigger Enable (PWM1INTEN), offset 0x084 Register 15: PWM2 Interrupt and Trigger Enable (PWM2INTEN), offset 0x0C4 These registers control the interrupt and ADC trigger generation capabilities of the PWM generators (PWM0INTEN controls the PWM generator 0 block, and so on).
PAGE 681
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset 12 TrCmpBU R/W 0 Description Trigger for Counter=Comparator B Up Value Description 11 TrCmpAD R/W 0 1 An ADC trigger pulse is output when the counter matches the value in the PWMnCMPB register value while counting up. 0 No ADC trigger is output.
PAGE 682
NRND: Not recommended for new designs. Pulse Width Modulator (PWM) Bit/Field Name Type Reset 4 IntCmpBU R/W 0 Description Interrupt for Counter=Comparator B Up Value Description 3 IntCmpAD R/W 0 1 A raw interrupt occurs when the counter matches the value in the PWMnCMPB register value while counting up. 0 No interrupt.
PAGE 683
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 16: PWM0 Raw Interrupt Status (PWM0RIS), offset 0x048 Register 17: PWM1 Raw Interrupt Status (PWM1RIS), offset 0x088 Register 18: PWM2 Raw Interrupt Status (PWM2RIS), offset 0x0C8 These registers provide the current set of interrupt sources that are asserted, regardless of whether they cause an interrupt to be asserted to the controller (PWM0RIS controls the PWM generator 0 block, and so on).
PAGE 684
NRND: Not recommended for new designs. Pulse Width Modulator (PWM) Register 19: PWM0 Interrupt Status and Clear (PWM0ISC), offset 0x04C Register 20: PWM1 Interrupt Status and Clear (PWM1ISC), offset 0x08C Register 21: PWM2 Interrupt Status and Clear (PWM2ISC), offset 0x0CC These registers provide the current set of interrupt sources that are asserted to the controller (PWM0ISC controls the PWM generator 0 block, and so on).
PAGE 685
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 22: PWM0 Load (PWM0LOAD), offset 0x050 Register 23: PWM1 Load (PWM1LOAD), offset 0x090 Register 24: PWM2 Load (PWM2LOAD), offset 0x0D0 These registers contain the load value for the PWM counter (PWM0LOAD controls the PWM generator 0 block, and so on).
PAGE 686
NRND: Not recommended for new designs. Pulse Width Modulator (PWM) Register 25: PWM0 Counter (PWM0COUNT), offset 0x054 Register 26: PWM1 Counter (PWM1COUNT), offset 0x094 Register 27: PWM2 Counter (PWM2COUNT), offset 0x0D4 These registers contain the current value of the PWM counter (PWM0COUNT is the value of the PWM generator 0 block, and so on).
PAGE 687
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 28: PWM0 Compare A (PWM0CMPA), offset 0x058 Register 29: PWM1 Compare A (PWM1CMPA), offset 0x098 Register 30: PWM2 Compare A (PWM2CMPA), offset 0x0D8 These registers contain a value to be compared against the counter (PWM0CMPA controls the PWM generator 0 block, and so on).
PAGE 688
NRND: Not recommended for new designs. Pulse Width Modulator (PWM) Register 31: PWM0 Compare B (PWM0CMPB), offset 0x05C Register 32: PWM1 Compare B (PWM1CMPB), offset 0x09C Register 33: PWM2 Compare B (PWM2CMPB), offset 0x0DC These registers contain a value to be compared against the counter (PWM0CMPB controls the PWM generator 0 block, and so on).
PAGE 689
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 34: PWM0 Generator A Control (PWM0GENA), offset 0x060 Register 35: PWM1 Generator A Control (PWM1GENA), offset 0x0A0 Register 36: PWM2 Generator A Control (PWM2GENA), offset 0x0E0 These registers control the generation of the PWMnA signal based on the load and zero output pulses from the counter, as well as the compare A and compare B pulses from the comparators (PWM0GENA controls the PWM generator 0 block, and so on).
PAGE 690
NRND: Not recommended for new designs. Pulse Width Modulator (PWM) Bit/Field Name Type Reset 9:8 ActCmpBU R/W 0x0 Description Action for Comparator B Up The action to be taken when the counter matches comparator B while counting up. Occurs only when the Mode bit in the PWMnCTL register (see page 678) is set to 1. The table below defines the effect of the event on the output signal. Value Description 0x0 Do nothing. 0x1 Invert the output signal. 0x2 Set the output signal to 0.
PAGE 691
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset 1:0 ActZero R/W 0x0 Description Action for Counter=0 The action to be taken when the counter is zero. The table below defines the effect of the event on the output signal. Value Description 0x0 Do nothing. 0x1 Invert the output signal. 0x2 Set the output signal to 0. 0x3 Set the output signal to 1.
PAGE 692
NRND: Not recommended for new designs. Pulse Width Modulator (PWM) Register 37: PWM0 Generator B Control (PWM0GENB), offset 0x064 Register 38: PWM1 Generator B Control (PWM1GENB), offset 0x0A4 Register 39: PWM2 Generator B Control (PWM2GENB), offset 0x0E4 These registers control the generation of the PWMnB signal based on the load and zero output pulses from the counter, as well as the compare A and compare B pulses from the comparators (PWM0GENB controls the PWM generator 0 block, and so on).
PAGE 693
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset 9:8 ActCmpBU R/W 0x0 Description Action for Comparator B Up The action to be taken when the counter matches comparator B while counting up. Occurs only when the Mode bit in the PWMnCTL register is set to 1. The table below defines the effect of the event on the output signal. Value Description 0x0 Do nothing. 0x1 Invert the output signal. 0x2 Set the output signal to 0.
PAGE 694
NRND: Not recommended for new designs. Pulse Width Modulator (PWM) Bit/Field Name Type Reset 1:0 ActZero R/W 0x0 Description Action for Counter=0 The action to be taken when the counter is 0. The table below defines the effect of the event on the output signal. Value Description 0x0 Do nothing. 0x1 Invert the output signal. 0x2 Set the output signal to 0. 0x3 Set the output signal to 1.
PAGE 695
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 40: PWM0 Dead-Band Control (PWM0DBCTL), offset 0x068 Register 41: PWM1 Dead-Band Control (PWM1DBCTL), offset 0x0A8 Register 42: PWM2 Dead-Band Control (PWM2DBCTL), offset 0x0E8 The PWM0DBCTL register controls the dead-band generator, which produces the PWM0 and PWM1 signals based on the PWM0A and PWM0B signals.
PAGE 696
NRND: Not recommended for new designs. Pulse Width Modulator (PWM) Register 43: PWM0 Dead-Band Rising-Edge Delay (PWM0DBRISE), offset 0x06C Register 44: PWM1 Dead-Band Rising-Edge Delay (PWM1DBRISE), offset 0x0AC Register 45: PWM2 Dead-Band Rising-Edge Delay (PWM2DBRISE), offset 0x0EC The PWM0DBRISE register contains the number of clock ticks to delay the rising edge of the PWM0A signal when generating the PWM0 signal.
PAGE 697
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 46: PWM0 Dead-Band Falling-Edge-Delay (PWM0DBFALL), offset 0x070 Register 47: PWM1 Dead-Band Falling-Edge-Delay (PWM1DBFALL), offset 0x0B0 Register 48: PWM2 Dead-Band Falling-Edge-Delay (PWM2DBFALL), offset 0x0F0 The PWM0DBFALL register contains the number of clock ticks to delay the falling edge of the PWM0A signal when generating the PWM1 signal. If the dead-band generator is disabled, this register is ignored.
PAGE 698
NRND: Not recommended for new designs. Quadrature Encoder Interface (QEI) 19 Quadrature Encoder Interface (QEI) A quadrature encoder, also known as a 2-channel incremental encoder, converts linear displacement into a pulse signal. By monitoring both the number of pulses and the relative phase of the two signals, you can track the position, direction of rotation, and speed. In addition, a third channel, or index signal, can be used to reset the position counter.
PAGE 699
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Figure 19-1. QEI Block Diagram QEILOAD Control & Status Velocity Timer QEITIME QEICTL QEISTAT Velocity Accumulator Velocity Predivider clk PhA PhB QEICOUNT QEISPEED QEIMAXPOS Quadrature Encoder dir Position Integrator QEIPOS IDX QEIINTEN Interrupt Control Interrupt QEIRIS QEIISC 19.
PAGE 700
NRND: Not recommended for new designs. Quadrature Encoder Interface (QEI) Table 19-2. QEI Signals (108BGA) (continued) Pin Name a Pin Number Pin Type Buffer Type Description PhB0 M2 I TTL QEI module 0 phase B. PhB1 B11 I TTL QEI module 1 phase B. a. The TTL designation indicates the pin has TTL-compatible voltage levels. 19.
PAGE 701
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller counting commences on a new time period. The number of edges counted in a given time period is directly proportional to the velocity of the encoder. Figure 19-2 on page 701 shows how the Stellaris quadrature encoder converts the phase input signals into clock pulses, the direction signal, and how the velocity predivider operates (in Divide by 4 mode). Figure 19-2.
PAGE 702
NRND: Not recommended for new designs. Quadrature Encoder Interface (QEI) Important: Reducing constant factors at compile time is the best way to control the intermediate values of this equation, as well as reducing the processing requirement of computing this equation. The division can be avoided by selecting a timer load value such that the divisor is a power of 2; a simple shift can therefore be done in place of the division.
PAGE 703
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Note that the QEI module clock must be enabled before the registers can be programmed (see page 223). There must be a delay of 3 system clocks after the QEI module clock is enabled before any QEI module registers are accessed. Table 19-3. QEI Register Map Offset Name Type Reset Description See page 0x000 QEICTL R/W 0x0000.0000 QEI Control 704 0x004 QEISTAT RO 0x0000.
PAGE 704
NRND: Not recommended for new designs. Quadrature Encoder Interface (QEI) Register 1: QEI Control (QEICTL), offset 0x000 This register contains the configuration of the QEI module. Separate enables are provided for the quadrature encoder and the velocity capture blocks; the quadrature encoder must be enabled in order to capture the velocity, but the velocity does not need to be captured in applications that do not need it.
PAGE 705
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Bit/Field Name Type Reset 5 VelEn R/W 0 Description Capture Velocity When set, enables capture of the velocity of the quadrature encoder. 4 ResMode R/W 0 Reset Mode The Reset mode for the position counter. When 0, the position counter is reset when it reaches the maximum; when 1, the position counter is reset when the index pulse is captured.
PAGE 706
NRND: Not recommended for new designs. Quadrature Encoder Interface (QEI) Register 2: QEI Status (QEISTAT), offset 0x004 This register provides status about the operation of the QEI module. QEI Status (QEISTAT) QEI0 base: 0x4002.C000 QEI1 base: 0x4002.D000 Offset 0x004 Type RO, reset 0x0000.
PAGE 707
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 3: QEI Position (QEIPOS), offset 0x008 This register contains the current value of the position integrator. Its value is updated by inputs on the QEI phase inputs, and can be set to a specific value by writing to it. QEI Position (QEIPOS) QEI0 base: 0x4002.C000 QEI1 base: 0x4002.D000 Offset 0x008 Type R/W, reset 0x0000.
PAGE 708
NRND: Not recommended for new designs. Quadrature Encoder Interface (QEI) Register 4: QEI Maximum Position (QEIMAXPOS), offset 0x00C This register contains the maximum value of the position integrator. When moving forward, the position register resets to zero when it increments past this value. When moving backward, the position register resets to this value when it decrements from zero. QEI Maximum Position (QEIMAXPOS) QEI0 base: 0x4002.C000 QEI1 base: 0x4002.D000 Offset 0x00C Type R/W, reset 0x0000.
PAGE 709
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 5: QEI Timer Load (QEILOAD), offset 0x010 This register contains the load value for the velocity timer. Since this value is loaded into the timer the clock cycle after the timer is zero, this value should be one less than the number of clocks in the desired period. So, for example, to have 2000 clocks per timer period, this register should contain 1999. QEI Timer Load (QEILOAD) QEI0 base: 0x4002.C000 QEI1 base: 0x4002.
PAGE 710
NRND: Not recommended for new designs. Quadrature Encoder Interface (QEI) Register 6: QEI Timer (QEITIME), offset 0x014 This register contains the current value of the velocity timer. This counter does not increment when VelEn in QEICTL is 0. QEI Timer (QEITIME) QEI0 base: 0x4002.C000 QEI1 base: 0x4002.D000 Offset 0x014 Type RO, reset 0x0000.
PAGE 711
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 7: QEI Velocity Counter (QEICOUNT), offset 0x018 This register contains the running count of velocity pulses for the current time period.
PAGE 712
NRND: Not recommended for new designs. Quadrature Encoder Interface (QEI) Register 8: QEI Velocity (QEISPEED), offset 0x01C This register contains the most recently measured velocity of the quadrature encoder. This corresponds to the number of velocity pulses counted in the previous velocity timer period. This register does not update when VelEn in QEICTL is 0. QEI Velocity (QEISPEED) QEI0 base: 0x4002.C000 QEI1 base: 0x4002.D000 Offset 0x01C Type RO, reset 0x0000.
PAGE 713
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 9: QEI Interrupt Enable (QEIINTEN), offset 0x020 This register contains enables for each of the QEI module’s interrupts. An interrupt is asserted to the controller if its corresponding bit in this register is set to 1. QEI Interrupt Enable (QEIINTEN) QEI0 base: 0x4002.C000 QEI1 base: 0x4002.D000 Offset 0x020 Type R/W, reset 0x0000.
PAGE 714
NRND: Not recommended for new designs. Quadrature Encoder Interface (QEI) Register 10: QEI Raw Interrupt Status (QEIRIS), offset 0x024 This register provides the current set of interrupt sources that are asserted, regardless of whether they cause an interrupt to be asserted to the controller (this is set through the QEIINTEN register). Bits set to 1 indicate the latched events that have occurred; a zero bit indicates that the event in question has not occurred.
PAGE 715
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Register 11: QEI Interrupt Status and Clear (QEIISC), offset 0x028 This register provides the current set of interrupt sources that are asserted to the controller. Bits set to 1 indicate the latched events that have occurred; a zero bit indicates that the event in question has not occurred. This is a R/W1C register; writing a 1 to a bit position clears the corresponding interrupt reason.
PAGE 716
NRND: Not recommended for new designs. Pin Diagram 20 Pin Diagram The LM3S8962 microcontroller pin diagrams are shown below. Figure 20-1.
PAGE 717
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Figure 20-2.
PAGE 718
NRND: Not recommended for new designs. Signal Tables 21 Signal Tables Important: All multiplexed pins are GPIOs by default, with the exception of the five JTAG pins (PB7 and PC[3:0]) which default to the JTAG functionality. The following tables list the signals available for each pin. Functionality is enabled by software with the GPIOAFSEL register. All digital inputs are Schmitt triggered.
PAGE 719
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 21-1. Signals by Pin Number (continued) a Pin Number Pin Name Pin Type Buffer Type PD3 I/O TTL GPIO port D bit 3. 13 U1Tx O TTL UART module 1 transmit. When in IrDA mode, this signal has IrDA modulation. VDD25 - Power Positive supply for most of the logic function, including the processor core and most peripherals. Ground reference for logic and I/O pins.
PAGE 720
NRND: Not recommended for new designs. Signal Tables Table 21-1. Signals by Pin Number (continued) Pin Number a Pin Name Pin Type Buffer Type VDD25 - Power Positive supply for most of the logic function, including the processor core and most peripherals. 39 GND - Power Ground reference for logic and I/O pins. 40 RXIP I Analog RXIP of the Ethernet PHY. 41 ERBIAS I Analog 12.4-kΩ resistor (1% precision) used internally for Ethernet PHY. 42 GNDPHY - Power GND of the Ethernet PHY.
PAGE 721
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 21-1. Signals by Pin Number (continued) Pin Number a Pin Name Pin Type Buffer Type Description PB1 I/O TTL GPIO port B bit 1. PWM3 O TTL PWM 3. This signal is controlled by PWM Generator 1. 68 VDD - Power Positive supply for I/O and some logic. 69 GND - Power Ground reference for logic and I/O pins. PB2 I/O TTL GPIO port B bit 2. I2C0SCL I/O OD I2C module 0 clock.
PAGE 722
NRND: Not recommended for new designs. Signal Tables Table 21-1. Signals by Pin Number (continued) Pin Number a Pin Name Pin Type Buffer Type PB5 I/O TTL GPIO port B bit 5. C0o O TTL Analog comparator 0 output. PB4 I/O TTL GPIO port B bit 4. 91 92 Description C0- I Analog Analog comparator 0 negative input. 93 VDD - Power Positive supply for I/O and some logic. 94 GND - Power Ground reference for logic and I/O pins. PD4 I/O TTL GPIO port D bit 4.
PAGE 723
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 21-2. Signals by Signal Name (continued) a Pin Name Pin Number Pin Type Buffer Type Description ERBIAS 41 I Analog Fault 99 I TTL GND 9 15 21 33 39 45 54 57 63 69 82 87 94 - Power Ground reference for logic and I/O pins. GNDA 4 97 - Power The ground reference for the analog circuits (ADC, Analog Comparators, etc.).
PAGE 724
NRND: Not recommended for new designs. Signal Tables Table 21-2. Signals by Signal Name (continued) a Pin Name Pin Number Pin Type Buffer Type Description PB0 66 I/O TTL GPIO port B bit 0. PB1 67 I/O TTL GPIO port B bit 1. PB2 70 I/O TTL GPIO port B bit 2. PB3 71 I/O TTL GPIO port B bit 3. PB4 92 I/O TTL GPIO port B bit 4. PB5 91 I/O TTL GPIO port B bit 5. PB6 90 I/O TTL GPIO port B bit 6. PB7 89 I/O TTL GPIO port B bit 7. PC0 80 I/O TTL GPIO port C bit 0.
PAGE 725
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 21-2. Signals by Signal Name (continued) a Pin Name Pin Number Pin Type Buffer Type Description PWM3 67 O TTL PWM 3. This signal is controlled by PWM Generator 1. PWM4 72 O TTL PWM 4. This signal is controlled by PWM Generator 2. PWM5 73 O TTL PWM 5. This signal is controlled by PWM Generator 2. System reset input. RST 64 I TTL RXIN 37 I Analog RXIN of the Ethernet PHY. RXIP of the Ethernet PHY.
PAGE 726
NRND: Not recommended for new designs. Signal Tables Table 21-2. Signals by Signal Name (continued) a Pin Name Pin Number Pin Type Buffer Type Description VDDA 3 98 - Power The positive supply for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions.
PAGE 727
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 21-3. Signals by Function, Except for GPIO (continued) Function Ethernet General-Purpose Timers Pin Name a Pin Number Pin Type Buffer Type Description ERBIAS 41 I Analog 12.4-kΩ resistor (1% precision) used internally for Ethernet PHY. GNDPHY 42 85 86 - Power GND of the Ethernet PHY. LED0 59 O TTL Ethernet LED 0. LED1 60 O TTL Ethernet LED 1. MDIO 58 I/O TTL MDIO of the Ethernet PHY.
PAGE 728
NRND: Not recommended for new designs. Signal Tables Table 21-3. Signals by Function, Except for GPIO (continued) Function Pin Name Pin Number a Pin Type Buffer Type Description SWCLK 80 I TTL JTAG/SWD CLK. SWDIO 79 I/O TTL JTAG TMS and SWDIO. SWO 77 O TTL JTAG TDO and SWO. TCK 80 I TTL JTAG/SWD CLK. TDI 78 I TTL JTAG TDI. TDO 77 O TTL JTAG TDO and SWO. TMS 79 I/O TTL JTAG TMS and SWDIO. TRST 89 I TTL JTAG TRST. Fault 99 I TTL PWM Fault.
PAGE 729
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 21-3. Signals by Function, Except for GPIO (continued) Function Pin Name a Pin Number Pin Type Buffer Type GND 9 15 21 33 39 45 54 57 63 69 82 87 94 - Power Ground reference for logic and I/O pins. GNDA 4 97 - Power The ground reference for the analog circuits (ADC, Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions.
PAGE 730
NRND: Not recommended for new designs. Signal Tables Table 21-3. Signals by Function, Except for GPIO (continued) Function System Control & Clocks Pin Name a Pin Number Pin Type Buffer Type CMOD0 65 I TTL CPU Mode bit 0. Input must be set to logic 0 (grounded); other encodings reserved. CMOD1 76 I TTL CPU Mode bit 1. Input must be set to logic 0 (grounded); other encodings reserved. OSC0 48 I Analog Main oscillator crystal input or an external clock reference input.
PAGE 731
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 21-4. GPIO Pins and Alternate Functions (continued) IO Pin Number Multiplexed Function PC5 24 PC6 23 PC7 22 PD0 10 CAN0Rx PD1 11 CAN0Tx PD2 12 U1Rx PD3 13 U1Tx PD4 95 CCP0 Multiplexed Function PhB0 PD5 96 PD6 99 Fault PD7 100 IDX0 PE0 72 PWM4 PE1 73 PWM5 PE2 74 PhB1 PE3 75 PhA1 PF0 47 PWM0 PF1 61 IDX1 PF2 60 LED1 PF3 59 LED0 PG0 19 PG1 18 PWM1 21.
PAGE 732
NRND: Not recommended for new designs. Signal Tables Table 21-5. Signals by Pin Number (continued) a Pin Number Pin Name Pin Type Buffer Type PC0 I/O TTL GPIO port C bit 0. A9 SWCLK I TTL JTAG/SWD CLK. TCK I TTL JTAG/SWD CLK. PC3 I/O TTL GPIO port C bit 3. SWO O TTL JTAG TDO and SWO. TDO O TTL JTAG TDO and SWO. PE0 I/O TTL GPIO port E bit 0. PWM4 O TTL PWM 4. This signal is controlled by PWM Generator 2. A10 A11 Description PE3 I/O TTL GPIO port E bit 3.
PAGE 733
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 21-5. Signals by Pin Number (continued) Pin Number a Pin Name Pin Type Buffer Type VDDA - Power The positive supply for the analog circuits (ADC, Analog Comparators, etc.). These are separated from VDD to minimize the electrical noise contained on VDD from affecting the analog functions.
PAGE 734
NRND: Not recommended for new designs. Signal Tables Table 21-5. Signals by Pin Number (continued) Pin Number a Pin Name Pin Type Buffer Type Description PD1 I/O TTL GPIO port D bit 1. CAN0Tx O TTL CAN module 0 transmit. VDD25 - Power Positive supply for most of the logic function, including the processor core and most peripherals. G10 VDD33 - Power Positive supply for I/O and some logic. G2 G3 G11 VDD33 - Power Positive supply for I/O and some logic.
PAGE 735
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 21-5. Signals by Pin Number (continued) Pin Number K12 a Pin Name Pin Type Buffer Type XOSC1 O Analog Description Hibernation module oscillator crystal output. Leave unconnected when using a single-ended clock source. PC4 I/O TTL GPIO port C bit 4. PhA0 I TTL QEI module 0 phase A. L2 PC7 I/O TTL GPIO port C bit 7. PA0 I/O TTL GPIO port A bit 0. L3 U0Rx I TTL UART module 0 receive.
PAGE 736
NRND: Not recommended for new designs. Signal Tables 21.2.2 Signals by Signal Name Table 21-6. Signals by Signal Name a Pin Name Pin Number Pin Type Buffer Type ADC0 B1 I Analog Description Analog-to-digital converter input 0. ADC1 A1 I Analog Analog-to-digital converter input 1. ADC2 B3 I Analog Analog-to-digital converter input 2. ADC3 B2 I Analog Analog-to-digital converter input 3. C0+ A7 I Analog Analog comparator 0 positive input.
PAGE 737
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 21-6. Signals by Signal Name (continued) a Pin Name Pin Number Pin Type Buffer Type Description LDO E3 - Power LED0 J12 O TTL Ethernet LED 0. LED1 J11 O TTL Ethernet LED 1. MDIO L9 I/O TTL MDIO of the Ethernet PHY. NC A2 A3 A4 B4 C1 C2 D1 D2 - - OSC0 L11 I Analog Main oscillator crystal input or an external clock reference input. OSC1 M11 O Analog Main oscillator crystal output.
PAGE 738
NRND: Not recommended for new designs. Signal Tables Table 21-6. Signals by Signal Name (continued) a Pin Name Pin Number Pin Type Buffer Type Description PD1 G2 I/O TTL GPIO port D bit 1. PD2 H2 I/O TTL GPIO port D bit 2. PD3 H1 I/O TTL GPIO port D bit 3. PD4 E1 I/O TTL GPIO port D bit 4. PD5 E2 I/O TTL GPIO port D bit 5. PD6 F2 I/O TTL GPIO port D bit 6. PD7 F1 I/O TTL GPIO port D bit 7. PE0 A11 I/O TTL GPIO port E bit 0.
PAGE 739
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 21-6. Signals by Signal Name (continued) Pin Name Pin Number TRST A8 TXON L8 TXOP M8 U0Rx Pin Type a Buffer Type Description I TTL JTAG TRST. O Analog TXON of the Ethernet PHY. O Analog TXOP of the Ethernet PHY. L3 I TTL UART module 0 receive. When in IrDA mode, this signal has IrDA modulation. U0Tx M3 O TTL UART module 0 transmit. When in IrDA mode, this signal has IrDA modulation.
PAGE 740
NRND: Not recommended for new designs. Signal Tables 21.2.3 Signals by Function, Except for GPIO Table 21-7. Signals by Function, Except for GPIO Function Pin Name Pin Type Buffer Type ADC0 B1 I Analog Analog-to-digital converter input 0. ADC1 A1 I Analog Analog-to-digital converter input 1. ADC2 B3 I Analog Analog-to-digital converter input 2. ADC3 B2 I Analog Analog-to-digital converter input 3. C0+ A7 I Analog Analog comparator 0 positive input.
PAGE 741
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 21-7. Signals by Function, Except for GPIO (continued) Function Pin Name a Pin Number Pin Type Buffer Type HIB M12 O OD VBAT L12 - Power Power source for the Hibernation module. It is normally connected to the positive terminal of a battery and serves as the battery backup/Hibernation module power-source supply.
PAGE 742
NRND: Not recommended for new designs. Signal Tables Table 21-7. Signals by Function, Except for GPIO (continued) Function Pin Name a Pin Number Pin Type Buffer Type GND B6 C4 C5 F10 F11 F12 H3 J3 J10 K5 K6 K10 L10 - Power Ground reference for logic and I/O pins. GNDA A5 B5 - Power The ground reference for the analog circuits (ADC, Analog Comparators, etc.). These are separated from GND to minimize the electrical noise contained on VDD from affecting the analog functions.
PAGE 743
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 21-7. Signals by Function, Except for GPIO (continued) Function System Control & Clocks Pin Name a Pin Number Pin Type Buffer Type CMOD0 E11 I TTL CPU Mode bit 0. Input must be set to logic 0 (grounded); other encodings reserved. CMOD1 B10 I TTL CPU Mode bit 1. Input must be set to logic 0 (grounded); other encodings reserved.
PAGE 744
NRND: Not recommended for new designs. Signal Tables Table 21-8. GPIO Pins and Alternate Functions (continued) 21.
PAGE 745
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 21-9. Connections for Unused Signals (100-pin LQFP) (continued) Function Signal Name Pin Number Acceptable Practice Preferred Practice ERBIAS 41 Connect to GND through 12.4-kΩ resistor. Connect to GND through 12.4-kΩ resistor.
PAGE 746
NRND: Not recommended for new designs. Signal Tables Table 21-10. Connections for Unused Signals, 108-pin BGA (continued) Function Signal Name Pin Number Acceptable Practice Preferred Practice ERBIAS K3 Connect to GND through 12.4-kΩ resistor. Connect to GND through 12.4-kΩ resistor.
PAGE 747
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 22 Operating Characteristics Table 22-1. Temperature Characteristics Characteristic Symbol Value Industrial operating temperature range TA -40 to +85 Unit °C Extended operating temperature range TA -40 to +105 °C Unpowered storage temperature range TS -65 to +150 °C Table 22-2.
PAGE 748
NRND: Not recommended for new designs. Electrical Characteristics 23 Electrical Characteristics 23.1 DC Characteristics 23.1.1 Maximum Ratings The maximum ratings are the limits to which the device can be subjected without permanently damaging the device. Note: The device is not guaranteed to operate properly at the maximum ratings. Table 23-1.
PAGE 749
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 23-2. Recommended DC Operating Conditions (continued) Parameter Parameter Name Min Nom Max Unit VIH High-level input voltage 2.0 - 5.0 V VIL Low-level input voltage -0.3 - 1.3 V a VOH High-level output voltage 2.4 - - V VOLa Low-level output voltage - - 0.4 V 2-mA Drive 2.0 - - mA 4-mA Drive 4.0 - - mA 8-mA Drive 8.0 - - mA 2-mA Drive 2.0 - - mA 4-mA Drive 4.
PAGE 750
NRND: Not recommended for new designs. Electrical Characteristics ■ VDD25 = 2.50 V ■ VBAT = 3.0 V ■ VDDA = 3.3 V ■ VDDPHY = 3.3 V ■ Temperature = 25°C ■ Clock Source (MOSC) =3.579545 MHz Crystal Oscillator ■ Main oscillator (MOSC) = enabled ■ Internal oscillator (IOSC) = disabled Table 23-5. Detailed Power Specifications Parameter Parameter Name Run mode 1 (Flash loop) Conditions VDD25 = 2.50 V 3.3 V VDD, VDDA, VDDPHY 2.5 V VDD25 3.
PAGE 751
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 23-5. Detailed Power Specifications (continued) Parameter Parameter Name Conditions 3.3 V VDD, VDDA, VDDPHY 3.0 V VBAT Unit Nom Max Nom Max Nom Max 0 0 0 0 16 pendinga VBAT = 3.0 V IDD_HIBERNATE Hibernate mode 2.5 V VDD25 µA VDD = 0 V VDD25 = 0 V VDDA = 0 V VDDPHY = 0 V Peripherals = All OFF System Clock = OFF Hibernate Module = 32 kHz a. Pending characterization completion. 23.1.
PAGE 752
NRND: Not recommended for new designs. Electrical Characteristics Figure 23-1. Load Conditions CL = 50 pF pin GND 23.2.2 Clocks Table 23-9. Phase Locked Loop (PLL) Characteristics Min Nom Max Unit fref_crystal Parameter Crystal reference Parameter Name 3.579545 - 8.192 MHz fref_ext External clock referencea 3.579545 - 8.192 MHz a b fpll PLL frequency - 400 - MHz TREADY PLL lock time - - 0.5 ms a.
PAGE 753
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 23-11. Clock Characteristics (continued) Parameter Parameter Name fXOSC_EXT External clock reference for hibernation module fMOSC Main oscillator frequency tMOSC_per Main oscillator period fref_crystal_bypass Min Nom Max Unit - 32.768 - KHz 1 - 8.192 MHz 125 - 1000 ns Crystal reference using the main oscillator a (PLL in BYPASS mode) 1 - 8.
PAGE 754
NRND: Not recommended for new designs. Electrical Characteristics Table 23-14. JTAG Characteristics (continued) Parameter No.
PAGE 755
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Figure 23-3. JTAG Test Access Port (TAP) Timing TCK J7 TMS TDI J8 J7 TMS Input Valid TMS Input Valid J9 J9 J10 TDI Input Valid J11 TDO J8 J10 TDI Input Valid J12 J13 TDO Output Valid TDO Output Valid Figure 23-4. JTAG TRST Timing TCK J14 J15 TRST 23.2.4 Reset Table 23-15. Reset Characteristics Parameter No.
PAGE 756
NRND: Not recommended for new designs. Electrical Characteristics Table 23-15. Reset Characteristics (continued) Parameter No. R11 Parameter TMIN Parameter Name Minimum RST pulse width Min Nom Max Unit 2 - - µs a. 20 * t MOSC_per Figure 23-5. External Reset Timing (RST) RST R7 R11 /Reset (Internal) Figure 23-6. Power-On Reset Timing R1 VDD R3 /POR (Internal) R5 /Reset (Internal) Figure 23-7. Brown-Out Reset Timing R2 VDD R4 /BOR (Internal) R6 /Reset (Internal) Figure 23-8.
PAGE 757
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Figure 23-9. Watchdog Reset Timing WDOG Reset (Internal) R9 /Reset (Internal) 23.2.5 Sleep Modes a Table 23-16.
PAGE 758
NRND: Not recommended for new designs. Electrical Characteristics Figure 23-10. Hibernation Module Timing 32.768 KHz (internal) H1 H2 HIB H4 WAKE H3 23.2.7 General-Purpose I/O (GPIO) Note: All GPIOs are 5 V-tolerant. Table 23-18.
PAGE 759
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 23-19. ADC Characteristics (continued) Parameter Parameter Name Min Nom Max Unit d EO Offset error - - +6 LSB EG Full-scale gain error - - ±3 LSB ETS Temperature sensor accuracy - - ±5 °C a. The ADC reference voltage is 3.0 V. This reference voltage is internally generated from the 3.3 VDDA supply by a band gap circuit. b.
PAGE 760
NRND: Not recommended for new designs. Electrical Characteristics Table 23-21. SSI Characteristics (continued) Parameter No. Parameter Parameter Name Min Nom Max Unit S8 tDSs Data from slave setup time 1 - - system clocks S9 tDSh Data from slave hold time 2 - - system clocks a. Note that the delays shown are using 8-mA drive strength. Figure 23-12.
PAGE 761
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Figure 23-14. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 S1 S2 S4 SSIClk (SPO=0) S3 SSIClk (SPO=1) S6 SSITx (master) S7 MSB S5 SSIRx (slave) S8 LSB S9 MSB LSB SSIFss 23.2.10 Inter-Integrated Circuit (I2C) Interface Table 23-22. I2C Characteristics Parameter No.
PAGE 762
NRND: Not recommended for new designs. Electrical Characteristics Figure 23-15. I2C Timing I2 I6 I5 I2CSCL I1 I4 I7 I8 I3 I9 I2CSDA 23.2.11 Ethernet Controller a Table 23-23. 100BASE-TX Transmitter Characteristics Parameter Name Min Nom Max Unit Peak output amplitude 950 - 1050 mVpk Output amplitude symmetry 98 - 102 % Output overshoot - - 5 % Rise/Fall time 3 - 5 ns Rise/Fall time imbalance - - 500 ps Duty cycle distortion - - - ps Jitter - - 1.4 ns a.
PAGE 763
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Table 23-26. 10BASE-T Transmitter Characteristics (continued) Parameter Name Start-of-idle pulse width Min Nom Max Unit - 300 - ns 350 a. The Manchester-encoded data pulses, the link pulse and the start-of-idle pulse are tested against the templates and using the procedures found in Clause 14 of IEEE 802.3. a Table 23-27.
PAGE 764
NRND: Not recommended for new designs. Electrical Characteristics Table 23-30. Ethernet Reference Crystal (continued) Name Value Condition Aging ±2 PPM/yr Temperature stability (-40° to 85°) ±5 PPM ±5 PPM Temperature stability (-40° to 105°) Oscillation mode Parallel resonance, fundamental mode Parameters at 25° C ±2° C; Drive level = 0.
PAGE 765
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 23.2.12 Analog Comparator Table 23-32. Analog Comparator Characteristics Parameter Parameter Name Min Nom Max Unit VOS Input offset voltage - ±10 ±25 mV VCM Input common mode voltage range 0 - VDD-1.5 V CMRR Common mode rejection ratio 50 - - dB TRT Response time - - 1 µs TMC Comparator mode change to Output Valid - - 10 µs Table 23-33.
PAGE 766
NRND: Not recommended for new designs. Serial Flash Loader A Serial Flash Loader A.1 Serial Flash Loader ® The Stellaris serial flash loader is a preprogrammed flash-resident utility used to download code to the flash memory of a device without the use of a debug interface. The serial flash loader uses a simple packet interface to provide synchronous communication with the device. The flash loader runs off the crystal and does not enable the PLL, so its speed is determined by the crystal used.
PAGE 767
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller the flash loader. Since the host device is the master, the SSI on the flash loader device does not need to determine the clock as it is provided directly by the host. A.3 Packet Handling All communications, with the exception of the UART auto-baud, are done via defined packets that are acknowledged (ACK) or not acknowledged (NAK) by the devices.
PAGE 768
NRND: Not recommended for new designs. Serial Flash Loader flash loader only accepts the first non-zero data as a valid response. This zero padding is needed by the SSI interface in order to receive data to or from the flash loader. A.4 Commands The next section defines the list of commands that can be sent to the flash loader. The first byte of the data should always be one of the defined commands, followed by data or parameters as determined by the command that is sent. A.4.
PAGE 769
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller Byte[8] = Program Size [23:16] Byte[9] = Program Size [15:8] Byte[10] = Program Size [7:0] A.4.4 COMMAND_SEND_DATA (0x24) This command should only follow a COMMAND_DOWNLOAD command or another COMMAND_SEND_DATA command if more data is needed. Consecutive send data commands automatically increment address and continue programming from the previous location.
PAGE 770
NRND: Not recommended for new designs. Serial Flash Loader Byte[0] = 3 Byte[1] = checksum(Byte[2]) Byte[2] = COMMAND_RESET The flash loader responds with an ACK signal back to the host device before actually executing the software reset to the device running the flash loader. This allows the host to know that the command was received successfully and the part will be reset.
PAGE 771
NRND: Not recommended for new designs.
PAGE 772
NRND: Not recommended for new designs. Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PSR, type R/W, , reset 0x0100.0000 (see page 67) N Z C V Q ICI / IT THUMB ICI / IT ISRNUM PRIMASK, type R/W, , reset 0x0000.0000 (see page 71) PRIMASK FAULTMASK, type R/W, , reset 0x0000.0000 (see page 72) FAULTMASK BASEPRI, type R/W, , reset 0x0000.0000 (see page 73) BASEPRI CONTROL, type R/W, , reset 0x0000.
PAGE 773
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UNPEND1, type R/W, offset 0x284, reset 0x0000.0000 INT ACTIVE0, type RO, offset 0x300, reset 0x0000.0000 INT INT ACTIVE1, type RO, offset 0x304, reset 0x0000.0000 INT PRI0, type R/W, offset 0x400, reset 0x0000.0000 INTD INTC INTB INTA PRI1, type R/W, offset 0x404, reset 0x0000.
PAGE 774
NRND: Not recommended for new designs. Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ISRPRE ISRPEND INTCTRL, type R/W, offset 0xD04, reset 0x0000.0000 NMISET PENDSV UNPENDSV PENDSTSET PENDSTCLR VECPEND VECPEND RETBASE VECACT VTABLE, type R/W, offset 0xD08, reset 0x0000.0000 BASE OFFSET OFFSET APINT, type R/W, offset 0xD0C, reset 0xFA05.
PAGE 775
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MPUBASE, type R/W, offset 0xD9C, reset 0x0000.0000 ADDR ADDR VALID REGION VALID REGION VALID REGION VALID REGION MPUBASE1, type R/W, offset 0xDA4, reset 0x0000.0000 ADDR ADDR MPUBASE2, type R/W, offset 0xDAC, reset 0x0000.0000 ADDR ADDR MPUBASE3, type R/W, offset 0xDB4, reset 0x0000.
PAGE 776
NRND: Not recommended for new designs. Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RCC2, type R/W, offset 0x070, reset 0x0780.2810 (see page 203) USERCC2 SYSDIV2 PWRDN2 BYPASS2 OSCSRC2 DSLPCLKCFG, type R/W, offset 0x144, reset 0x0780.
PAGE 777
NRND: Not recommended for new designs.
PAGE 778
NRND: Not recommended for new designs. Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 COMT MERASE ERASE WRITE PRIS ARIS PMASK AMASK PMISC AMISC DBG1 DBG0 FMD, type R/W, offset 0x004, reset 0x0000.0000 DATA DATA FMC, type R/W, offset 0x008, reset 0x0000.0000 WRKEY FCRIS, type RO, offset 0x00C, reset 0x0000.0000 FCIM, type R/W, offset 0x010, reset 0x0000.
PAGE 779
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FMPPE3, type R/W, offset 0x40C, reset 0xFFFF.FFFF PROG_ENABLE PROG_ENABLE General-Purpose Input/Outputs (GPIOs) GPIO Port A base: 0x4000.4000 GPIO Port B base: 0x4000.5000 GPIO Port C base: 0x4000.6000 GPIO Port D base: 0x4000.7000 GPIO Port E base: 0x4002.4000 GPIO Port F base: 0x4002.
PAGE 780
NRND: Not recommended for new designs. Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIOPUR, type R/W, offset 0x510, reset - (see page 317) PUE GPIOPDR, type R/W, offset 0x514, reset 0x0000.0000 (see page 318) PDE GPIOSLR, type R/W, offset 0x518, reset 0x0000.0000 (see page 319) SRL GPIODEN, type R/W, offset 0x51C, reset - (see page 320) DEN GPIOLOCK, type R/W, offset 0x520, reset 0x0000.
PAGE 781
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GPIOPCellID3, type RO, offset 0xFFC, reset 0x0000.00B1 (see page 335) CID3 General-Purpose Timers Timer0 base: 0x4003.0000 Timer1 base: 0x4003.1000 Timer2 base: 0x4003.2000 Timer3 base: 0x4003.3000 GPTMCFG, type R/W, offset 0x000, reset 0x0000.
PAGE 782
NRND: Not recommended for new designs. Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESEN INTEN GPTMTBPMR, type R/W, offset 0x044, reset 0x0000.0000 (see page 370) TBPSMR GPTMTAR, type RO, offset 0x048, reset 0xFFFF.FFFF (see page 371) TARH TARL GPTMTBR, type RO, offset 0x04C, reset 0x0000.FFFF (see page 372) TBRL Watchdog Timer Base 0x4000.0000 WDTLOAD, type R/W, offset 0x000, reset 0xFFFF.
PAGE 783
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ASEN3 ASEN2 ASEN1 ASEN0 INR3 INR2 INR1 INR0 MASK3 MASK2 MASK1 MASK0 IN3 IN2 IN1 IN0 OV3 OV2 OV1 OV0 UV1 UV0 WDTPeriphID2, type RO, offset 0xFE8, reset 0x0000.0018 (see page 391) PID2 WDTPeriphID3, type RO, offset 0xFEC, reset 0x0000.
PAGE 784
NRND: Not recommended for new designs. Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADCSSCTL0, type R/W, offset 0x044, reset 0x0000.
PAGE 785
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OE BE PE FE EPS PEN BRK SIRLP SIREN UARTEN Universal Asynchronous Receivers/Transmitters (UARTs) UART0 base: 0x4000.C000 UART1 base: 0x4000.D000 UARTDR, type R/W, offset 0x000, reset 0x0000.0000 (see page 443) OE BE PE FE DATA UARTRSR/UARTECR, type RO, offset 0x004, reset 0x0000.
PAGE 786
NRND: Not recommended for new designs. Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UARTPeriphID6, type RO, offset 0xFD8, reset 0x0000.0000 (see page 466) PID6 UARTPeriphID7, type RO, offset 0xFDC, reset 0x0000.0000 (see page 467) PID7 UARTPeriphID0, type RO, offset 0xFE0, reset 0x0000.0011 (see page 468) PID0 UARTPeriphID1, type RO, offset 0xFE4, reset 0x0000.
PAGE 787
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TXMIS RXMIS RTMIS RORMIS RTIC RORIC SSIMIS, type RO, offset 0x01C, reset 0x0000.0000 (see page 500) SSIICR, type W1C, offset 0x020, reset 0x0000.0000 (see page 501) SSIPeriphID4, type RO, offset 0xFD0, reset 0x0000.0000 (see page 502) PID4 SSIPeriphID5, type RO, offset 0xFD4, reset 0x0000.
PAGE 788
NRND: Not recommended for new designs. Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ACK STOP START RUN I2CMCS, type WO, offset 0x004, reset 0x0000.0000 (Writes) I2CMDR, type R/W, offset 0x008, reset 0x0000.0000 DATA I2CMTPR, type R/W, offset 0x00C, reset 0x0000.0001 TPR I2CMIMR, type R/W, offset 0x010, reset 0x0000.0000 IM I2CMRIS, type RO, offset 0x014, reset 0x0000.
PAGE 789
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TEST CCE DAR EIE SIE IE INIT BOFF EWARN EPASS Controller Area Network (CAN) Module CAN0 base: 0x4004.0000 CANCTL, type R/W, offset 0x000, reset 0x0000.0001 (see page 573) CANSTS, type R/W, offset 0x004, reset 0x0000.0000 (see page 575) RXOK TXOK LEC CANERR, type RO, offset 0x008, reset 0x0000.
PAGE 790
NRND: Not recommended for new designs. Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CANIF2ARB1, type R/W, offset 0x090, reset 0x0000.0000 (see page 588) ID CANIF1ARB2, type R/W, offset 0x034, reset 0x0000.0000 (see page 589) MSGVAL XTD DIR ID CANIF2ARB2, type R/W, offset 0x094, reset 0x0000.0000 (see page 589) MSGVAL XTD DIR ID CANIF1MCTL, type R/W, offset 0x038, reset 0x0000.
PAGE 791
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PHYINT MDINT RXER FOV TXEMP TXER RXINT PHYINT MDINT RXER FOV TXEMP TXER RXINT RXERM FOVM TXEMPM TXERM RXINTM PRMS AMUL RXEN CRC PADEN TXEN WRITE START CANMSG1INT, type RO, offset 0x140, reset 0x0000.0000 (see page 596) INTPND CANMSG2INT, type RO, offset 0x144, reset 0x0000.
PAGE 792
NRND: Not recommended for new designs. Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MACMTXD, type R/W, offset 0x02C, reset 0x0000.0000 MDTX MACMRXD, type R/W, offset 0x030, reset 0x0000.0000 MDRX MACNP, type RO, offset 0x034, reset 0x0000.0000 NPR MACTR, type R/W, offset 0x038, reset 0x0000.0000 NEWTX MACTS, type R/W, offset 0x03C, reset 0x0000.
PAGE 793
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ACINTEN, type R/W, offset 0x008, reset 0x0000.0000 (see page 654) IN0 ACREFCTL, type R/W, offset 0x010, reset 0x0000.0000 (see page 655) EN RNG VREF ACSTAT0, type RO, offset 0x020, reset 0x0000.0000 (see page 656) OVAL ACCTL0, type R/W, offset 0x024, reset 0x0000.
PAGE 794
NRND: Not recommended for new designs.
PAGE 795
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PWM0CMPB, type R/W, offset 0x05C, reset 0x0000.0000 (see page 688) CompB PWM1CMPB, type R/W, offset 0x09C, reset 0x0000.0000 (see page 688) CompB PWM2CMPB, type R/W, offset 0x0DC, reset 0x0000.0000 (see page 688) CompB PWM0GENA, type R/W, offset 0x060, reset 0x0000.
PAGE 796
NRND: Not recommended for new designs. Register Quick Reference 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Swap Enable Direction Error PWM2DBFALL, type R/W, offset 0x0F0, reset 0x0000.0000 (see page 697) FallDelay Quadrature Encoder Interface (QEI) QEI0 base: 0x4002.C000 QEI1 base: 0x4002.D000 QEICTL, type R/W, offset 0x000, reset 0x0000.
PAGE 797
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller C Ordering and Contact Information C.
PAGE 798
NRND: Not recommended for new designs. Ordering and Contact Information C.3 Kits The Stellaris Family provides the hardware and software tools that engineers need to begin development quickly.
PAGE 799
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller D Package Information D.1 100-Pin LQFP Package D.1.1 Package Dimensions Figure D-1. Stellaris LM3S8962 100-Pin LQFP Package Dimensions Note: The following notes apply to the package drawing. 1. All dimensions shown in mm. 2. Dimensions shown are nominal with tolerances indicated. 3. Foot length 'L' is measured at gage plane 0.25 mm above seating plane.
PAGE 800
NRND: Not recommended for new designs. Package Information Body +2.00 mm Footprint, 1.4 mm package thickness Symbols Leads 100L A Max. 1.60 A1 - 0.05 Min./0.15 Max. A2 ±0.05 1.40 D ±0.20 16.00 D1 ±0.05 14.00 E ±0.20 16.00 E1 ±0.05 14.00 L +0.15/-0.10 0.60 e Basic 0.50 b +0.05 0.22 θ - 0˚-7˚ ddd Max. 0.08 ccc Max. 0.
PAGE 801
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller D.1.2 Tray Dimensions Figure D-2. 100-Pin LQFP Tray Dimensions D.1.3 Tape and Reel Dimensions Note: In the figure that follows, pin 1 is located in the top right corner of the device.
PAGE 802
NRND: Not recommended for new designs. Package Information Figure D-3. 100-Pin LQFP Tape and Reel Dimensions THIS IS A COMPUTER GENERATED UNCONTROLLED DOCUMENT PRINTED ON 06.01.2003 06.01.2003 06.01.2003 MUST NOT BE REPRODUCED WITHOUT WRITTEN PERMISSION FROM SUMICARRIER (S) PTE LTD 06.01.2003 06.01.
PAGE 803
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller D.2 108-Ball BGA Package D.2.1 Package Dimensions Figure D-4.
PAGE 804
NRND: Not recommended for new designs. Package Information Note: The following notes apply to the package drawing. Symbols MIN NOM MAX A 1.22 1.36 1.50 A1 0.29 0.34 0.39 A3 0.65 0.70 0.75 c 0.28 0.32 0.36 D 9.85 10.00 10.15 D1 E 8.80 BSC 9.85 E1 b 10.00 8.80 BSC 0.43 0.48 bbb 0.53 .20 ddd .12 e 0.80 BSC f 10.15 - 0.
PAGE 805
NRND: Not recommended for new designs. ® Stellaris LM3S8962 Microcontroller D.2.2 Tray Dimensions Figure D-5.
PAGE 806
NRND: Not recommended for new designs. Package Information D.2.3 Tape and Reel Dimensions Figure D-6.
PAGE 807
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.