Datasheet

Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058
On a read, this register gives the current masked status value of the corresponding interrupt. All of
the bits are R/W1C and this action also clears the corresponding raw interrupt bit in the RIS register
(see page 194).
Masked Interrupt Status and Clear (MISC)
Base 0x400F.E000
Offset 0x058
Type R/W1C, reset 0x0000.0000
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
reserved
BORMISreservedPLLLMISreserved
ROR/W1CROROROROR/W1CROROROROROROROROROType
0000000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved31:7
PLL Lock Masked Interrupt Status
This bit is set when the PLL T
READY
timer asserts. The interrupt is cleared
by writing a 1 to this bit.
0R/W1CPLLLMIS6
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved5:2
BOR Masked Interrupt Status
The BORMIS is simply the BORRIS ANDed with the mask value, BORIM.
0R/W1CBORMIS1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0ROreserved0
June 18, 2012196
Texas Instruments-Production Data
System Control
NRND: Not recommended for new designs.