Datasheet

This register provides user-enabled stalling when the microcontroller asserts the CPU halt flag

during debug.

Watchdog Test (WDTTEST)

Base 0x4000.0000

Offset 0x418

Type R/W, reset 0x0000.0000

16171819202122232425262728293031

reserved

ROROROROROROROROROROROROROROROROType

0000000000000000Reset

0123456789101112131415

reservedSTALLreserved

ROROROROROROROROR/WROROROROROROROType

0000000000000000Reset

DescriptionResetTypeNameBit/Field

Software should not rely on the value of a reserved bit. To provide

compatibility with future products, the value of a reserved bit should be

preserved across a read-modify-write operation.

0x00ROreserved31:9

Watchdog Stall Enable

When set to 1, if the Stellaris microcontroller is stopped with a debugger,

the watchdog timer stops counting. Once the microcontroller is restarted,

the watchdog timer resumes counting.

0R/WSTALL8

Software should not rely on the value of a reserved bit. To provide

compatibility with future products, the value of a reserved bit should be

preserved across a read-modify-write operation.

0x00ROreserved7:0

383June 18, 2012

Texas Instruments-Production Data

Stellaris

LM3S8962 Microcontroller

NRND: Not recommended for new designs.