Datasheet

Register 4: SSI Status (SSISR), offset 0x00C
SSISR is a status register that contains bits that indicate the FIFO fill status and the SSI busy status.
SSI Status (SSISR)
SSI0 base: 0x4000.8000
Offset 0x00C
Type RO, reset 0x0000.0003
16171819202122232425262728293031
reserved
ROROROROROROROROROROROROROROROROType
0000000000000000Reset
0123456789101112131415
TFETNFRNERFFBSYreserved
R0ROROROROROROROROROROROROROROROType
1100000000000000Reset
DescriptionResetTypeNameBit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00ROreserved31:5
SSI Busy Bit
The BSY values are defined as follows:
DescriptionValue
SSI is idle.0
SSI is currently transmitting and/or receiving a frame, or the
transmit FIFO is not empty.
1
0ROBSY4
SSI Receive FIFO Full
The RFF values are defined as follows:
DescriptionValue
Receive FIFO is not full.0
Receive FIFO is full.1
0RORFF3
SSI Receive FIFO Not Empty
The RNE values are defined as follows:
DescriptionValue
Receive FIFO is empty.0
Receive FIFO is not empty.1
0RORNE2
SSI Transmit FIFO Not Full
The TNF values are defined as follows:
DescriptionValue
Transmit FIFO is full.0
Transmit FIFO is not full.1
1ROTNF1
June 18, 2012494
Texas Instruments-Production Data
Synchronous Serial Interface (SSI)
NRND: Not recommended for new designs.