Datasheet
APPLICATION INFORMATION
Start-Up Characteristics
1-Hz Rate
V
Z
LM4040
R
S
V
IN
Output Capacitor
SOT-23 Connections
Use With ADCs or DACs
28
27
26
25
24
23
22
21
20
19
18
17
16
1514
13
12
11
10
9
8
1
2
3
4
5
6
7
V
REF
AIN0
AIN1
AIN2
AGND
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DGND
AIN3
V
ANA
2.2 µF
A1
A0
CLK
DB0
DB1
DB2
DB3
DB4
V
DIG
BUSY
WR
CS
RD
3.2-MHz Clock
BUSY Output
Write Input
Read Input
5-V Analog Supply
10 µF
+
+ +
0.1 µF
ADS7842
LM4040A-41
909
0 V to V
REF
5 V
LM4040
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.................................................................................................................................................. SLOS456K – JANUARY 2005 – REVISED MARCH 2008
Figure 7. Test Circuit
The LM4040 does not require an output capacitor across cathode and anode for stability. However, if an output
bypass capacitor is desired, the LM4040 is designed to be stable with all capacitive loads.
There is a parasitic Schottky diode connected between pins 2 and 3 of the SOT-23 packaged device. Thus, pin 3
of the SOT-23 package must be left floating or connected to pin 2.
The LM4040x-41 is designed to be a cost-effective voltage reference as required in 12-bit data-acquisition
systems. For 12-bit systems operating from 5-V supplies such as the ADS7842 (see Figure 8 ), the LM4040x-41
(4.096 V) permits operation with an LSB of 1 mV.
Figure 8. Data-Acquisition Circuit With LM4040x-41
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