Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsLinear IC - Audio amplifier 1-channel (mono) with mono and stereo headphones Class D DS

LM49350, LM49350RLEVAL

www.ti.com

SNAS359D –SEPTEMBER 2008–REVISED JUNE 2012

LM49350 Boomer® Audio Power Amplifier Series High Performance Audio Codec Sub-

System with a Ground-Referenced Stereo Headphone Amplifier & an Ultra Low EMI Class

D Loudspeaker Amplifier with Dual I

S/PCM Digital Audio Interfaces

Check for Samples: LM49350, LM49350RLEVAL

FEATURES

• Micro-Power Shutdown Mode

• Available in the 3.5 x 3.5 mm 36 Bump DSBGA

• High Performance 96dB SNR Stereo DAC

Package

• High Performance 94dB SNR Stereo ADC

• Up to 192kHz Stereo Audio Playback

APPLICATIONS

• Up to 48kHz Stereo Recording

• Smart Phones

• Dual Bidirectional I

S or PCM Compatible

• Mobile Phones and VOIP Phones

Audio Interfaces

• Portable GPS Navigator and Portable Gaming

• Read/Write I

C Compatible Control Interface

Devices

• Flexible Digital Mixer with Sample Rate

• Portable DVD/CD/AAC/MP3/MP4 Players

Conversion

• Digital Cameras/Camcorders

• Dual Sigma-Delta PLLs for Operation from any

Clock at Any Sample rate

KEY SPECIFICATIONS

• Digital 3D Stereo Enhancement

• P

at A_V

= 3.3V, Stereo 32Ω, 1% THD

• Dual 5 Band Parametric Equalizers

69mW/ch (typ)

• Cascadable DSP Effects that Allow 10 Band

• P

at LS_V

= 5V, 8Ω, 1% THD 1.2W (typ)

Parametric Equalization

• P

at LS_V

= 4.2V, 8Ω, 1% THD 825mW (typ)

• ALC/Compressor/Limiter on Both DAC and

• P

at LS_V

= 3.3V, 8Ω, 1% THD 495mW (typ)

ADC Paths

• P

at A_V

= 3.3V, 32Ω BTL, 1% THD 58mW

• Ultra Low EMI, Class D Loudspeaker Amplifier

(typ)

with Spread Spectrum Control

• Supply Voltage Range

• Ground Referenced Output Cap-Less

– D_V

= 1.7V to 2.0V

Headphone Amplifier Operation

– LS_V

and A_V

= 2.7V to 5.5V

• Earpiece Speaker Amplifier with Reduced

Power Consumption Mode for Mono

– I/O_V

= 1.6V to 4.5V

Differential Line out Applications

• SNR (Stereo DAC at 48kHz) 96dB (typ)

• Stereo Auxiliary Inputs or Mono Differential

• SNR (Stereo ADC at 48kHz) 94dB (typ)

Input

• PSRR at 217 Hz, A_V

= 3.3V, (HP from AUX)

• Differential Stereo Microphone Inputs with

97dB (typ)

Single-Ended Option

• Automatic Level Control for Digital Audio

DESCRIPTION

Inputs, Stereo Microphone Inputs, and Stereo

The LM49350 is a high performance audio subsystem

Auxiliary Inputs

that supports both analog and digital audio functions.

The LM49350 includes a high quality stereo DAC, a

• Flexible Audio Routing from Input to Output

high quality stereo ADC, a stereo headphone

• 16 Step Volume Control for Microphones with

amplifier that supports ground referenced output cap-

2dB Steps

less operation, a dual mode earpiece speaker

• 32 Step Volume Control for Auxiliary Inputs in

amplifier, and a low EMI Class D loudspeaker

1.5dB Steps

amplifier. It is designed for demanding applications in

mobile phones and other portable devices.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (108 pages)

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LM49350, LM49350RLEVAL www.ti.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com DESCRIPTION CONTINUED The LM49350 features dual bi-directional I2S or PCM audio interfaces for full range audio and an I2C compatible interface for control. The stereo DAC path features an SNR of 96dB with 24-bit 48 kHz input. The headphone amplifier delivers 69mWRMS (typ) to a 32Ω single-ended stereo load with less than 1% distortion (THD+N) when A_VDD = 3.3V.
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LM49350, LM49350RLEVAL www.ti.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com Typical Application D_VDD I/O_VDD A_VDD LS_VDD LEFT_MIC- HP_VSS LEFT_MIC+ VREF 0.5 - 50 MHz CP+ MIC_BIAS CP- RIGHT_MIC+ RIGHT_MIC- MCLK 2 I C LM49350 Baseband Controller 2 I S/PCM (PORT1) GPIO HPL HPR LS+ LS8O AUX_OUT+ Bluetooth Transceiver 2 I S/PCM (PORT2) AUX_OUT- 32O DGND LSGND AGND AUX_L AUX_R Synthesized FM Radio/TV Tuner Figure 2.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 D_VDD I/O_VDD A_VDD LS_VDD LEFT_MIC- HP_VSS LEFT_MIC+ VREF 0.5 - 50 MHz CP+ MIC_BIAS CP- RIGHT_MIC+ RIGHT_MIC- MCLK 2 I C LM49350 Baseband Controller 2 I S/PCM (PORT1) HPL HPR LS+ LS- AUX_OUT+ Bluetooth Transceiver 2 I S/PCM (PORT2) LM4675 AUX_OUTGPIO DGND LSGND AGND AUX_L AUX_R LM4675 Can Be Used for Stereo 8: Loudspeakers Synthesized FM Radio/TV Tuner Figure 3.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com D_VDD I/O_VDD A_VDD LEFT_MIC- HP_VSS LEFT_MIC+ VREF 0.5 - 50 MHz LS_VDD CP+ MIC_BIAS CP- RIGHT _MIC+ RIGHT _MIC- MCLK 2 I C Baseband Controller HPL LM49350 2 I S/PCM (PORT1) GPIO HPR LS+ LS- AUX_OUT+ Bluetooth Transceiver 2 I S/PCM (PORT2) AUX_OUTMONO_IN+ Voice Modem MONO_INDGND LSGND AGND Figure 4.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 D_VDD I/O_VDD A_VDD LS_VDD LEFT_MIC- HP_VSS LEFT_MIC+ VREF 0.5 - 50 MHz CP+ MIC_BIAS CP- HPL MCLK HPR 2 I C LM49350 MP3/MP4 CODEC 2 LS+ LS- I S/PCM (PORT1) AUX_OUT+ LM4675 AUX_OUTGPIO LM4675 Can Be Used for Stereo Loudspeakers Bluetooth Transceiver 2 I S/PCM (PORT2) RIGHT_LINE+ RIGHT_LINEAUX_IN+ DGND LSGND AGND AUX_IN- Synthesized FM Radio/ TV Tuner (Stereo Differential) Figure 5.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com Connection Diagram Figure 6.
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LM49350, LM49350RLEVAL www.ti.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com OPERATING RATINGS −40°C to +85°C Temperature Range Supply Voltage (1) A_VDD and LS_VDD (1) 2.7V to 5.5V D_VDD 1.7V to 2.0V I/O_VDD 1.6V to 4.5V LS_VDD need to be the highest voltage than A_VDD, D_VDD, and I/O_VDD. For proper power supply sequence, LS_VDD need to be applied first. ELECTRICAL CHARACTERISTICS: A_VDD = LS_VDD = 3.3V; D_VDD = I/O_VDD = 1.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 ELECTRICAL CHARACTERISTICS: A_VDD = LS_VDD = 3.3V; D_VDD = I/O_VDD = 1.8V(1)(2) (continued) The following specifications apply for RL(LS) = 8Ω, RL(HP) = 32Ω, f = 1kHz, unless otherwise specified. Limits apply for TA = 25°C.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com ELECTRICAL CHARACTERISTICS: A_VDD = LS_VDD = 3.3V; D_VDD = I/O_VDD = 1.8V(1)(2) (continued) The following specifications apply for RL(LS) = 8Ω, RL(HP) = 32Ω, f = 1kHz, unless otherwise specified. Limits apply for TA = 25°C. Symbol VOS Parameter Limit (4) Units (Limits) 0.5 6 mV (max) DAC Gain = 0dB, From DAC Input fMCLK = 12.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 ELECTRICAL CHARACTERISTICS: A_VDD = LS_VDD = 3.3V; D_VDD = I/O_VDD = 1.8V(1)(2) (continued) The following specifications apply for RL(LS) = 8Ω, RL(HP) = 32Ω, f = 1kHz, unless otherwise specified. Limits apply for TA = 25°C. Symbol Parameter Conditions LM49350 Typical (3) Limit (4) Units (Limits) MIC BIAS VBIAS Microphone Bias Voltage MIC input selected 2.2 V –46.5 dB Maximum Gain 12 dB Minimum Gain –76.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com TIMING CHARACTERISTICS: DVDD = I/OVDD = 1.8V (1) (2) The following specifications apply for RL(SP) = 8Ω, RL(HP) = 32Ω, f = 1kHz, unless otherwise specified. Limits apply for TA = 25°C. LM49350 Symbol Parameter Conditions Typical (3 ) Limit (4) Units (Limits) PLL fIN PLL Input Frequency Range Minimum MCLK Frequency 0.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 TIMING CHARACTERISTICS: DVDD = I/OVDD = 1.8V (1) (2) The following specifications apply for RL(SP) = 8Ω, RL(HP) = 32Ω, f = 1kHz, unless otherwise specified. Limits apply for TA = 25°C. LM49350 Symbol Parameter Conditions Typical ( 3) Limit (4) Units (Limit) PLL fIN PLL Input Frequency Range Minimum MCLK Frequency 0.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com TCLK_H TCLK_L I2S_CLKPER I2S_CLK (CLK_PHASE = 0) I2S_WS TWS_DLY I2S_SDI tDST tDHT I2S_SDO TSDO_DLY w = write (SDA = “0”) r = read (SDA = “1”) ack = acknowledge (SDA pulled down by slave) rs = repeated start Figure 7.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 TYPICAL PERFORMANCE CHARACTERISTICS +1 DAC Frequency Response fS = 48kHz, OSR = 128 +1 +0.8 DAC Frequency Response fS = 8kHz, OSR = 128 +0.5 +0.6 MAGNITUDE (dB) MAGNITUDE (dB) -0 +0.4 +0.2 +0 -0.2 -0.4 -0.5 -1 -1.5 -2 -0.6 -2.5 -0.8 -1 20 -3 50 100 200 500 1k 2k 20 5k 10k 20k 50 100 200 500 1k 2k 4k FREQUENCY (Hz) FREQUENCY (Hz) Figure 9. Figure 10.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Mono Voice ADC Frequency Response fS = 8kHz, OSR = 128, CIN = 1μF, MIC gain = 6dB Mono Voice ADC HPF Frequency Response fS = 48kHz, OSR = 128, CIN = 1μF, MIC gain = 6dB (Top-No HPF) (From Left to Right: HPF_Mode = '000', '001', '010', '011', '100') +1 +0 +0.5 -10 -20 MAGNITUDE (dB) MAGNITUDE (dB) -0 -0.5 -1 -1.5 -2 -30 -40 -50 -60 -70 -80 -2.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 TYPICAL PERFORMANCE CHARACTERISTICS (continued) ADC Output THD+N vs VIN Differential MIC Input, MIC Gain = 6dB VIN = 1kHz, fS = 48kHz Loudspeaker THD+N vs Frequency Differential Aux Input, Aux Gain = 0dB VDD = 3.3V, POUT = 400mW, RL = 8Ω 10 10 5 2 2 1 1 THD+N (%) THD+N (%) 5 0.5 0.2 0.5 0.2 0.1 0.1 0.05 0.05 0.02 0.02 0.01 1m 2m 0.01 20 5m 10m 20m 50m100m 200m 500m 1 50 100 200 500 1k 2k Figure 21.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Loudspeaker THD+N vs Output Power Differential Aux Input, Aux Gain = 0dB VDD = 5V, VIN = 1kHz, RL = 8Ω Loudspeaker THD+N vs Output Power Differential Aux Input, Aux Gain = 0dB LS_VDD = 3.3V, RL = 4Ω, f = 1kHz 10 5 5 2 2 1 1 THD + N (%) THD+N (%) 10 0.5 0.2 0.1 0.5 0.2 0.1 0.05 0.05 0.02 0.02 0.01 10m 20m 50m 100m 200m 500m 1 0.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 TYPICAL PERFORMANCE CHARACTERISTICS (continued) +0 Loudspeaker PSRR vs Frequency LS_VDD = 5V, Aux Gain = 0dB Differential Aux Input to Ground VRIPPLE = 200mVPP Headphone THD+N vs Frequency Stereo Aux Input, Aux Gain = 0dB VDD = 3.3V, POUT = 7.5mW, RL = 32Ω 10 5 -10 2 1 -40 0.5 THD+N (%) PSRR (dB) -20 -30 -50 -60 -70 -80 0.2 0.1 0.05 0.02 0.01 0.005 -90 -100 -110 0.002 0.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Headphone THD+N vs Output Power A_VDD = 3.3V, Stereo Aux Input, Aux Gain = 0dB RL = 16Ω, f = 1kHz 10 Headphone PSRR vs Frequency Differential Aux Input to Ground, Aux Gain = 0dB VRIPPLE = 200mVPP +0 -10 5 -30 1 -40 PSRR (dB) THD + N (%) -20 2 0.5 0.2 0.1 -50 -60 -70 -80 -90 0.05 -100 0.02 0.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 TYPICAL PERFORMANCE CHARACTERISTICS (continued) AUXOUT THD+N vs Frequency Differential Aux Input, Aux Gain = 0dB VDD = 5V, VOUT = 1VRMS, RL = 5kΩ AUXOUT THD+N vs Output Voltage Differential Aux Input, Aux Gain = 0dB VIN = 1kHz, RL = 5kΩ 10 5 10 2 1 2 1 0.5 5 THD+N (%) THD+N (%) 0.5 0.2 0.1 0.05 0.02 0.01 0.005 0.002 0.001 20 0.2 0.1 0.05 0.02 0.01 0.005 50 100 200 500 1k 2k 0.002 0.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com SYSTEM CONTROL Method 1. I2C Compatible Interface I2C SIGNALS In I2C mode the LM49350 pin SCL is used for the I2C clock SCL and the pin SDA is used for the I2C data signal SDA. Both these signals need a pull-up resistor according to I2C specification. The I2C slave address for LM49350 is 00110102. I2C DATA VALIDITY The data on SDA line must be stable during the HIGH period of the clock signal (SCL).
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 MSB LSB ADR6 Bit7 ADR5 bit6 ADR4 bit5 ADR3 bit4 ADR2 bit3 ADR1 bit2 ADR0 bit1 R/W bit0 2 I C SLAVE address (chip address) Figure 50. I2C Chip Address Register changes take effect at the SCL rising edge during the last ACK from slave.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com I2C TIMING PARAMETERS (1) Symbol (1) 26 Limit Parameter 1 Hold Time (repeated) START Condition 2 3 Min Max Units 0.6 µs Clock Low Time 1.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 Device Register Map Table 1.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com Table 1.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 Table 1.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com Table 1.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 Basic PMC Setup Register This register is used to control the LM49350's Basic Power Management Setup: Table 2. PMC_SETUP (0x00h) Bits 0 Field CHIP_ENABLE Description When this bit is set the power management will enable the MCLK I/O or internal oscillator (1). It will then use this clock to sequence the enabling of the analog references and bias points.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com PMC Clocks Register This register is used to control the LM49350's Basic Power Management Setup: Table 3. PMC_SETUP (0x01h) Bits Field 1:0 PMC_CLK_SEL Description This selects the source of the PMC input clock.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 The LM49350's Power Management Circuit (PMC) requires a clock that is independent from the DAC or ADC. It is recommended to provide a ≈300kHz clock at Point C. The PMC clock divider (R divider) is available to generate the correct clock to the PMC block. The PMC clock path can be driven directly by the MCLK input, the internal 300kHz oscillator, the DAC_SOURCE_CLK, or the ADC_SOURCE_CLK. Table 5.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com -300 kHz INTERNAL OSCILLATOR %R C PMC A PLL2 %S Stereo DAC 1 ± 25 MHz 0 _> 50 MHz PLL1 MCLK MIXER 0 _ 50 MHz %T Stereo ADC B AUDIO PORT 1 PORT1_CLK 0 _ 50 MHz R, S, T = Half Cycle 1, 1.5, 2, 2.5 _> 128 AUDIO PORT 2 PORT2_CLK Figure 54. Internal Clock Network PLL Setup Registers PLL_P2 1 ± 25 MHz % P1 9 P2A = 0,1 + 0/2 _> 256 P= 0.1 + 0/2 _> 64 0.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 The LM49350 contains two PLLs for flexible operation of its dual audio ports. PLL1 has a P1 and P2 output divider thereby allowing PLL1 to generate two distinct clock outputs. The equations for PLL1's generated output clocks are as follows: fOUT1 = (fIN . N1 / M1 . P1) fOUT2 = (fIN . N1 / M1 .
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com Table 7. PLL Settings for Common System Clock Frequencies (continued) fIN (MHz) M N N_MOD P fOUT (MHz) Error (Hz) 16.8 7 85 0 17 12000000 0 19.2 8 85 0 17 12000000 0 19.68 20.5 200 0 16 12000000 0 19.8 16.5 170 0 17 12000000 0 11.2896 8 125 0 16 11025000 0 12 10 147 0 16 11025000 0 12.288 8 114 27 16 11025000 0 13 6.5 96 15 17.5 11025000 0 13.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 Table 10. PLL1_N (0x05h) Bits Field 7:0 PLL1_N Description This programs the PLL1 N divider to divide from 1 to 250. PLL1_N Feedback Divider Value 00000000 to 00001010 10 00001011 11 00001100 12 00001101 13 00001110 14 00001111 15 — — 11111000 248 11111001 249 11111010 to 11111111 250 Table 11.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com Table 13. PLL1_P2 (0x08h) Bits Field 7:0 PLL1_P2[7:0] Description This programs 8 LSBs of PLL1's P2 Divider. These LSBs combine with PLL1_P2[8] which allows the P2 divider to divide by up to 256 PLL1_P2 P2 Divider Value 000000000 1 000000001 1 000000010 1.5 000000011 2 000000100 2.5 000000101 3 — — 111111101 255 111111110 255.5 111111111 256 Table 14.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 Table 16. PLL2_N_MOD (0x0Bh) Bits Field 4:0 PLL2_N_MOD Description This programs the sigma-delta modulator in PLL2 PLL2_N_MOD 5 PLL2_P[8] Fractional Part of N 00000 0 00001 1/32 00010 2/32 00011 3/32 00100 4/32 00101 5/32 — — 11101 29/32 11110 30/32 11111 31/32 This is the MSB of the P Divider on PLL2. Table 17.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com CLASS D LOUDSPEAKER AMPLIFIER The LM49350 features a filterless modulation scheme. The differential outputs of the device switch at 300kHz from VDD to GND. When there is no input signal applied, the two outputs (LS+ and LS-) switch with a 50% duty cycle, with both outputs in phase. Because the outputs of the LM49350 are differential, the two signals cancel each other.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 LS+ Ferrite Bead LM49350 Class D Speaker 10 pF LSFerrite Bead 10 pF LSGND Figure 57. EMI/RFI Filter for the Class D Amplifier Table 19. LEFT HEADPHONE_OUTPUT (0x11h) Bits Field Description 0 DACR_HPL The right DAC output is added to the left headphone output. 1 DACL_HPL The left DAC output is added to the left headphone output. 2 MICR_HPL The right MIC input is added to the left headphone output.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com CHARGE PUMP FLYING CAPACITOR (C6) The flying capacitor (C6) affects the load regulation and output impedance of the charge pump. A C6 value that is too low results in a loss of current drive, leading to a loss of amplifier headroom. A higher valued C6 improves load regulation and lowers charge pump output impedance to an extent. Above 2.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 Table 23. ADC_INPUT (0x15h) Bits Field 0 DACR_ADCR The right DAC output is added to the ADC right input. Description 1 DACL_ADCL The left DAC output is added to the ADC left input. 2 MICR_ADCR The right MIC input is added to the ADC right input. Setting this bit enables MIC BIAS. 3 MICL_ADCL The left MIC input is added to the ADC left input. Setting this bit enables MIC BIAS.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com Table 25. MIC_R_INPUT (0x17h) 44 Bits Field 3:0 MIC_R_LEVEL 4 SE_DIFF 5 MUTE Description This sets the gain of the right microphone preamp. MIC_R_LEVEL Gain 0000 6dB 0001 8dB 0010 10dB 0011 12dB 0100 14dB 0101 16dB 0110 18dB 0111 20dB 1000 22dB 1001 24dB 1010 26dB 1011 28dB 1100 30dB 1101 32dB 1110 34dB 1111 36dB If set, the MIC_R negative input is ignored.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 Table 26. AUX_L_INPUT (0x18h) Bits Field 5:0 AUX_L_LEVEL 6 FROM_LINE_L Description This programs the left AUX input level. All gain changes are performed at zero crossings. AUX_L_LEVEL Level AUX_L_LEVEL Level 000000 –46.5dB 100000 1.5dB 000001 –45dB 100001 3dB 000010 –43.5dB 100010 4.5dB 000011 –42dB 100011 6dB 000100 –40.5dB 100100 7.5dB 000101 –39dB 100101 9dB 000110 –37.5dB 100110 10.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com Table 27. AUX_R_INPUT (0x19h) Bits 5:0 6 7 46 Field Description AUX_R_LEVEL This programs the right AUX input level. All gain changes are performed at zero crossings. AUX_R_LEVEL Level AUX_R_LEVEL Level 000000 –46.5dB 100000 1.5dB 000001 –45dB 100001 3dB 000010 –43.5dB 100010 4.5dB 000011 –42dB 100011 6dB 000100 –40.5dB 100100 7.5dB 000101 –39dB 100101 9dB 000110 –37.5dB 100110 10.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 ADC Control Registers This register is used to control the LM49350's ADC: Table 28. ADC Basic (0x20h) Bits Field 0 MONO Description This sets mono or stereo operation of the ADC. MONO 1 2 OSR ADC Operation 0 Stereo Audio 1 Mono Voice (Right ADC channel disabled, Left ADC channel active) This sets the oversampling ratio of the ADC.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com Table 30. ADC TRIM (0x22h) Bits Field Description 7:0 ADC_TRIM If set, the ADC is compensated with recommended compensation filter coefficients.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 Digital Mixer Control Registers DIGITAL MIXER The LM49350’s digital mixer allows for flexible routing of digital audio signals between both audio ports, DAC, and ADC. This mixer handles which digital data path (Port1 RX data, Port2 RX data, or ADC output) is routed to the DAC input.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com The LM49350 includes two separate and independent DSP blocks, one for the DAC and the other for the ADC. The digital mixer also allows both DSP blocks to be cascaded together in either order so that the DSP effects from both blocks can be combined into the same signal path. For example, the 5 band parametric EQ of each DSP block can be combined together to form a 10 band parametric EQ for added flexibility.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 Table 34. Input Levels 2 (0x41h) Bits Field 1:0 ADC_L_LVL Description This programs the input level of the data arriving from the left ADC channel. ADC_L_LVL 3:2 ADC_R_LVL Level 00 0dB 01 –6dB 10 –12dB 11 –18dB This programs the input level of the data arriving from the right ADC channel.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com Table 36. Audio Port 2 Input (0x43h) Bits Field 1:0 L_SEL Description This selects which input is fed to Audio Port 2's Left TX Channel. L_SEL 3:2 R_SEL Selected Input 00 None 01 ADC_L 10 PORT1_RX_L 11 DAC_INTERP_L This selects which input is fed to Audio Port 2's Right TX Channel.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 Table 38. Decimator Input Select (0x45h) (continued) Bits Field Description 5:4 MXR_CLK_SEL This selects sets the source of the Digital Mixer Clock. The 'Auto' setting will automatically select the source with the highest clock frequency. Whenever the DAC interpolator (DAC_OSR_L or DAC_OSR_R) is selected then MXR_CLK_SEL should be set to '10'.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com PCM_CLK PCM_SYNC PCM_SDO/ PCM_SDI 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 Short frame sync mode Long frame sync mode Figure 62. PCM Serial Data Format (16 bit example) The following registers are used to control the LM49350's audio ports. Audio Port 1 and Audio Port 2 are identical. Port 1 is programmed through the (0x5Xh) registers.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 Table 40. CLK_GEN_1 (0x51h/0x61h) Bits 5:0 6 Field Description HALF_CYCLE_CLK_DI This programs the half-cycle divider that generates the master clocks in the audio port. The input of V this divider should be around 12MHz. The default of this divider is 0x00, i.e. bypassed. Program this divider with the division you want, multiplied by 2, and subtract 1.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com Table 42. CLK_GEN_1 (0x53h/63h) Bits Field Description 2:0 SYNC_RATE This sets the number of clock cycles before the sync pattern repeats. This depends if the audio port data is mono or stereo.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 Table 43. DATA_WIDTHS (0x54h/64h) Bits Field 2:0 RX_WIDTH 5:3 7:6 TX_WIDTH TX_EXTRA_BITS Description This programs the expected bits per word of the serial data input SDI. RX_WIDTH Bits 000 24 001 20 010 18 011 16 100 14 101 13 110 12 111 8 This programs the bits per word of the serial data output SDO.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com Table 44. RX_MODE (0x55h/65h) Bits Field 0 RX_MODE 5:1 MSB_POSITION Description This sets the RX data input justification with respect to the SYNC signal. RX_MODE Description 0 MSB Justified 1 LSB Justified This specifies the bit location of the MSB from the start of the frame (MSB Justified) or from the end of the frame (LSB Justified).
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 Table 45. TX_MODE (0x56h/x66h) Bits Field 0 TX_MODE 5:1 MSB_POSITION Description This sets the TX data output justification with respect to the SYNC signal. TX_MODE Description 0 MSB Justified 1 LSB Justified This specifies the bit location of the MSB from the start of the frame (MSB Justified) or from the end of the frame (LSB Justified).
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com Digital Effects Engine DIGITAL SIGNAL PROCESSOR (DSP) The LM49350 is designed to handle the entire audio signal conditioning and processing within the audio system, thereby freeing up the workload of any other applications processor contained within the system. The LM49350 features two independent DSPs, one for the DAC and the other for the ADC.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 Table 47. DAC EFFECTS (0x71h) Bits Field 0 DAC_ALC_ENB Description This enables the DAC's Auto Level Control. 1 DAC_PK_ENB This enables the DAC's Peak Detector. 2 DAC_EQ_ENB This enables the DAC's 5-band Parametric EQ. 3 DAC_3D_ENB This enables the DAC's Stereo Widening Circuit. 4 ADC_SCLP_ENB This enables the DAC's Soft Clip Feature. Table 48.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com signal amplitude instantaneously, but tracks decreases in audio input signal amplitude at programmable rate (PEAK DECAY TIME). ATTACK RATE, DECAY RATE, HOLD TIME, and PEAK DECAY TIME are fully adjustable which allows flexible operation of the ALC circuit.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 Table 50. ADC_ALC_2 (0x82h) Bits Field Description 3:0 NOISE_FLOOR This sets the anticipated noise floor. Signals lower than the noise floor specified will be gated from the ALC to avoid noise pumping.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com Table 51. ADC_ALC_3 (0x83h) 64 Bits Field 4:0 TARGET_LEVEL Description This sets the desired target output level. Signals lower than this will be amplified and signals larger than this will be attenuated. Submit Documentation Feedback TARGET_LEVEL Target Level (dB) 00000 –1.5 00001 –3 00010 –4.5 00011 –6 00100 –7.5 00101 –9 00110 –10.5 00111 –12 01000 –13.5 01001 –15 01010 –16.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 Table 52. ADC_ALC_4 (0x84h) Bits Field 4:0 ATTACK_RATE Description This sets the rate at which the ALC will reduce gain if it detects the input signal is large.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com Table 53. ADC_ALC_5 (0x85h) Bits Field Description 4:0 DECAY_RATE This sets the rate at which the ALC will increase gain if it detects the input signal is too small.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 Table 54. ADC_ALC_6 (0x86h) Bits Field 4:0 HOLD_TIME Description This sets how long the ALC circuit waits before increasing the gain. HOLD_TIME Time (ms) 00000 1 00001 1.25 00010 1.6 00011 2 00100 2.5 00101 3.2 00110 4 00111 5 01000 6.25 01001 8 01010 10 01011 12.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com Table 57. ADC_L_LEVEL (0x89h) (Default data value is 0x33h) 68 Bits Field 5:0 ADC_L_LEVEL Submit Documentation Feedback Description This sets the post ADC digital gain of the left channel. ADC_L_LEVEL Level ADC_L_LEVEL Level 000000 -76.5dB 100000 -28.5dB 000001 -75dB 100001 -27dB 000010 -73.5dB 100010 -25.5dB 000011 -72dB 100011 -24dB 000100 -70.5dB 100100 -22.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 Table 58. ADC_R_LEVEL (0x8Ah) (Default data value is 0x33h) Bits Field 5:0 ADC_R_LEVEL Description This sets the post ADC digital gain of the right channel. ADC_R_LEVEL Level ADC_R_LEVEL Level 000000 -76.5dB 100000 -28.5dB 000001 -75dB 100001 -27dB 000010 -73.5dB 100010 -25.5dB 000011 -72dB 100011 -24dB 000100 -70.5dB 100100 -22.5dB 000101 -69dB 100101 -21dB 000110 -67.5dB 100110 -20.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com Table 59. EQ_BAND_1 (0x8Bh) Bits Field Description 1:0 FREQ This sets the Sub-bass shelving filter's cut-off frequency. The cut-off frequencies shown are based on a 48kHz sample rate. Using lower sample rates will scale down the cut-off frequencies proportionately. 6:2 70 LEVEL Submit Documentation Feedback FREQ Frequency (Hz) 00 60 01 80 10 100 11 120 This sets the gain at fc.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 Table 60. EQ_BAND_2 (0x8Ch) Bits Field 1:0 FREQ 6:2 7 LEVEL Q Description This sets the Bass peak filter's center frequency. The cut-off frequencies shown are based on a 48kHz sample rate. Using lower sample rates will scale down the cut-off frequencies proportionately. FREQ Frequency (Hz) 00 150 01 200 10 250 11 300 This sets the gain at fc.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com Table 61. EQ_BAND_3 (0x8Dh) Bits Field Description 1:0 FREQ This sets the Mid peak filter's center frequency. The cut-off frequencies shown are based on a 48kHz sample rate. Using lower sample rates will scale down the cut-off frequencies proportionately. 6:2 7 72 LEVEL Q Submit Documentation Feedback FREQ Frequency (Hz) 00 600 01 800 10 1k 11 1.2k This sets the gain at fC.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 Table 62. EQ_BAND_4 (0x8Eh) Bits Field Description 1:0 FREQ This sets the Treble peak filter's center frequency. The cut-off frequencies shown are based on a 48kHz sample rate. Using lower sample rates will scale down the cut-off frequencies proportionately. 6:2 7 LEVEL Q FREQ Frequency (Hz) 00 2k 01 2.7k 10 3.4k 11 4.1k This sets the gain at fC.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com Table 63. EQ_BAND_5 (0x8Fh) Bits Field Description 1:0 FREQ This sets the presence shelving filter's cut-off frequency. The cut-off frequencies shown are based on a 48kHz sample rate. Using lower sample rates will scale down the cut-off frequencies proportionately. 6:2 74 LEVEL Submit Documentation Feedback FREQ Frequency (Hz) 00 7k 01 9k 10 11k 11 20k This sets the gain at fC.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 Table 64. SOFTCLIP1 (0x90h) Bits Field 3:0 THRESHOLD 4 SOFT_KNEE Description This sets the threshold level of the audio compressor. Audio signals above the threshold will be compressed. THRESHOLD Threshold Level (dB) 0000 -36dB 0001 -30dB 0010 -24dB 0011 -20dB 0100 -18dB 0101 -17dB 0110 -16dB 0111 -15dB 1000 -14dB 1001 -12dB 1010 -10dB 1011 -8dB 1100 -6dB 1101 -4dB 1110 -2.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com Table 65. SOFTCLIP2 (0x91h) 76 Bits Field 4:0 RATIO Submit Documentation Feedback Description This sets the ratio at which the audio is compressed to when it passes beyond the threshold. In SOFT_KNEE mode this is the final level of compression. RATIO Ratio 00000 1:1 (Bypass) 00001 1:1.2 00010 1:1.4 00011 1:1.7 00100 1:2.0 00101 1:2.4 00110 1:2.8 00111 1:3.4 01000 1:4.0 01001 1:4.7 01010 1:5.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 Table 66. SOFTCLIP3 (0x92h) Bits Field 4:0 LEVEL Description This sets the post compressor gain level. LEVEL Level (dB) 00000 -22.5dB 00001 -21dB 00010 -19.5dB 00011 -18dB 00100 -16.5dB 00101 -15dB 00110 -13.5dB 00111 -12dB 01000 -10.5dB 01001 -9dB 01010 -7.5dB 01011 -6dB 01100 -4.5dB 01101 -3dB 01110 -1.5dB 01111 0dB 10000 1.5dB 10001 3dB 10010 4.5dB 10011 6dB 10100 7.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com DAC Effects Registers Table 67. DAC_ALC_1 (0xA0h) Bits Field 2:0 SAMPLE_ RATE Description This programs the timers on the ALC with the closest DAC sample rate.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 Table 69. DAC_ALC_3 (0xA2h) Bits Field 4:0 TARGET_LEVEL Description This sets the desired output level. Signals lower than this will be amplified and signals larger than this will be attenuated. TARGET_LEVEL Target Level (dB) 00000 -1.5 00001 -3 00010 -4.5 00011 -6 00100 -7.5 00101 -9 00110 -10.5 00111 -12 01000 -13.5 01001 -15 01010 -16.5 01011 -18 01100 -19.5 01101 -21 01110 -22.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com Table 70. DAC_ALC_4 (0xA3h) 80 Bits Field Description 4:0 ATTACK_RATE This sets the rate at which the ALC will reduce gain if it detects the input signal is too large.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 Table 71. DAC_ALC_5 (0xA4h) Bits Field 4:0 DECAY_RATE 7:5 PK_DECAY_RATE Description This sets the rate at which the ALC will increase gain if it detects the input signal is too small.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com Table 72. DAC_ALC_6 (0xA5h) Bits Field 4:0 HOLD_TIME Description This sets how long the ALC circuit waits before increasing the gain. HOLDTIME Time (ms) 00000 1 00001 1.25 00010 1.6 00011 2 00100 2.5 00101 3.2 00110 4 00111 5 01000 6.25 01001 8 01010 10 01011 12.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 Table 75. DAC_L_LEVEL (0xA8h) (Default data value is 0x33h) Bits Field 5:0 DAC_L_LEVEL Description This sets the pre DAC digital gain. DAC_L_LEVEL Level DAC_L_LEVEL Level 000000 -76.5dB 100000 -28.5dB 000001 -75dB 100001 -27dB 000010 -73.5dB 100010 -25.5dB 000011 -72dB 100011 -24dB 000100 -70.5dB 100100 -22.5dB 000101 -69dB 100101 -21dB 000110 -67.5dB 100110 -20.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com Table 76. DAC_R_LEVEL (0xA9h) (Default data value is 0x33h) 84 Bits Field 5:0 DAC_R_LEVEL Submit Documentation Feedback Description This sets the pre DAC digital gain. DAC_R_LEVEL Level DAC_R_LEVEL Level 000000 -76.5dB 100000 -28.5dB 000001 -75dB 100001 -27dB 000010 -73.5dB 100010 -25.5dB 000011 -72dB 100011 -24dB 000100 -70.5dB 100100 -22.5dB 000101 -69dB 100101 -21dB 000110 -67.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 Table 77. DAC_3D (0xAAh) Bits Field 0 EFFECT_MODE Description This sets the digital 3D stereo enhancement mode. EFFECT_MODE 2:1 EFFECT_LEVEL Loudspeaker 1 Headphone This sets the applied level of 3D effect. EFFECT_LEVEL 6:3 7 FILTER_TYPE ATTENUATE Type 0 Level 00 25% 01 37.50% 10 50% 11 75% This sets the 3D effect filter response.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com Table 78. EQ_BAND_1 (0xABh) Bits Field 1:0 FREQ 6:2 86 LEVEL Submit Documentation Feedback Description This sets the Sub-bass shelving filter's cut-off frequency. The cut-off frequencies shown are based on a 48kHz sample rate. Using lower sample rates will scale down the cut-off frequencies proportionately. FREQ Frequency (Hz) 00 60 01 80 10 100 11 120 This sets the gain at fC.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 Table 79. EQ_BAND_2 (0xACh) Bits Field 1:0 FREQ 6:2 7 LEVEL Q Description This sets the Bass peak filter's center frequency. The cut-off frequencies shown are based on a 48kHz sample rate. Using lower sample rates will scale down the cut-off frequencies proportionately. FREQ Frequency (Hz) 00 150 01 200 10 250 11 300 This sets the gain at fC.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com Table 80. EQ_BAND_3 (0xADh) Bits Field 1:0 FREQ 6:2 7 88 LEVEL Q Submit Documentation Feedback Description This sets the Mid peak filter's center frequency. The cut-off frequencies shown are based on a 48kHz sample rate. Using lower sample rates will scale down the cut-off frequencies proportionately. FREQ Frequency (Hz) 00 600 01 800 10 1k 11 1.2k This sets the gain at fC.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 Table 81. EQ_BAND_4 (0xAEh) Bits Field Description 1:0 FREQ This sets the Treble peak filter's center frequency. The cut-off frequencies shown are based on a 48kHz sample rate. Using lower sample rates will scale down the cut-off frequencies proportionately. 6:2 7 LEVEL Q FREQ Frequency (Hz) 00 2k 01 2.7k 10 3.4k 11 4.1k This sets the gain at fC.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com Table 82. EQ_BAND_5 (0xAFh) Bits Field Description 1:0 FREQ This sets the presence shelving filter's cut-off frequency. The cut-off frequencies shown are based on a 48kHz sample rate. Using lower sample rates will scale down the cut-off frequencies proportionately. 6:2 90 LEVEL Submit Documentation Feedback FREQ Frequency (Hz) 00 7k 01 9k 10 11k 11 20k This sets the gain at fC.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 Table 83. SOFTCLIP1 (0xB0h) Bits Field 3:0 TRESHOLD 4 SOFT_KNEE Description This sets the threshold level of the audio compressor. Audio signals above the threshold will be compressed. THRESHOLD Threshold Level (dB) 0000 -36dB 0001 -30dB 0010 -24dB 0011 -20dB 0100 -18dB 0101 -17dB 0110 -16dB 0111 -15dB 1000 -14dB 1001 -12dB 1010 -10dB 1011 -8dB 1100 -6dB 1101 -4dB 1110 -2.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com Table 84. SOFTCLIP2 (0xB1h) 92 Bits Field 4:0 RATIO Submit Documentation Feedback Description This sets the ratio at which the audio is compressed to when it passes beyond the threshold. In soft clip mode this is the final level of compression. RATIO Ratio 00000 1:1 (Bypass) 00001 1:1.2 00010 1:1.4 00011 1:1.7 00100 1:2.0 00101 1:2.4 00110 1:2.8 00111 1:3.4 01000 1:4.0 01001 1:4.7 01010 1:5.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 Table 85. SOFTCLIP3 (0xB2h) Table 40: Bits Field 4:0 LEVEL Description This sets the post compressor gain level. LEVEL Level (dB) 00000 -22.5dB 00001 -21dB 00010 -19.5dB 00011 -18dB 00100 -16.5dB 00101 -15dB 00110 -13.5dB 00111 -12dB 01000 -10.5dB 01001 -9dB 01010 -7.5dB 01011 -6dB 01100 -4.5dB 01101 -3dB 01110 -1.5dB 01111 0dB 10000 1.5dB 10001 3dB 10010 4.5dB 10011 6dB 10100 7.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com GPIO Registers Table 86. GPIO (0xE0h) Bits Field 3:0 GPIO_MODE 4 Description This sets the mode of the GPIO pin.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 Table 88. Spread Spectrum (0xF1h) Bits Field 1:0 RSVD Description 2 SS_DISABLE Reserved If this bit is set, Spread Spectrum mode will be disabled from the Class D amplifier. Table 89. ADC Compensation Filter C0 LSBs (0xF8h) Bits Field 7:0 ADC_CO_LSB Description Bits Field 7:0 ADC_CO_MSB Bits 7:0 of C0[15:0] Table 90. ADC Compensation Filter C0 MSBs (0xF9h) Description Bits 15:0 of C0[15:0] Table 91.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com Schematic Diagram Figure 66.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 Demonstration Board Layout Figure 67. Top Silkscreen Layer Figure 68.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com Figure 69. Inner Layer 1 Figure 70.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 Figure 71. Bottom Silkscreen Layer Figure 72.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com APPLICATION NOTE FOR LM49350 POWER CONNECTIONS Recommended target application circuit must provide same voltage level for A_VDD and LSVDD to get performance on Electrical Specifications on LM49350 datasheet. VDD D_VDD I/O_VDD A_VDD LS_VDD LEFT_MIC+ HP_VSS LEFT_MICVREF 0.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 MICROPHONE BIAS CONFIGURATIONS Schematic Considerations for MEMs Microphones The internal microphone bias of the LM49350 is provided through a two stage amplifier. Adding a capacitor larger than 100pF directly to this pin can cause instability. In many cases, when using MEMs microphones, a larger bypass capacitor is required on the MIC_BIAS pin.
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LM49350, LM49350RLEVAL SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 www.ti.com PCB LAYOUT CONSIDERATIONS Microphone Inputs When routing the differential microphone inputs the electrical length of the two traces should be well matched. The differential input pair can be routed in parallel on the same plane or the traces can overlap on two adjacent planes.
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LM49350, LM49350RLEVAL www.ti.com SNAS359D – SEPTEMBER 2008 – REVISED JUNE 2012 REVISION HISTORY Rev Date 1.0 09/03/08 Description Initial released. 1.01 09/04/08 Text edits. 1.02 09/22/08 Text edits. 1.03 10/24/08 Text edits. 1.04 12/15/08 Text edits and replaced the top silkscreen layer. 1.05 05/27/09 Added the EMI/RFI section and the corresponding graphic. 1.06 05/29/09 Text edits. 1.07 04/09/10 Text edits. 1.08 04/15/10 Text edits. 1.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LM49350RL/NOPB DSBGA YPG 36 250 178.0 12.4 LM49350RLX/NOPB DSBGA YPG 36 1000 178.0 12.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.63 3.63 0.76 8.0 12.0 Q1 3.63 3.63 0.76 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM49350RL/NOPB DSBGA YPG LM49350RLX/NOPB DSBGA YPG 36 250 210.0 185.0 35.0 36 1000 210.0 185.0 35.
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MECHANICAL DATA YPG0036xxx D 0.650±0.075 E RLA36XXX (Rev A) D: Max = 3.49 mm, Min = 3.43 mm E: Max = 3.49 mm, Min = 3.43 mm 4214895/A NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. This drawing is subject to change without notice. www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.