Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - voltage regulators - DC DC switch controllers VSSOP 10

VIN

FBCOMP

VCC

OUT

UVLO GND

LM5022

C2R1

UV1

UV2

FB1

FB2

SNS

LM5022

www.ti.com

SNVS480G –JANUARY 2007–REVISED DECEMBER 2013

LM5022 60V Low Side Controller for Boost and SEPIC

Check for Samples: LM5022

FEATURES

DESCRIPTION

The LM5022 is a high voltage low-side N-channel

• Internal 60V Startup Regulator

MOSFET controller ideal for use in boost and SEPIC

• 1A Peak MOSFET Gate Driver

regulators. It contains all of the features needed to

• V

Range 6V to 60V

implement single ended primary topologies. Output

voltage regulation is based on current-mode control,

• Duty Cycle Limit of 90%

which eases the design of loop compensation while

• Programmable UVLO with Hysteresis

providing inherent input voltage feed-forward. The

• Cycle-by-Cycle Current Limit

LM5022 includes a start-up regulator that operates

over a wide input range of 6V to 60V. The PWM

• External Synchronizable (AC-coupled)

controller is designed for high speed capability

• Single Resistor Oscillator Frequency Set

including an oscillator frequency range up to 2 MHz

• Slope Compensation

and total propagation delays less than 100 ns.

Additional features include an error amplifier,

• Adjustable Soft-start

precision reference, line under-voltage lockout, cycle-

• VSSOP-10 Package

by-cycle current limit, slope compensation, soft-start,

external synchronization capability and thermal

APPLICATIONS

shutdown. The LM5022 is available in the VSSOP-10

• Boost Converter package.

• SEPIC Converter

Typical Application

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (34 pages)

PAGE 1
LM5022 www.ti.com SNVS480G – JANUARY 2007 – REVISED DECEMBER 2013 LM5022 60V Low Side Controller for Boost and SEPIC Check for Samples: LM5022 FEATURES DESCRIPTION • • • • • • • • • • • The LM5022 is a high voltage low-side N-channel MOSFET controller ideal for use in boost and SEPIC regulators. It contains all of the features needed to implement single ended primary topologies.
PAGE 2
LM5022 SNVS480G – JANUARY 2007 – REVISED DECEMBER 2013 www.ti.com Connection Diagram 1 2 3 4 5 VIN SS FB RT COMP CS VCC UVLO OUT GND 10 9 8 7 6 Figure 1. 10-Lead VSSOP Package See Package Number DGS0010A PIN DESCRIPTIONS Pins Name Description 1 VIN Source input voltage Input to the start-up regulator. Operates from 6V to 60V. 2 FB Feedback pin Inverting input to the internal voltage error amplifier. The noninverting input of the error amplifier connects to a 1.25V reference.
PAGE 3
LM5022 www.ti.com SNVS480G – JANUARY 2007 – REVISED DECEMBER 2013 Absolute Maximum Ratings (1) (2) VIN to GND -0.3V to 65V VCC to GND -0.3V to 16V RT/SYNC to GND -0.3V to 5.5V OUT to GND -1.5V for < 100 ns All other pins to GND -0.3V to 7V Power Dissipation Internally Limited Junction Temperature 150°C Storage Temperature -65°C to +150°C Soldering Information Vapor Phase (60 sec.) 215°C Infrared (15 sec.
PAGE 4
LM5022 SNVS480G – JANUARY 2007 – REVISED DECEMBER 2013 Electrical Characteristics www.ti.com (1) Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. VIN = 24V and RT = 27.4 kΩ unless otherwise indicated.
PAGE 5
LM5022 www.ti.com SNVS480G – JANUARY 2007 – REVISED DECEMBER 2013 Electrical Characteristics (1) (continued) Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only. VIN = 24V and RT = 27.4 kΩ unless otherwise indicated.
PAGE 6
LM5022 SNVS480G – JANUARY 2007 – REVISED DECEMBER 2013 www.ti.com Typical Performance Characteristics 6 Efficiency, VO = 40V, Example Circuit BOM VFB vs. Temp (VIN = 24V) Figure 2. Figure 3. VFB vs. VIN (TA = 25°C) VCC vs. VIN (TA = 25°C) Figure 4. Figure 5. Max Duty Cycle vs. fSW (TA = 25°C) fSW vs. Temperature (RT = 16.2 kΩ) Figure 6. Figure 7.
PAGE 7
LM5022 www.ti.com SNVS480G – JANUARY 2007 – REVISED DECEMBER 2013 Typical Performance Characteristics (continued) RT vs. fSW (TA = 25°C) SS vs. Temperature Figure 8. Figure 9. OUT Pin tRISE vs. Gate Capacitance OUT Pin tFALL vs. Gate Capacitance Figure 10. Figure 11.
PAGE 8
LM5022 SNVS480G – JANUARY 2007 – REVISED DECEMBER 2013 www.ti.com Block Diagram BYPASS SWITCH (6V to 8.7V) VCC VIN 7V SERIES REGULATOR REFERENCE ENABLE + - UVLO 5V 1.25V LOGIC 1.25V UVLO HYSTERESIS CLK (20 PA) RT/SYNC OSC DRIVER 45 PA Max Duty Limit 0 S Q R Q OUT 5V COMP GND 5k 1.25V PWM 100 k: FB + - LOGIC 1.4V 50 k: SS CS 0.
PAGE 9
LM5022 www.ti.com SNVS480G – JANUARY 2007 – REVISED DECEMBER 2013 Example Circuit VIN = 9V to 16V CIN1,2 L1 VO = 40V D1 CINX Q1 CO1,2 RS1 VIN OUT RT CS RT RS2 UVLO CSS RUV1 LM5022 RUV2 COX SS RSNS CCS GND CF VCC COMP RFB2 FB R1 C2 RFB1 C1 Figure 12. Design Example Schematic APPLICATIONS INFORMATION OVERVIEW The LM5022 is a low-side N-channel MOSFET controller that contains all of the features needed to implement single ended power converter topologies.
PAGE 10
LM5022 SNVS480G – JANUARY 2007 – REVISED DECEMBER 2013 www.ti.com INPUT UNDER-VOLTAGE DETECTOR The LM5022 contains an input Under Voltage Lock Out (UVLO) circuit. UVLO is programmed by connecting the UVLO pin to the center point of an external voltage divider from VIN to GND. The resistor divider must be designed such that the voltage at the UVLO pin is greater than 1.25V when VIN is in the desired operating range.
PAGE 11
LM5022 www.ti.com SNVS480G – JANUARY 2007 – REVISED DECEMBER 2013 The LM5022 current sense and PWM comparators are very fast, and may respond to short duration noise pulses. Layout considerations are critical for the current sense filter and sense resistor. The capacitor associated with the CS filter must be located very close to the device and connected directly to the pins of the controller (CS and GND).
PAGE 12
LM5022 SNVS480G – JANUARY 2007 – REVISED DECEMBER 2013 www.ti.com PWM COMPARATOR AND SLOPE COMPENSATION The PWM comparator compares the current ramp signal with the error voltage derived from the error amplifier output. The error amplifier output voltage at the COMP pin is offset by 1.4V and then further attenuated by a 3:1 resistor divider. The PWM comparator polarity is such that 0V on the COMP pin will result in a zero duty cycle at the controller output.
PAGE 13
LM5022 www.ti.com D= SNVS480G – JANUARY 2007 – REVISED DECEMBER 2013 VO - VIN + VD VO + VD where • VD is the forward voltage drop of the output diode (2) The following is a design procedure for selecting all the components for the boost converter circuit shown in Figure 12. The application is "in-cabin" automotive, meaning that the operating ambient temperature ranges from -20°C to 85°C.
PAGE 14
LM5022 SNVS480G – JANUARY 2007 – REVISED DECEMBER 2013 www.ti.com Switching loss, PSW, occurs during the brief transition period as the MOSFET turns on and off. During the transition period both current and voltage are present in the channel of the MOSFET. The loss can be approximated as: PSW = 0.
PAGE 15
LM5022 www.ti.com L2 = SNVS480G – JANUARY 2007 – REVISED DECEMBER 2013 D(1-D) x VIN IO x fSW (9) By calculating in terms of volts, amps and megahertz the inductance value will come out in µH. For this design ΔiL will be set to 40% of the maximum IL. Duty cycle is evaluated first at VIN(MIN) and at VIN(MAX). Second, the average inductor current is evaluated at the two input voltages. Third, the inductor ripple current is determined.
PAGE 16
LM5022 SNVS480G – JANUARY 2007 – REVISED DECEMBER 2013 www.ti.com Hence an inductor must be selected that has a peak current rating greater than 2.5A and an average current rating greater than 2.3A. One possibility is an off-the-shelf 33 µH ±20% inductor that can handle a peak current of 3.2A and an average current of 3.4A. Finally, the inductor current ripple is recalculated at the maximum input voltage: ΔiL-VIN(MAX) = (16 x 0.6) / (0.5 x 33) = 0.
PAGE 17
LM5022 www.ti.com SNVS480G – JANUARY 2007 – REVISED DECEMBER 2013 ÂvO VO ID Figure 17. ΔVO Using Low ESR Capacitors For this example the small size and high temperature rating of ceramic capacitors make them a good choice. The output ripple voltage waveform of Figure 17 is assumed, and the capacitance will be selected first. The desired ΔVO is ±2% of 40V, or 0.8VP-P. Beginning with the calculation for ΔVO2, the required minimum capacitance is: CO-MIN = (IO / ΔVO) x (DMAX / fSW) CO-MIN = (0.5 / 0.
PAGE 18
LM5022 SNVS480G – JANUARY 2007 – REVISED DECEMBER 2013 www.ti.com INPUT CAPACITOR The input capacitors to a boost regulator control the input voltage ripple, ΔVIN, hold up the input voltage during load transients, and prevent impedance mismatch (also called power supply interaction) between the LM5022 and the inductance of the input leads. Selection of input capacitors is based on their capacitance, ESR, and RMS current rating.
PAGE 19
LM5022 www.ti.com SNVS480G – JANUARY 2007 – REVISED DECEMBER 2013 RSNS, RS2 AND CURRENT LIMIT The current sensing resistor RSNS is used for steady state regulation of the inductor current and to sense overcurrent conditions. The slope compensation resistor is used to ensure control loop stability, and both resistors affect the current limit threshold.
PAGE 20
LM5022 SNVS480G – JANUARY 2007 – REVISED DECEMBER 2013 www.ti.com L + C O D VIN + - RO RSNS RC + RFB2 R1 C2 C1 + VREF RFB1 + - Figure 18. Power Stage and Error Amplifier One popular method for selecting the compensation components is to create Bode plots of gain and phase for the power stage and error amplifier. Combined, they make the overall bandwidth and phase margin of the regulator easy to determine.
PAGE 21
LM5022 www.ti.com SNVS480G – JANUARY 2007 – REVISED DECEMBER 2013 RO x ZRHP = VIN 2 VO L (47) The sampling double pole quality factor is: 1 Qn = S -D + 0.5 + (1 - D) Se Sn (48) The sampling double corner frequency is: ωn = π x fSW (49) The natural inductor current slope is: Sn = RSNS x VIN / L (50) The external ramp slope is: Se = 45 µA x (2000 + RS1 + RS2)] x fSW (51) In the equation for APS, DC gain is highest when input voltage and output current are at the maximum.
PAGE 22
LM5022 SNVS480G – JANUARY 2007 – REVISED DECEMBER 2013 www.ti.com POWER STAGE PHASE (°) 180 120 60 0 -60 -120 -180 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 20. Power Stage Gain and Phase The single pole causes a roll-off in the gain of -20 dB/decade at lower frequency. The combination of the RHP zero and sampling double pole maintain the slope out to beyond the switching frequency.
PAGE 23
LM5022 www.ti.com C2 = SNVS480G – JANUARY 2007 – REVISED DECEMBER 2013 1 : 2S x R1 x fZ1 For this example, C2 = 125 nF 8. Select a frequency for the compensation pole, fP1: The suggested placement for this pole is at one-fifth of the switching frequency. For this example, fP1 = 100 kHz 9. Set C1 = C2 : 2S x C2 x R1 x fP1 -1 For this example, C1 = 530 pF 10.
PAGE 24
LM5022 www.ti.com 60 180 40 120 OVERALL LOOP PHASE (°) OVERALL LOOP GAIN (dB) SNVS480G – JANUARY 2007 – REVISED DECEMBER 2013 20 0 -20 -40 -60 100 1k 10k 100k 1M 60 0 -60 -120 -180 100 FREQUENCY (Hz) 1k 10k 100k 1M FREQUENCY (Hz) Figure 23. Overall Loop Gain and Phase Figure 24. Overall Loop Gain and Phase The bandwidth of this example circuit at VIN = 16V is 10.5 kHz, with a phase margin of 66°. 13.
PAGE 25
LM5022 www.ti.com SNVS480G – JANUARY 2007 – REVISED DECEMBER 2013 INPUT CAPACITOR LOSS This term represents the loss as input ripple current passes through the ESR of the input capacitor bank. In this equation ‘n’ is the number of capacitors in parallel. The 4.7 µF input capacitors selected have a combined ESR of approximately 1.5 mΩ, and ΔiL for a 13.8V input is 0.55A: PCIN = IIN-RMS2 x ESR n IIN-RMS = 0.29 x ΔiL = 0.29 x 0.55 = 0.16A PCIN = [0.162 x 0.0015] / 2 = 0.
PAGE 26
LM5022 SNVS480G – JANUARY 2007 – REVISED DECEMBER 2013 www.ti.com + - Figure 25. Boost Converter Current Loops The dark grey, inner loops represents the high current paths during the MOSFET on-time. The light grey, outer loop represents the high current path during the off-time.
PAGE 27
LM5022 www.ti.com SNVS480G – JANUARY 2007 – REVISED DECEMBER 2013 GROUND PLANE AND SHAPE ROUTING The diagram of Figure 25 is also useful for analyzing the flow of continuous current vs. the flow of pulsating currents. The circuit paths with current flow during both the on-time and off-time are considered to be continuous current, while those that carry current during the on-time or off-time only are pulsating currents.
PAGE 28
LM5022 SNVS480G – JANUARY 2007 – REVISED DECEMBER 2013 www.ti.com REVISION HISTORY Changes from Revision E (March 2013) to Revision F • Changed layout of National Data Sheet to TI format .......................................................................................................... 27 Changes from Revision F (March 2013) to Revision G • 28 Page Page Changed timing resistor equation. Incorrect change when converting to TI format ...........................................................
PAGE 29
PACKAGE OPTION ADDENDUM www.ti.
PAGE 30
PACKAGE OPTION ADDENDUM www.ti.com 6-Dec-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
PAGE 31
PACKAGE MATERIALS INFORMATION www.ti.com 6-Dec-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM5022MM VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5022MM/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5022MME/NOPB VSSOP DGS 10 250 178.0 12.4 5.3 3.4 1.4 8.0 12.
PAGE 32
PACKAGE MATERIALS INFORMATION www.ti.com 6-Dec-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5022MM VSSOP DGS 10 1000 210.0 185.0 35.0 LM5022MM/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0 LM5022MME/NOPB VSSOP DGS 10 250 210.0 185.0 35.0 LM5022MMX/NOPB VSSOP DGS 10 3500 367.0 367.0 35.
PAGE 33
PAGE 34
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.