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LM5025A

www.ti.com

SNVS293E –DECEMBER 2004–REVISED MARCH 2013

Active Clamp Voltage Mode PWM Controller

Check for Samples: LM5025A

FEATURES

DESCRIPTION

The LM5025A is a functional variant of the LM5025

• Internal Start-up Bias Regulator

active clamp PWM controller. The functional

• 3A Compound Main Gate Driver

differences of the LM5025A are: The CS1 and CS2

• Programmable Line Under-Voltage Lockout

current limit thresholds have been increased to 0.5V.

(UVLO) with Adjustable Hysteresis

The internal CS2 filter discharge device has been

disabled and no longer operates each clock cycle.

• Voltage Mode Control with Feed-Forward

The internal V

and V

REF

regulators continue to

• Adjustable Dual Mode Over-Current Protection

operate when the line UVLO pin is below threshold.

• Programmable Overlap or Deadtime between

The LM5025A PWM controller contains all of the

the Main and Active Clamp Outputs

features necessary to implement power converters

• Volt x Second Clamp

utilizing the Active Clamp / Reset technique. With the

active clamp technique, higher efficiencies and

• Programmable Soft-start

greater power densities can be realized compared to

• Leading Edge Blanking

conventional catch winding or RDC clamp / reset

• Single Resistor Programmable Oscillator

techniques. Two control outputs are provided, the

• Oscillator UP / DOWN Sync Capability

main power switch control (OUT_A) and the active

clamp switch control (OUT_B). The two internal

• Precision 5V Reference

compound gate drivers parallel both MOS and Bipolar

• Thermal Shutdown

devices, providing superior gate drive characteristics.

This controller is designed for high-speed operation

PACKAGES

including an oscillator frequency range up to 1MHz

and total PWM and current sense propagation delays

• TSSOP-16

less than 100ns. The LM5025A includes a high-

• WSON-16 (5x5 mm) Thermally Enhanced

voltage start-up regulator that operates over a wide

input range of 13V to 90V. Additional features

include: Line Under Voltage Lockout (UVLO),

softstart, oscillator UP/DOWN sync capability,

precision reference and thermal shutdown.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (22 pages)

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LM5025A www.ti.com SNVS293E – DECEMBER 2004 – REVISED MARCH 2013 Active Clamp Voltage Mode PWM Controller Check for Samples: LM5025A FEATURES DESCRIPTION • • • The LM5025A is a functional variant of the LM5025 active clamp PWM controller. The functional differences of the LM5025A are: The CS1 and CS2 current limit thresholds have been increased to 0.5V. The internal CS2 filter discharge device has been disabled and no longer operates each clock cycle.
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LM5025A SNVS293E – DECEMBER 2004 – REVISED MARCH 2013 www.ti.com Typical Application Circuit VOUT 3.3V VIN 35 - 78V LM5025A ERROR AMP & ISOLATION CS1 VIN VCC UVLO OUT_A OUT_B RAMP COMP REF CS2 SYNC Rt TIME SS PGND AGND UP/DOWN SYNC Figure 1. Simplified Active Clamp Forward Power Converter Connection Diagram VIN 1 16 UVLO RAMP 2 15 SYNC CS1 3 14 RT CS2 4 13 COMP TIME 5 12 SS REF 6 11 AGND VCC 7 10 PGND OUT_A 8 9 OUT_B Figure 2. 16-Lead TSSOP, WSON Table 1.
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LM5025A www.ti.com SNVS293E – DECEMBER 2004 – REVISED MARCH 2013 Table 1. PIN DESCRIPTION (continued) Pin Name 3 CS1 Current sense input for cycle-bycycle limiting Description If CS1 exceeds 0.5V the outputs will go into Cycle-by-Cycle current limit. CS1 is held low for 50ns after OUT_A switches high providing leading edge blanking. Application Information 4 CS2 Current sense input for soft restart If CS2 exceeds 0.5V the outputs will be disabled and a softstart commenced.
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LM5025A SNVS293E – DECEMBER 2004 – REVISED MARCH 2013 www.ti.com Block Diagram 7.6V SERIES REGULATOR VCC VIN 5V REFERENCE VCC REF UVLO UVLO + - LOGIC 2.5V ENABLE OUTPUTS UVLO HYSTERESIS (20 PA) VCC OUT_A CLK RT DRIVER OSCILLATOR SYNC SLOPE D TO VIN DEADTIME OR OVERLAP CONTROL FF RAMP RAMP TIME VCC 5V 5k + - COMP OUT_B PWM 1V SS Amp (Sink Only) LOGIC SS S Q R Q DRIVER + - 2.5V MAX V*S CLAMP CS1 PGND + - 0.5V CS2 0.5V + AGND CLK + LEB SS 20 PA SS 19 PA Figure 3.
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LM5025A www.ti.com SNVS293E – DECEMBER 2004 – REVISED MARCH 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) VIN to GND -0.3V to 105V VCC to GND -0.3V to 16V CS1, CS2 to GND -0.3 to 1.00V All other inputs to GND -0.
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LM5025A SNVS293E – DECEMBER 2004 – REVISED MARCH 2013 www.ti.com Electrical Characteristics (continued) Specifications with standard typeface are for TJ = 25°C, and those with boldface type apply over full Operating Junction Temperature range. VIN = 48V, VCC = 10V, RT = 31.3kΩ, RSET = 27.4kΩ) unless otherwise stated (1) Symbol Parameter Cycle Skip Threshold Voltage (CS2) Conditions Resets SS capacitor; auto restart Min Typ Max Unit 0.45 0.5 0.
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LM5025A www.ti.com SNVS293E – DECEMBER 2004 – REVISED MARCH 2013 Electrical Characteristics (continued) Specifications with standard typeface are for TJ = 25°C, and those with boldface type apply over full Operating Junction Temperature range. VIN = 48V, VCC = 10V, RT = 31.3kΩ, RSET = 27.4kΩ) unless otherwise stated (1) Symbol Parameter Conditions Min Typ Max Unit Output Timing Control Overlap Time RSET = 38 kΩ connected to GND, 50% to 50% transitions 75 105 135 ns Deadtime RSET = 29.
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LM5025A SNVS293E – DECEMBER 2004 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics VCC Regulator Start-up Characteristics, VCC vs Vin VCC vs ICC 16 10 VIN 14 8 12 6 VCC (V) VCC (V) 10 VCC 8 4 6 4 2 2 0 0 0 2 4 6 8 10 12 14 16 0 5 10 15 20 VIN (V) ICC (mA) Figure 4. Figure 5. VREF vs IREF Oscillator Frequency vs RT 25 6 5 VREF (V) 4 3 2 1 0 0 5 10 15 20 25 IREF (mA) Figure 6. Figure 7.
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LM5025A www.ti.com SNVS293E – DECEMBER 2004 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Dead Time vs Temperature RSET = 29.5K Dead Time vs RSET 140 400 350 130 DEADTIME (ns) DEADTIME (ns) 300 250 200 150 120 110 100 100 90 50 0 0 20 40 60 80 100 80 -40 120 RSET (k:) 25 75 125 o TEMPERATURE ( C) Figure 10. Figure 11. SS Pin Current vs Temperature 26 SS CURRENT (PA) 24 22 20 18 16 14 -40 25 75 125 o TEMPERATURE ( C) Figure 12.
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LM5025A SNVS293E – DECEMBER 2004 – REVISED MARCH 2013 www.ti.com DETAILED OPERATING DESCRIPTION The LM5025A is a functional variant of the LM5025 active clamp PWM controller. The functional differences of the LM5025A are: • The CS1 and CS2 current limit thresholds have been increased to 0.5V. • The internal CS2 filter discharge device has been disabled and no longer operates each clock cycle. • The internal VCC and VREF regulators continue to operate when the line UVLO pin is below threshold.
PAGE 11
LM5025A www.ti.com SNVS293E – DECEMBER 2004 – REVISED MARCH 2013 LM5025A is the ability to accurately configure either dead time (both off) or overlap time (both on) of the gate driver outputs. The overlap / deadtime magnitude is controlled by the resistor value connected to the TIME pin of the controller. The opposite end of the resistor can be connected to either REF for deadtime control or GND for overlap control.
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LM5025A SNVS293E – DECEMBER 2004 – REVISED MARCH 2013 www.ti.com PWM Comparator The PWM comparator compares the ramp signal (RAMP) to the loop error signal (COMP). This comparator is optimized for speed in order to achieve minimum controllable duty cycles. The internal 5kΩ pull-up resistor, connected between the internal 5V reference and COMP, can be used as the pull-up for an optocoupler. The comparator polarity is such that 0V on the COMP pin will produce a zero duty cycle on both gate driver outputs.
PAGE 13
LM5025A www.ti.com SNVS293E – DECEMBER 2004 – REVISED MARCH 2013 A small RC filter, located near the controller, is recommended for each of the CS pins. The CS1 input has an internal FET which discharges the current sense filter capacitor at the conclusion of every cycle, to improve dynamic performance. This same FET remains on an additional 50ns at the start of each main switch cycle to attenuate the leading edge spike in the current sense signal.
PAGE 14
LM5025A SNVS293E – DECEMBER 2004 – REVISED MARCH 2013 www.ti.com Soft-Start The softstart feature allows the power converter to gradually reach the initial steady state operating point, thus reducing start-up stresses and surges. At power on, a 20µA current is sourced out of the softstart pin (SS) into an external capacitor. The capacitor voltage will ramp up slowly and will limit the COMP pin voltage and therefore the PWM duty cycle.
PAGE 15
LM5025A www.ti.com SNVS293E – DECEMBER 2004 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision D (March 2013) to Revision E • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 7-Oct-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM5025AMTCX/NOPB TSSOP PW 16 2500 330.0 12.4 6.95 8.3 1.6 8.0 12.0 Q1 LM5025ASD/NOPB WSON NHQ 16 1000 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 LM5025ASDX/NOPB WSON NHQ 16 4500 330.0 12.4 5.3 5.3 1.3 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5025AMTCX/NOPB LM5025ASD/NOPB TSSOP PW 16 2500 367.0 367.0 35.0 WSON NHQ 16 1000 210.0 185.0 35.0 LM5025ASDX/NOPB WSON NHQ 16 4500 367.0 367.0 35.
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MECHANICAL DATA NHQ0016A SDA16A (Rev A) www.ti.
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