Datasheet

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36 - 78V

OUT

3.3V

SYNC I/O

LM5026

UVLO

PGND

AGND

COMP

OUT_A

OUT_B

SYNC

REF

TIME

RES

DCL

ERROR

AMP and

ISOLATION

LM5026

www.ti.com

SNVS363D –AUGUST 2005–REVISED APRIL 2013

LM5026 Active Clamp Current Mode PWM Controller

Check for Samples: LM5026

FEATURES

DESCRIPTION

The LM5026 PWM controller contains all of the

• Current Mode Control

features necessary to implement power converters

• Internal 100V Start-up Bias Regulator

utilizing the active clamp / reset technique with

• 3A Compound Main Gate Driver

current mode control. With the active clamp

technique, higher efficiencies and greater power

• High Bandwidth Opto-coupler Interface

densities can be realized compared to conventional

• Programmable Line Under-Voltage Lockout

catch winding or RDC clamp / reset techniques. Two

(UVLO) with Adjustable Hysteresis

control outputs are provided, the main power switch

• Versatile Dual Mode Over-Current Protection

control (OUT_A) and the active clamp switch control

with hiccup delay timer

(OUT_B). The device can be configured to control

either a P-Channel or N-Channel clamp switch. The

• Programmable Overlap or Deadtime between

main gate driver features a compound configuration,

the Main and Active Clamp Outputs

consisting of both MOS and Bipolar devices,

• Programmable Maximum Duty Cycle Clamp

providing superior gate drive characteristics. The

• Programmable Soft-start LM5026 can be configured to operate with bias

voltages over a wide input range of 8V to 100V.

• Leading Edge Blanking

Additional features include programmable maximum

• Resistor Programmed 1MHz Capable Oscillator

duty cycle, line under-voltage lockout, cycle-by-cycle

• Oscillator Sync I/O Capability

current limit, hiccup mode fault operation with

adjustable timeout delay, PWM slope compensation,

• Precision 5V Reference

soft-start, 1MHz capable oscillator with

synchronization input / output capability, precision

PACKAGES

reference and thermal shutdown.

• TSSOP-16

• WSON-16 (5x5 mm) Thermally Enhanced

Typical Application Circuit

Figure 1. Simplified Forward Power Converter with Active Clamp Reset

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (33 pages)

PAGE 1
LM5026 www.ti.com SNVS363D – AUGUST 2005 – REVISED APRIL 2013 LM5026 Active Clamp Current Mode PWM Controller Check for Samples: LM5026 FEATURES DESCRIPTION • • • • • The LM5026 PWM controller contains all of the features necessary to implement power converters utilizing the active clamp / reset technique with current mode control. With the active clamp technique, higher efficiencies and greater power densities can be realized compared to conventional catch winding or RDC clamp / reset techniques.
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LM5026 SNVS363D – AUGUST 2005 – REVISED APRIL 2013 www.ti.com Connection Diagram VIN 1 16 DCL UVLO 2 15 SYNC 16 DCL VIN 1 UVLO 2 15 SYNC CS 3 CS 3 14 RT RES 4 13 COMP TIME 5 12 SS REF 6 11 AGND VCC 7 10 PGND OUT_A 8 9 OUT_B RES 4 TIME 5 14 RT EP REF 6 11 AGND VCC 7 10 PGND OUT_A 8 Figure 2. 16-Lead TSSOP 13 COMP 12 SS 9 OUT_B Figure 3.
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LM5026 www.ti.com SNVS363D – AUGUST 2005 – REVISED APRIL 2013 PIN DESCRIPTIONS (continued) Pin EP Name Description Application Information Exposed Pad Exposed Pad, underside of (WSON WSON package Package Only) Connect to system ground plane for reduced thermal resistance. Block Diagram 7.6V BIAS REGULATOR VIN VCC VCC UVLO STANDBY REF 5V REFERENCE UVLO 1.25V LOGIC HYSTERESIS (20 PA) SHUTDOWN VCC THERMAL LIMIT 0.4V/0.
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LM5026 SNVS363D – AUGUST 2005 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) VIN to GND -0.3V to 105V VCC to GND -0.3V to 16V CS to GND -0.3 to 1.0V COMP Input Current 10mA All other inputs to GND -0.
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LM5026 www.ti.com SNVS363D – AUGUST 2005 – REVISED APRIL 2013 Electrical Characteristics (continued) Specifications with standard typeface are for TJ = 25°C, and those with boldface type apply over full Operating Junction Temperature range. VIN = 48V, VCC = 10V, RT = 30.0kΩ, RSET = 34.8kΩ) unless otherwise stated (1) Symbol Parameter Conditions Min Undervoltage Shutdown Hysteresis Typ Max Units 0.1 V Undervoltage Standby Threshold 1.21 1.25 1.
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LM5026 SNVS363D – AUGUST 2005 – REVISED APRIL 2013 www.ti.com Electrical Characteristics (continued) Specifications with standard typeface are for TJ = 25°C, and those with boldface type apply over full Operating Junction Temperature range. VIN = 48V, VCC = 10V, RT = 30.0kΩ, RSET = 34.
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LM5026 www.ti.com SNVS363D – AUGUST 2005 – REVISED APRIL 2013 Typical Performance Characteristics VCC Regulator Start-up Characteristics, VCC vs Vin VCC vs ICC 10 16 14 VIN 8 12 VCC (V) VCC (V) 10 8 VCC 6 6 4 4 2 2 0 0 2 4 6 8 10 12 14 0 16 5 10 20 25 30 Figure 5. Figure 6. VREF vs IREF Soft-start, Soft-stop and Restart Current vs Temperature 1.4 54 SOFT-START & STOP CURRENT (PA) 6 5 4 3 2 1 0 0 5 35 ICC (mA) VIN (V) VREF (V) 15 10 15 20 25 1.3 52 SOFT-STOP 1.
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LM5026 SNVS363D – AUGUST 2005 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) Overlap Time vs RSET Overlap Time vs Temperature 120 400 115 350 110 300 OVERLAP TIME (ns) OVERLAP TIME (ns) RSET to AGND 250 200 150 105 100 95 100 90 50 85 RSET = 34.8 k: 0 0 20 40 80 60 100 80 -50 120 -25 0 25 50 75 100 125 150 RSET (k:) TEMPERATURE ( C) Figure 11. Figure 12.
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LM5026 www.ti.com SNVS363D – AUGUST 2005 – REVISED APRIL 2013 Typical Performance Characteristics (continued) COMP Current vs INV PWM Comparator Voltage 800 -40°C COMP CURRENT (PA) 700 25°C 85°C 600 125°C 500 400 300 -0.10 0.00 0.10 0.20 0.30 0.40 0.50 INVERTING INPUT TO PWM COMPARATOR (V) Figure 17.
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LM5026 SNVS363D – AUGUST 2005 – REVISED APRIL 2013 www.ti.com DETAILED OPERATING DESCRIPTION The LM5026 PWM controller contains all of the features necessary to implement power converters utilizing the active clamp reset technique with current mode control. With the active clamp reset, higher efficiencies and greater power densities can be realized compared to conventional catch winding or RDC clamp reset techniques.
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LM5026 www.ti.com SNVS363D – AUGUST 2005 – REVISED APRIL 2013 PWM Outputs The relative phase of the main switch gate driver OUT_A and active clamp gate driver OUT_B can be configured for multiple applications. For active clamp configurations utilizing a ground referenced P-Channel clamp switch, the two outputs should be in phase, with the active clamp output overlapping the main output.
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LM5026 SNVS363D – AUGUST 2005 – REVISED APRIL 2013 www.ti.com VCC LM5026 PWM OUT_A PGND Figure 19. Compound Gate Driver PWM Comparator/Slope Compensation The PWM comparator modulates the pulse width of the controller output by comparing the current sense ramp signal to the loop error signal. This comparator is optimized for speed in order to achieve minimum controllable duty cycles. The loop error signal is input into the controller in the form of a control current into the COMP pin.
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LM5026 www.ti.com SNVS363D – AUGUST 2005 – REVISED APRIL 2013 The main output (OUT_A) duty cycle is normally controlled by the control current sourced into the COMP pin from the external feedback circuit. When the feedback demands maximum output from the converter, the duty cycle will be limited by one of two circuits within the LM5026: the user programmable duty cycle clamp and the voltage-dependent duty cycle limiter, which varies inversely with the input line voltage.
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LM5026 SNVS363D – AUGUST 2005 – REVISED APRIL 2013 www.ti.com Soft-Start/Soft-Stop The soft-start circuit allows the regulator to gradually reach a steady state operating point, thereby reducing startup stresses and current surges. Upon turn-on, the SS pin capacitor is discharged by an internal switch. When the UVLO, VCC and REF pins reach their operating thresholds, the SS capacitor is released and charged with a 50uA current source. The PWM comparator control voltage is clamped to the SS pin voltage.
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LM5026 www.ti.com SNVS363D – AUGUST 2005 – REVISED APRIL 2013 sequences will occur. 2. Hiccup only: The timer can be configured for immediate activation of a hiccup sequence upon detection of an overload by leaving the RES pin open circuit. 3. Delayed Hiccup: The most common configuration as previously described, is a programmed interval of cycle-by-cycle limiting before initiating a hiccup mode restart.
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LM5026 SNVS363D – AUGUST 2005 – REVISED APRIL 2013 www.ti.com LM5026 SYNC LM5026 SYNC UP TO 5 TOTAL DEVICES Figure 25. Sync from Multiple Devices Multiple LM5026 devices can be synchronized together simply by connecting the devices SYNC pins together as shown in Figure 25. Care should be taken to ensure the ground potential differences between devices are minimized. In this configuration all of the devices will be synchronized to the highest frequency device.
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LM5026 www.ti.com SNVS363D – AUGUST 2005 – REVISED APRIL 2013 Applications Information LINE INPUT (VIN) The LM5026 contains an internal high voltage start-up regulator that allows the input pin (VIN) to be connected directly to a nominal 48V line voltage. The voltage applied to the VIN pin can vary in the range of 13 to 100V with transient capability to 105V. When power is applied and the UVLO pin potential is greater than 0.
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LM5026 SNVS363D – AUGUST 2005 – REVISED APRIL 2013 www.ti.com UNDER-VOLTAGE LOCKOUT (UVLO) When the UVLO pin voltage is below 0.4V the controller is in a low current shutdown mode. When the UVLO pin voltage is greater than 0.4V but less than 1.25V the controller is in standby mode. When the UVLO pin voltage is greater than 1.25V the controller is fully enabled. Typically, two external resistors program the minimum operational voltage for the power converter as shown in Figure 29.
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LM5026 www.ti.com SNVS363D – AUGUST 2005 – REVISED APRIL 2013 The SYNC pin can be used to synchronize the internal oscillator to an external clock. An open drain output is the recommended interface from the external clock to the SYNC pin. The clock pulse width should be greater than 15 ns. The external clock must be a higher frequency than the free running frequency set by the RT resistor. Multiple LM5026 devices can be synchronized together simply by connecting the devices SYNC pins together.
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LM5026 SNVS363D – AUGUST 2005 – REVISED APRIL 2013 www.ti.com HICCUP MODE CURRENT LIMIT RESTART (RES) The basic operation of the hiccup mode current limit restart is described in the functional description. The delay time to restart is programmed with the selection of the RES pin capacitor CRES as illustrated in Figure 23. In the case of continuous cycle-by-cycle current limit detection at the CS pin, the time required for CRES to reach the 2.5V hiccup mode threshold is: t1 = CRES x 2.5 10 PA 5 = 2.
PAGE 21
LM5026 www.ti.com SNVS363D – AUGUST 2005 – REVISED APRIL 2013 The cool down time, t2 is set by the soft-start capacitor (CSS) and the internal 1 µA SS current source, and is equal to: t2 = CSS x 1.4V 1 PA 6 = 1.4 x 10 x CSS (9) If CSS = 0.01 µF, t2 is ≈14 ms. The soft-start time t3 is set by the internal 50 µA current source, and is equal to: t3 = CSS x 3.
PAGE 22
LM5026 SNVS363D – AUGUST 2005 – REVISED APRIL 2013 www.ti.com VPWR R1A LM5026 20 PA R1B UVLO Z1 1.25V R2 Max. Duty Cycle Limiter VPWR Z1 LM5026 20 PA R1 UVLO 1.25V R2 Max. Duty Cycle Limiter Figure 33. Altering the Slope of Duty Cycle vs. VPWR Programmable Maximum Duty Cycle Clamp (DCL) When the UVLO pin is biased at 1.25V (minimum operating level), the maximum duty cycle of OUT_A is limited by the duty cycle of the internal clock signal.
PAGE 23
LM5026 www.ti.com SNVS363D – AUGUST 2005 – REVISED APRIL 2013 The two ground pins (AGND, PGND) must be connected together with a short direct connection to avoid jitter due to relative ground bounce. If the internal dissipation of the LM5026 produces high junction temperatures during normal operation, the use of multiple vias under the IC to a ground place can help conduct heat away from the IC.
PAGE 24
LM5026 SNVS363D – AUGUST 2005 – REVISED APRIL 2013 www.ti.com Figure 34. Application Circuit: Input 36-78V, Output 3.
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LM5026 www.ti.com SNVS363D – AUGUST 2005 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision C (April 2013) to Revision D • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 22-Mar-2014 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
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PACKAGE MATERIALS INFORMATION www.ti.com 18-Apr-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing LM5026MTX/NOPB TSSOP LM5026MTX/NOPB LM5026SD/NOPB LM5026SDX/NOPB SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant PW 16 2500 330.0 12.4 6.95 8.3 1.6 8.0 12.0 Q1 TSSOP PW 16 2500 330.0 12.4 6.95 8.3 1.6 8.0 12.0 Q1 WSON NHQ 16 1000 178.0 12.4 5.3 5.3 1.3 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 18-Apr-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5026MTX/NOPB TSSOP PW 16 2500 367.0 367.0 35.0 LM5026MTX/NOPB TSSOP PW 16 2500 367.0 367.0 35.0 LM5026SD/NOPB WSON NHQ 16 1000 210.0 185.0 35.0 LM5026SDX/NOPB WSON NHQ 16 4500 367.0 367.0 35.
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MECHANICAL DATA NHQ0016A SDA16A (Rev A) www.ti.
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