Datasheet

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ERROR AMP

& ISOLATION

ERROR AMP

& ISOLATION

CS1

CS2

OUT1

OUT2

AC1

AC2

COMP1

COMP2

VIN

SS1

SS2

VCC2

DCL

OVLP

VCC1

RES

UVLO

LM5034

3.3V

2.5V

Sync

36V to 75V

Input

GND1 GND2

PWR

LM5034

www.ti.com

SNVS347A –FEBRUARY 2005–REVISED APRIL 2013

LM5034 High Voltage Dual Interleaved Current Mode Controller with Active Clamp

Check for Samples: LM5034

FEATURES

APPLICATIONS

• Two Independent PWM Current Mode

• Telecommunication Power Converters

Controllers

• Industrial Power Converters

• Integrated High Voltage Startup Regulator

• +42V Automotive Systems

• Compound 2.5A Main Output Gate Drivers

DESCRIPTION

• Single Resistor Oscillator Setting to 2 MHz

The LM5034 dual current mode PWM controller

• Synchronizable Oscillator

contains all the features needed to control either two

• Active Clamp Gate Driver for P-Channel

independent forward/active clamp dc/dc converters or

MOSFETs

a single high current converter comprised of two

interleaved power stages. The two controller

• Adjustable Gate Drive Overlap Time

channels operate 180° out of phase thereby reducing

• Programmable Maximum Duty Cycle

input ripple current. The LM5034 includes a startup

• Maximum Duty Cycle Fold-Back at High Line

regulator that operates over a wide input range up to

Voltage

100V and compound (bipolar + CMOS) gate drivers

that provide a robust 2.5A peak sink current. The

• Adjustable Timer for Hiccup Mode Current

adjustable dead-time of the active clamp gate drivers

Limiting

and adjustable maximum PWM duty cycle reduce

• Integrated Slope Compensation

stress on the primary side MOSFET switches.

• Adjustable Line Under-Voltage Lockout

Additional features include programmable line under-

voltage lockout, cycle-by-cycle current limit, hiccup

• Independently Adjustable Soft-Start (Each

mode fault operation with adjustable restart delay,

Regulator)

PWM slope compensation, soft-start, and a 2 MHz

• Direct Interface with Opto-Coupler Transistor

capable oscillator with synchronization capability.

• Thermal Shutdown

PACKAGE

• TSSOP-20

Typical Application Circuit

Figure 1. Dual Interleaved Regulators with Independent Outputs

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (36 pages)

PAGE 1
LM5034 www.ti.com SNVS347A – FEBRUARY 2005 – REVISED APRIL 2013 LM5034 High Voltage Dual Interleaved Current Mode Controller with Active Clamp Check for Samples: LM5034 FEATURES APPLICATIONS • • • • 1 2 • • • • • • • • • • • • • • Two Independent PWM Current Mode Controllers Integrated High Voltage Startup Regulator Compound 2.
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LM5034 SNVS347A – FEBRUARY 2005 – REVISED APRIL 2013 www.ti.com Connection Diagram 1 2 3 4 5 6 7 8 9 10 OVLP VIN COMP1 RT/SYNC DCL COMP2 CS1 CS2 SS1 SS2 UVLO RES VCC1 VCC2 OUT1 OUT2 AC1 GND1 AC2 GND2 20 19 18 17 16 15 14 13 12 11 Figure 2.
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LM5034 www.ti.com SNVS347A – FEBRUARY 2005 – REVISED APRIL 2013 PIN DESCRIPTIONS PIN NAME 1 OVLP 2 VIN 3 COMP1 4 DESCRIPTION APPLICATIONS INFORMATION Active Clamp Overlap Adjust An external resistor (10 kΩ to 100 kΩ) sets the overlap time of the active clamp outputs relative to the main outputs for both Controller 1 and Controller 2. The overlap time results in deadtime between each main switch and its active clamp switch. Input Supply Input to the startup regulator.
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LM5034 SNVS347A – FEBRUARY 2005 – REVISED APRIL 2013 www.ti.com Block Diagram 7.7V SERIES REGULATOR VI N VCC1 VCC 5 VCC Disable THERMAL SHUTDOWN BIAS VOLTAGE GENERATOR RT/ SYNC 5 VCC1 VCC2 VCC UVT CLK1, 2 UserMaxDC1, 2 OSCILLATOR & RAMP GENERATOR 20 PA RAMP1, 2 UVLO 5.0V MaxDC1 Ramp1 -VUVLO LOGIC Clk1,2 10 PA DC1,2 2.55V MaxDC2 R S Vref Q Q Ramp2 Restart Latch Support Functions Restart 5.
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LM5034 www.ti.com SNVS347A – FEBRUARY 2005 – REVISED APRIL 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) VIN to GND -0.3V to 105V VCC to GND -0.3V to 16V RT/SYNC, RES and DCL to GND -0.3V to 5.5V CS Pins to GND -0.3V to 1.25V All other inputs to GND ESD Rating (3) -0.
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LM5034 SNVS347A – FEBRUARY 2005 – REVISED APRIL 2013 www.ti.com Electrical Characteristics Specifications with standard typeface are for TJ = 25°C, and those with boldface type apply over full Operating Junction Temperature range. VIN = 48V, VCC1 = VCC2 = 10V externally applied, RT = RDCL = 42.2kΩ, ROVLP =70kΩ, UVLO = 1.5V, unless otherwise stated. See (1) and (2).
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LM5034 www.ti.com SNVS347A – FEBRUARY 2005 – REVISED APRIL 2013 Electrical Characteristics (continued) Specifications with standard typeface are for TJ = 25°C, and those with boldface type apply over full Operating Junction Temperature range. VIN = 48V, VCC1 = VCC2 = 10V externally applied, RT = RDCL = 42.2kΩ, ROVLP =70kΩ, UVLO = 1.5V, unless otherwise stated. See(1) and (2). Symbol ICOMP Parameter COMP1 (COMP2) short circuit current Conditions COMP1 (COMP2) = 0V Min Typ Max Units 0.6 1 1.
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LM5034 SNVS347A – FEBRUARY 2005 – REVISED APRIL 2013 www.ti.com TEST CIRCUIT DIAGRAMS Timing Diagram 1/OSC. FREQ. INTERNAL CLOCK 40% 60% CLK1 CLK2 VDCL RAMP1 -VUVLO VDCL RAMP2 -VUVLO CLK1 UserMaxDC1 MaxDC1 PWM Comp1 PWM1 OUT1 CLK2 UserMaxDC2 MaxDC2 PWM Comp2 PWM2 OUT2 Figure 4.
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LM5034 www.ti.com SNVS347A – FEBRUARY 2005 – REVISED APRIL 2013 UVLO VIN UVT VCC tVCC 1.5V SS1 1.5V COMP1 t1 OUT1 SS2 COMP2 1.5V 1.5V OUT2 Figure 5.
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LM5034 SNVS347A – FEBRUARY 2005 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics IIN vs VIN IIN vs VIN 600 14 VCC Pins = Open INPUT CURRENT IIN (mA) INPUT CURRENT IIN (PA) 500 400 300 UVLO = 0V 200 VCC Pins = 10V 100 12 VCC pins = open, 10 OUT1 & OUT2 load = 2200 pF AC1 & AC2 load = 150 pF 8 VCC pins = open, Driver Outputs Open 6 4 UVLO > 1.25V Outputs frequency = 200 kHz VCC pins = 10V, Driver Outputs open or loaded 2 0 0 0 20 40 60 80 100 0 20 40 Figure 6.
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LM5034 www.ti.com SNVS347A – FEBRUARY 2005 – REVISED APRIL 2013 Typical Performance Characteristics (continued) User Defined Maximum Duty Cycle vs. RDCL Resistor Maximum Duty Cycle vs. UVLO Voltage 100 80 MAXIMUM DUTY CYCLE (%) MAXIMUM DUTY CYCLE (%) 100 UVLO Pin = 1.26V 60 40 20 80 60 40 20 0 0 0 RDCL/RT 1.0 2.0 3.0 4.0 1.25V VOLTAGE AT UVLO PIN (V) Figure 12. Figure 13. 0.2 0.4 0.6 0.8 0 1.0 Maximum Duty Cycle vs. VIN (Figure 31) 5.0 Active Clamp Overlap Time vs.
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LM5034 SNVS347A – FEBRUARY 2005 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) Soft-start Pin Current vs. Temperature Current Limit Threshold at CS1, CS2 vs. Temperature 510 55 45 | | 1.10 1.0 0.9 -50 CURRENT LIMIT THRESHOLD @ CS1, CS2 (mV) SOFT-START CURRENT (PA) 508 50 506 504 502 500 498 496 494 492 490 0 50 100 150 -50 TEMPERATURE (oC) 0 50 100 150 TEMPERATURE (oC) Figure 18. Figure 19.
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LM5034 www.ti.com SNVS347A – FEBRUARY 2005 – REVISED APRIL 2013 LM5034 VCC 7.6V/6.2V THERMAL SHUTDOWN VPWR VCC Disable 20 PA R1 UVLO Drivers Off UVLO 1.25V R2 Max . Duty Cycle Limiter Figure 20. Drivers Off and VCC Disable Startup Regulator, VIN, VCC1, VCC2 The high voltage startup regulator is integral to the LM5034. The input pin VIN can be connected directly to a voltage between 13V and 100V, with transient capability to 105V.
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LM5034 SNVS347A – FEBRUARY 2005 – REVISED APRIL 2013 www.ti.com Oscillator The oscillator frequency is set with an external resistor RT connected between the RT/SYNC and GND1 pins. The resistor value is calculated from: RT = 17100 FS - 0.001(FS - 400) (1) where FS is the desired oscillator frequency in kHz (maximum of 2 MHz), and RT is in kΩ. See Figure 11. The two gate driver outputs (OUT1 and OUT2) switch at half the oscillator frequency and 180° out of phase with each other.
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LM5034 www.ti.com SNVS347A – FEBRUARY 2005 – REVISED APRIL 2013 Cycle-by-Cycle Current Limit Each CS pin is designed to accept a signal representative of its transformer primary current. If the voltage at CS exceeds 0.5V the current sense comparator terminates the present main output driver (OUT pin) pulse. If the high current fault persists, the controller operates with constant peak switch current in a cycle-by-cycle current limit mode, and a Hiccup Mode Current Limit Restart cycle begins (see below).
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LM5034 SNVS347A – FEBRUARY 2005 – REVISED APRIL 2013 www.ti.com CS1 Current Limit Current Sense Circuit 5.0V Restart Current Source Logic 0.5V Clk1, Clk2 Current Limit Current Sense Circuit 20PA 10 PA RES C RES 0.5V CS2 SS1 COMP1 Voltage Feedback DC1 PWM #1 To Output Drivers 2.
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LM5034 www.ti.com SNVS347A – FEBRUARY 2005 – REVISED APRIL 2013 If the internal Drivers Off line is activated (see Drivers Off, VCC Disable), both SS pins are internally grounded. The SS pins pull the COMP pins to ground while the Driver Off signal disables the output drivers. When the event which activated the Drivers Off line is cleared and Vcc exceeds its under-voltage threshold, the SS pins are released.
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LM5034 SNVS347A – FEBRUARY 2005 – REVISED APRIL 2013 www.ti.com OUT1 and OUT2 are compound gate drivers with CMOS and Bipolar output transistors as shown in Figure 24. The parallel MOS and Bipolar devices provide a faster turn-off of the primary switch thereby reducing switching losses. The outputs switch at one-half the oscillator frequency with the rising edges at OUT1 and OUT2 180° out of phase with each other. The on-time of OUT1 and OUT2 is determined by their respective duty cycle control.
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LM5034 www.ti.com SNVS347A – FEBRUARY 2005 – REVISED APRIL 2013 APPLICATIONS INFORMATION VIN The voltage applied to the VIN pin, normally the same as the system voltage applied to the power transformer’s primary (VPWR), can vary in the range of 13 to 100V with transient capability to 105V. The current into VIN depends primarily on the output driver capacitive loads, the switching frequency, and any external loads on the VCC pins.
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LM5034 SNVS347A – FEBRUARY 2005 – REVISED APRIL 2013 www.ti.com UVLO The under-voltage lockout threshold (UVLO) is internally set at 1.25V at the UVLO pin. With two external resistors as shown in Figure 29, the LM5034 is enabled when VPWR exceeds the programmed threshold voltage. When VPWR is above the threshold, the internal 20 µA current source is enabled to raise the voltage at the UVLO pin, providing hysteresis. R1 and R2 are determined from the following equations: R1 = VHYS/20 µA R2 = (4) 1.
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LM5034 www.ti.com SNVS347A – FEBRUARY 2005 – REVISED APRIL 2013 The average VCC regulator current required to drive the external MOSFETs is a function of the MOSFET gate capacitance and the switching frequency (see Figure 8). To ensure VCC does not droop below the lower UVT threshold, an external supply should be diode connected to both VCC pins to provide the required current, as shown in Figure 31. The applied VCC voltage must be between 8V and 15V. Providing the VCC voltage higher than the 7.
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LM5034 SNVS347A – FEBRUARY 2005 – REVISED APRIL 2013 www.ti.com Power Current Sense VPWR Transformer VIN CS1 LM5034 RF CF R1 GND1 CAC Q1 Q2 OUT1 AC1 Figure 32. Current Sense Using a Current Sense Transformer Power Transformer VPWR CAC VIN Q1 Q2 OUT1 LM5034 RF CS1 CF R1 GND1 AC1 Figure 33. Current Sense Using a Source Sense Resistor (R1) HICCUP MODE CURRENT LIMIT RESTART This circuit’s operation is described in the Functional Description. Also see Figure 22 and Figure 23.
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LM5034 www.ti.com SNVS347A – FEBRUARY 2005 – REVISED APRIL 2013 If the application requires no delay from the first detection of a current limit condition, so that t1 is effectively zero, the RES pin can be left open (no external capacitor). If it is desired to disable the hiccup mode current limit operation then the RES pin should be connected to ground.
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LM5034 SNVS347A – FEBRUARY 2005 – REVISED APRIL 2013 www.ti.com LINE VOLTAGE DEPENDENT MAXIMUM DUTY CYCLE As VPWR increases and the voltage at UVLO follows, the maximum allowed duty cycle decreases according to the graph of Figure 13. Using values from the example above (R1 = 150 kΩ, R2 = 10 kΩ in Figure 29), the maximum duty cycle varies as shown in Figure 14. If it is desired to increase the slope of the ramp in Figure 14, Figure 35 shows a suggested configuration.
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LM5034 www.ti.com SNVS347A – FEBRUARY 2005 – REVISED APRIL 2013 APPLICATION CIRCUIT EXAMPLE Figure 40 shows an example of an LM5034 controlled 200W dual interleaved regulator which provides two independent regulated outputs or a single high current output. The input voltage range (VPWR) is 36V to 78V, and the output voltages are 3.3V and 2.5V in the dual output mode, or 3.3V in the single output mode. The output current capability is 30A from each output or 60A in the single output mode.
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LM5034 SNVS347A – FEBRUARY 2005 – REVISED APRIL 2013 www.ti.com 100 EFFICIENCY (%) 80 VIN = 48V VIN = 36V 60 VIN = 78V 40 20 3.3V and 2.5V outputs loaded equally, simultaneously 0 0 5 10 15 20 25 30 LOAD CURRENT (A) Figure 38. Total Board Efficiency, Independent Outputs 100 EFFICIENCY (%) 80 VIN = 48V VIN = 36V 60 40 VIN = 78V 20 VOUT = 3.3V 0 0 10 20 30 40 50 60 LOAD CURRENT (A) Figure 39.
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LM5034 www.ti.com SNVS347A – FEBRUARY 2005 – REVISED APRIL 2013 Evaluation Board Schematic Figure 40.
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LM5034 SNVS347A – FEBRUARY 2005 – REVISED APRIL 2013 www.ti.com Table 1. Bill of Materials (Circuit of Figure 40) Description Package Value C1-4 Item Capacitor 1812 2.2 µF, 100V C5, 50 Capacitor 1812 0.01 µF, 1000V C6, 17, 19 Capacitor 1206 0.1 µF, 250V C7, 10, 11, 35, 38 Capacitor 0805 0.01 µF, 50V C8, 16, 18, 24, 26, 27, 39, 40, 42 Capacitor 0805 0.1 µF, 50V C9 Capacitor 0805 100 pF C12, 13 Capacitor 1210 10 µF, 16V C14, 15 Capacitor 0805 0.
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LM5034 www.ti.com SNVS347A – FEBRUARY 2005 – REVISED APRIL 2013 Table 1. Bill of Materials (Circuit of Figure 40) (continued) Item Description Package Value Dual Optocoupler SO8 MOCD207M U3, 4 Op Amp SOT23-5 LM8261 U5, 6 Reference SOT23 LM4040-4.
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LM5034 SNVS347A – FEBRUARY 2005 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Original (April 2013) to Revision A • 30 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device LM5034MTCX/NOPB Package Package Pins Type Drawing TSSOP PW 20 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 7.1 1.6 8.0 W Pin1 (mm) Quadrant 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5034MTCX/NOPB TSSOP PW 20 2500 367.0 367.0 35.
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