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LM5041

www.ti.com

SNVS248D –AUGUST 2003–REVISED MARCH 2013

LM5041 Cascaded PWM Controller

Check for Samples: LM5041

FEATURES

PACKAGES

• Internal Start-up Bias Regulator

• TSSOP-16

• Programmable Line Under-Voltage Lockout • WSON-16 (5x5 mm) Thermally Enhanced

(UVLO) with Adjustable Hysteresis

DESCRIPTION

• Current Mode Control

The LM5041 PWM controller contains all of the

• Internal Error Amplifier with Reference

features necessary to implement either current-fed or

• Dual Mode Over-Current Protection

voltage-fed push-pull or bridge power converters.

• Leading Edge Blanking

These “Cascaded” topologies are well suited for

multiple output and higher power applications. The

• Programmable Push-Pull Overlap or Dead

LM5041’s four control outputs include: the buck stage

Time

controls (HD and LD) and the push-pull control

• Internal 1.5A Push-Pull Gate Drivers

outputs (PUSH and PULL). Push-pull outputs are

• Programmable Soft-start

driven at 50% nominal duty cycle at one half of the

switching frequency of the buck stage and can be

• Programmable Oscillator with Sync Capability

configured for either a specified overlap time (for

• Precision Reference

current-fed applications) or a specified both-off time

• Thermal Shutdown

(for voltage-fed applications). Push-pull stage

MOSFETs can be driven directly from the internal

gate drivers while the buck stage requires an external

APPLICATIONS

driver such as the LM5102. The LM5041 includes a

• Telecommunication Power Converters

high-voltage start-up regulator that operates over a

• Industrial Power Converters

wide input range of 15V to 100V. The PWM controller

is designed for high-speed capability including an

• Multi-Output Power Converters

oscillator frequency range up to 1 MHz and total

• +42V Automotive Systems

propagation delays of less than 100ns. Additional

features include: line Under-Voltage Lockout (UVLO),

soft-start, an error amplifier, precision voltage

reference, and thermal shutdown.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (22 pages)

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LM5041 www.ti.com SNVS248D – AUGUST 2003 – REVISED MARCH 2013 LM5041 Cascaded PWM Controller Check for Samples: LM5041 FEATURES PACKAGES • • • • 1 2 • • • • • • • • • • Internal Start-up Bias Regulator Programmable Line Under-Voltage Lockout (UVLO) with Adjustable Hysteresis Current Mode Control Internal Error Amplifier with Reference Dual Mode Over-Current Protection Leading Edge Blanking Programmable Push-Pull Overlap or Dead Time Internal 1.
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LM5041 SNVS248D – AUGUST 2003 – REVISED MARCH 2013 www.ti.com Typical Application Circuit VOUT 33 - 76V VDD HB VCC VIN HD HI HO HS LD LM5041 LI RT LM5102 2 VSS LO RT1 RT2 PUSH FEED BACK PULL FB Figure 1. Simplified Cascaded Push-Pull Power Converter Connection Diagram 1 2 3 4 5 6 7 8 VIN UVLO FB RT COMP 15 14 TIME 13 REF SS HD CS LD AGND VCC PGND PUSH 16 12 11 10 9 PULL Figure 2.
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LM5041 www.ti.com SNVS248D – AUGUST 2003 – REVISED MARCH 2013 PIN DESCRIPTION PIN NAME DESCRIPTION APPLICATION INFORMATION 1 VIN Source Input Voltage Input to start-up regulator. Input range 15V to 100V. 2 FB Feedback Signal Inverting input for the internal error amplifier. The noninverting input is connected to a 0.75V reference. 3 COMP Output of the Internal Error Amplifier There is an internal 5kΩ resistor pull-up on this pin. The error amplifier provides an active sink.
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LM5041 SNVS248D – AUGUST 2003 – REVISED MARCH 2013 www.ti.com Block Diagram Figure 3. Simplified Block Diagram 9V SERIES REGULATOR VIN VCC 5V REFERENCE VCC ENABLE VREF UVLO UVLO + - 2.5V LOGI C UVLO HYSTERESIS (20PA) 45PA CLK HD 5V SLOPE COMP RAMP GENERATOR COMP 5k 0.75V FB PWM 100k + - S Q LD + R 1.4V 50k Q LOGIC SS PGND CS 2k 0.5V + - CLK + LEB 0.6V + AGND 10PA SS SS TIME + 0.
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LM5041 www.ti.com SNVS248D – AUGUST 2003 – REVISED MARCH 2013 Absolute Maximum Ratings (1) (2) VIN to GND 100V VCC to GND 16V All Other Inputs to GND -0.3 to 7V Junction Temperature 150°C Storage Temperature Range -65°C to +150°C ESD Rating 2 kV Lead temperature (3) Wave 4 seconds 260°C Infrared 10 seconds 240°C Vapor Phase 75 seconds 219°C (1) Absolute Maximum Ratings are limits beyond which damage to the device may occur.
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LM5041 SNVS248D – AUGUST 2003 – REVISED MARCH 2013 www.ti.com Electrical Characteristics (continued) Specifications with standard typeface are for TJ = 25°C, and those with boldface type apply over full Operating Junction Temperature range. VIN = 48V, VCC = 10V, RT = 26.7kΩ, RSET = 20kΩ) unless otherwise stated.(1) Symbol Parameter Conditions Min Typ Max Units 5 5.15 V 25 50 mV Reference Supply VREF Ref Voltage IREF = 0 mA Ref Voltage Regulation IREF = 0 to 10mA 4.
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LM5041 www.ti.com SNVS248D – AUGUST 2003 – REVISED MARCH 2013 Electrical Characteristics (continued) Specifications with standard typeface are for TJ = 25°C, and those with boldface type apply over full Operating Junction Temperature range. VIN = 48V, VCC = 10V, RT = 26.7kΩ, RSET = 20kΩ) unless otherwise stated.(1) Symbol Typ Max Units Output Low Saturation Parameter IOUT = −10mA Conditions Min 0.
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LM5041 SNVS248D – AUGUST 2003 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics VCC and VIN vs VIN VCC vs ICC 10 20 VIN 8 VIN = 15V 6 VCC (V) VCC AND VIN (V) 15 VCC 10 4 5 2 0 0 5 0 15 10 20 0 5 10 15 VIN (V) ICC (mA) Figure 4. Figure 5. SS Pin Current vs Temp Frequency vs RT 13 20 25 1000 FREQUENCY (kHz) SS CURRENT (PA) 12 11 10 9 8 100 7 -25 25 75 125 10000 1000 Figure 6. Figure 7.
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LM5041 www.ti.com SNVS248D – AUGUST 2003 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Dead Time vs Temp 120 130 110 120 DEAD TIME (ns) OVERLAP TIME (ns) Overlap Time vs Temp 100 RSET = 20k: 90 80 70 110 RSET = 20k: 100 90 80 70 60 -25 25 75 -25 125 25 75 TEMPERATURE (oC) TEMPERATURE (oC) Figure 10. Figure 11. 125 Error Amplifier Gain Phase Figure 12.
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LM5041 SNVS248D – AUGUST 2003 – REVISED MARCH 2013 www.ti.com DETAILED OPERATING DESCRIPTION The LM5041 PWM controller contains all of the features necessary to implement either current-fed or voltage-fed push-pull or bridge power converters. These “Cascaded” topologies are well suited for multiple output and higher power applications. The LM5041’s four control outputs include: the buck stage controls (HD and LD) and the push-pull control outputs (PUSH and PULL).
PAGE 11
LM5041 www.ti.com SNVS248D – AUGUST 2003 – REVISED MARCH 2013 Push-Pull Outputs The push pull outputs operate continuously at a nominal 50% duty cycle. A distinguishing feature of the LM5041 is the ability to accurately configure either dead time (both-off) or overlap time (both-on) on the complementary push-pull outputs. The overlap/dead time magnitude is controlled by a resistor connected to the TIME pin on the controller. The TIME pin holds one end of the resistor at 2.
PAGE 12
LM5041 SNVS248D – AUGUST 2003 – REVISED MARCH 2013 www.ti.com Current Limit/Current Sense The LM5041 contains two levels of over-current protection. If the voltage at the CS pin exceeds 0.5V the present buck stage duty cycle is terminated (cycle by cycle current limit). If the voltage at the CS pin overshoots the 0.5V threshold and exceeds 0.6V, then the controller will terminate the present cycle and fully discharge the soft-start capacitor.
PAGE 13
LM5041 www.ti.com SNVS248D – AUGUST 2003 – REVISED MARCH 2013 Soft-start and Shutdown The soft-start feature allows the power converter to gradually reach the initial steady state operating point, thereby reducing start-up stresses and surges. At power on, a 10uA current is sourced out of the soft-start pin (SS) to charge an external capacitor. The capacitor voltage will ramp up slowly and will limit the maximum duty cycle of the buck stage.
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LM5041 SNVS248D – AUGUST 2003 – REVISED MARCH 2013 www.ti.com Application Circuit: Input 35-80V, Output 2.
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LM5041 www.ti.com SNVS248D – AUGUST 2003 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision C (March 2013) to Revision D • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing LM5041MTCX TSSOP LM5041MTCX/NOPB LM5041SD SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant PW 16 2500 330.0 12.4 6.95 8.3 1.6 8.0 12.0 Q1 TSSOP PW 16 2500 330.0 12.4 6.95 8.3 1.6 8.0 12.0 Q1 WSON NHQ 16 1000 178.0 12.4 5.3 5.3 1.3 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5041MTCX TSSOP PW 16 2500 367.0 367.0 35.0 LM5041MTCX/NOPB TSSOP PW 16 2500 367.0 367.0 35.0 LM5041SD WSON NHQ 16 1000 210.0 185.0 35.0 LM5041SD/NOPB WSON NHQ 16 1000 210.0 185.0 35.0 LM5041SDX/NOPB WSON NHQ 16 4500 367.0 367.0 35.
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MECHANICAL DATA NHQ0016A SDA16A (Rev A) www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.