Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - hot swap controller Multi-purpose VSSOP 10 Surface-mount

OUT

STATUS

UVLO

OVP

TIMER

GND

OUT

SENSE

GATE

VIN

LM5060

GND GND

nPGD

High = Fault, Low= OK

High = On, Low= Off

LM5060

www.ti.com

SNVS628F –OCTOBER 2009–REVISED APRIL 2013

LM5060 High-Side Protection Controller with Low Quiescent Current

Check for Samples: LM5060

FEATURES

APPLICATIONS

• Available in Automotive Grade / AEC Q-100

• Automotive Body Electronics

• Wide Operating Input Voltage Range: +5.5V to • Industrial Power Distribution and Control

+65V

PACKAGE

• Less than 15 µA Quiescent Current in Disabled

Mode

• 10-Lead VSSOP

• Controlled Output Rise Time for Safe

DESCRIPTION

Connection of Capacitive Loads

The LM5060 high-side protection controller provides

• Charge Pump Gate Driver for External N-

intelligent control of a high-side N-Channel MOSFET

Channel MOSFET

during normal on/off transitions and fault conditions.

• Adjustable Under-Voltage Lock-Out (UVLO)

In-rush current is controlled by the nearly constant

with Hysteresis

rise time of the output voltage. A power good output

• UVLO Serves as Second Enable Input for

indicates when the output voltage reaches the input

voltage and the MOSFET is fully on. Input Under-

Systems Requiring Safety Redundancy

Voltage Lock-Out, with hysteresis, is provided as well

• Programmable Fault Detection Delay Time

as programmable input Over-Voltage Protection. An

• MOSFET Latched off After Load Fault is

enable input provides remote On / Off control. The

Detected

programmable Under-Voltage Lock-Out input can be

used as second enable input for safety redundancy.

• Active Low Open Drain POWER GOOD (nPGD)

A single capacitor programs the initial start-up V

Output

fault detection delay time, the transition V

fault

• Adjustable Input Over-Voltage Protection

detection delay time, and the continuous Over-

(OVP)

Current V

fault detection delay time. When a

• Immediate Restart After Over-Voltage

detected fault condition persists longer than the

Shutdown

allowed fault delay time, the MOSFET is latched off

until either the Enable input or the Under-Voltage

Lock-Out input is toggled low and then high.

Typical Application

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (33 pages)

PAGE 1
LM5060 www.ti.com SNVS628F – OCTOBER 2009 – REVISED APRIL 2013 LM5060 High-Side Protection Controller with Low Quiescent Current Check for Samples: LM5060 FEATURES APPLICATIONS • • • • 1 2 • • • • • • • • • • Available in Automotive Grade / AEC Q-100 Wide Operating Input Voltage Range: +5.
PAGE 2
LM5060 SNVS628F – OCTOBER 2009 – REVISED APRIL 2013 www.ti.com Connection Diagram VIN 2 OVP 3 UVLO 4 EN 5 10 GATE LM5060Q1MM SENSE 1 9 OUT 8 nPGD 7 TIMER 6 GND Figure 1. 10-Lead VSSOP See Package Number DGS0010A PIN DESCRIPTIONS Pin No. Name Description Applications Information 1 SENSE Input Voltage Sense A constant current sink (16 μA typical) at the SENSE pin flows through an external resistor to set the threshold for fault detection.
PAGE 3
LM5060 www.ti.com SNVS628F – OCTOBER 2009 – REVISED APRIL 2013 Absolute Maximum Ratings (1) (2) VIN to GND (3) (4) -0.3V to 75V SENSE, OUT to GND (5) -0.3V to 75V GATE to GND (3) (5) -0.3V to 75V EN, UVLO to GND (4) -0.3V to 75V nPGD, OVP to GND -0.3V to 75V TIMER to GND -0.
PAGE 4
LM5060 SNVS628F – OCTOBER 2009 – REVISED APRIL 2013 www.ti.com Electrical Characteristics Unless otherwise stated the following conditions apply: VIN = 14V, EN =2.00V, UVLO =2.00V, OVP = 1.50V, and TJ = 25°C. Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the operating junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are ensured through test, design, or statistical correlation.
PAGE 5
LM5060 www.ti.com SNVS628F – OCTOBER 2009 – REVISED APRIL 2013 Electrical Characteristics (continued) Unless otherwise stated the following conditions apply: VIN = 14V, EN =2.00V, UVLO =2.00V, OVP = 1.50V, and TJ = 25°C. Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the operating junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are ensured through test, design, or statistical correlation.
PAGE 6
LM5060 SNVS628F – OCTOBER 2009 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics 6 VIN Pin Current vs. VIN Pin Voltage VGATE, VIN Voltage vs. Input Voltage Figure 2. Figure 3. OUT Pin Current (IOUT-EN) vs. VIN Voltage GATE Current (IGATE) vs VIN Voltage Figure 4. Figure 5. SENSE Current (ISENSE) vs VIN Voltage nPGD Low Voltage (PGDVOL vs Sink Current) Figure 6. Figure 7.
PAGE 7
LM5060 www.ti.com SNVS628F – OCTOBER 2009 – REVISED APRIL 2013 Typical Performance Characteristics (continued) GATE Pull-Down Current Off (IGATE-OFF) vs. GATE Voltage EN Threshold Voltage (ENTH) vs. Temperature Figure 8. Figure 9. UVLO Threshold Voltage (UVLOTH) vs. Temperature GATE Pull-Down Current Fault (IGATE-FLT) vs. GATE Voltage Figure 10. Figure 11. UVLO, EN Current vs. Temperature OVP Threshold (OVPTH), Hysteresis (OVPHYS) vs. Temperature Figure 12. Figure 13.
PAGE 8
LM5060 SNVS628F – OCTOBER 2009 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) VGS Comparator Threshold Voltage (VGATE-TH) vs. Temperature VDS Comparator Offset Voltage (VOFFSET) vs. Temperature Figure 14. Figure 15. GATE Current (IGATE) vs. Temperature GATE Output Voltage (VGATE) vs. Temperature Figure 16. Figure 17. Gate Pull-Down Current - Fault (IGATE-FLT) vs. Temperature Figure 18.
PAGE 9
LM5060 www.ti.com SNVS628F – OCTOBER 2009 – REVISED APRIL 2013 Typical Performance Characteristics (continued) VIN Pin Current (IEN) vs EN Voltage nPGD Low Voltage (PGDVOL) vs. Temperature Figure 19. Figure 20.
PAGE 10
LM5060 SNVS628F – OCTOBER 2009 – REVISED APRIL 2013 www.ti.com Block Diagram GATE OUT LM5060 VIN IGATE 24 PA Charge Pump 16.8V 1 k: VGS Status Comparator IOUT-EN 8 PA VGATE-TH 5V Normal OFF OUT+5V VDS Fault Comparator IGATE-OFF 2.2 mA 500: SENSE Fault OFF ISENSE 16 PA IGATE-FLT 80 mA nPGD PGOOD 6 PA: Start-Up Fault Timer 11 PA: O-C (VDS) Fault Timer One shot 5 PA OVP 6 PA OV OVPTH 2.0V UVLOTH 1.6V TIMER UVLO ITIMERR 6 mA UVLOBIAS 5.5 PA nEN S Q Reset Latch 1.
PAGE 11
LM5060 www.ti.com SNVS628F – OCTOBER 2009 – REVISED APRIL 2013 Q1 VIN VOUT RS SENSE GATE OUT VIN R4 R10 LM5060 UVLO R8 R11 R9 STATUS EN High = Fault, Low= OK OVP TIMER C1 nPGD GND High = On, Low= Off EN GND GND Figure 21. Basic Application Circuit Functional Description The LM5060 is designed to drive an external high-side N-channel MOSFET. Over-Current protection is implemented by sensing the voltage drop across the MOSFET.
PAGE 12
LM5060 SNVS628F – OCTOBER 2009 – REVISED APRIL 2013 www.ti.com VTMRH 11 PA VTIMER 6 PA VTMRL VGATE-TH VGS transition region nPGD Fault VGS Status EN VGS < 5V OFF OK VGS > 5V ON Figure 22. Voltages During Normal Start Up Sequence Table 1. Overview of Operating Conditions Input Conditions Outputs Status UVLO OVP (typ) VIN (typ) SENSE-OUT GATEOUT VIN Current (typ) L L - >5.10V NA NA 0.009 mA 2.2 mA sink Low NA NA Disabled L H - >5.10V NA NA 0.009 mA 2.
PAGE 13
LM5060 www.ti.com SNVS628F – OCTOBER 2009 – REVISED APRIL 2013 FAULT TIMER An external capacitor connected from the TIMER pin to the GND pin sets the fault detection delay time. If the voltage on the TIMER capacitor reaches the VTMRH threshold (2V typical) a fault condition is indicated. The LM5060 will latch off the MOSFET by discharging the GATE pin at a 80mA (typical) rate, and will remain latched off until either the EN pin, the UVLO pin, or the VIN pin is toggled low and then high.
PAGE 14
LM5060 SNVS628F – OCTOBER 2009 – REVISED APRIL 2013 www.ti.com VTRMRH VTIMER 6 PA Fault Latch VTRMRL GATE pin will be discharged to GND at 80 mA rate VGATE-TH VGS nPGD Fault VGS < 5V VGS Status EN OFF ON Figure 23. Voltages During Startup with VGS Gate Leakage Condition VDS FAULT CONDITION The LM5060 includes a VDS Fault Comparator that senses the voltage difference between the SENSE pin and the OUT pin.
PAGE 15
LM5060 www.ti.com SNVS628F – OCTOBER 2009 – REVISED APRIL 2013 VTMRH 11 PA 6 PA VTIMER Fault Latch VTMRL GATE pin will be discharged to GND at 80 mA rate VGS = 5V VGS VGATE-TH transition region nPGD Fault VGS < 5V VGS Status EN OFF VGS > 5V ON Figure 24. Voltages During Startup with VDS Fault Condition ENABLE The LM5060 Enable pin (EN) allows for remote On/Off control. The Enable pin on/off thresholds are CMOS compatible.
PAGE 16
LM5060 SNVS628F – OCTOBER 2009 – REVISED APRIL 2013 www.ti.com In addition to the programmable UVLO function, an internal Power-On-Reset (POR) monitors the voltage at the VIN pin and turns the MOSFET Off when VIN falls below typically 5.10V. up to 65V OK 1.6V (UVLOTH) 180 mV (hysterisis) UVLO Figure 26.
PAGE 17
LM5060 www.ti.com SNVS628F – OCTOBER 2009 – REVISED APRIL 2013 APPLICATION INFORMATION VDS FAULT DETECTION and SELECTING SENSE PIN RESISTOR RS The LM5060 monitors the VDS voltage of the external N-Channel MOSFET.
PAGE 18
LM5060 SNVS628F – OCTOBER 2009 – REVISED APRIL 2013 www.ti.com FAULT DETECTION DELAY TIME To allow the gate of the MOSFET adequate time to change, and to allow the MOSFET to conduct currents beyond the protection threshold for a brief period of time, a fault delay timer function is provided. This feature is important when drive loads which require a surge of current in excess of the normal ON current upon start up, or at any point in time, such as lamps and motors.
PAGE 19
LM5060 www.ti.com SNVS628F – OCTOBER 2009 – REVISED APRIL 2013 Since a single capacitor is used to set the delay time for multiple fault conditions, it is likely that some compromise will need to be made between a desired delay time and a practical delay time.
PAGE 20
LM5060 SNVS628F – OCTOBER 2009 – REVISED APRIL 2013 www.ti.com VIN VIN LM5060 R1 UVLOTH 1.60V UVLO UVLOBIAS 5.5 PA R2 OVP OVPTH 2.00V R3 Figure 29. UVLO and OVP Thresholds Set By R1, R2 and R3 The procedure to calculate the resistor values is as follows: 1. Select R1 based on current consumption allowed in the resistor divider, including UVLOBIAS, and consideration of noise sensitivity.
PAGE 21
LM5060 www.ti.com SNVS628F – OCTOBER 2009 – REVISED APRIL 2013 VIN VIN LM5060 R10 UVLO R8 UVLOTH 1.60V UVLOBIAS 5.5 PA R11 OVP OVPTH 2.00V R9 Figure 30. Programming the Thresholds with Resistors R8-R11 Choose the upper UVLO thresholds to ensure operation down to the lowest required operating input voltage (VINMIN). Select R11 based on resistive divider current consumption and noise sensitivity.
PAGE 22
LM5060 SNVS628F – OCTOBER 2009 – REVISED APRIL 2013 www.ti.com VIN LM5060 R4 nPGD VDS fault signal Status GND Figure 31. Circuitry at the nPGD Pin INPUT BYPASS CAPACITOR Some input capacitance from the VIN pin to the GND pin may be necessary to filter noise and voltage spikes from the VIN rail. If the current through Q1 in Figure 21 is very large a sudden shutdown of Q1 will cause an inductive kick across the line input and pc board trace inductance which could damage the LM5060.
PAGE 23
LM5060 www.ti.com SNVS628F – OCTOBER 2009 – REVISED APRIL 2013 VIN VOUT Q1 CL RL RS GATE SENSE OUT Fault OFF IGATE-FLT 80 mA GND LM5060 Figure 32. Discharge Path of Possible Load Capacitor In applications exposed to reverse polarity on the input and a large load capacitance on the output, a current limiting resistor in series with the OUT pin is required to protect the LM5060 OUT pin from reverse currents exceeding 25 mA. Figure 33 shows the resistor RO in the trace to the OUT pin.
PAGE 24
LM5060 SNVS628F – OCTOBER 2009 – REVISED APRIL 2013 www.ti.com When Q1 and Q2 are turned on, R1 does not cause any delay because the GATE pin is driven with a 24 µA current source. D6, Q3 and R2 protect Q2 from VGS damage in the event of reverse input polarity. Diodes D5 and D7 are only necessary if the output load is highly capacitive.
PAGE 25
LM5060 www.ti.com SNVS628F – OCTOBER 2009 – REVISED APRIL 2013 When calculating the minimum RO resistor required to limit the current into the OUT pin, the internal current sources of 8 µA and 16 µA may be neglected. The following formulas can be used to calculate the resistor value RO(MIN) which is necessary to keep the IO current to less than 4 mA. Case A for situations where VOUT > VIN and reverse polarity situation is present. See Figure 35.
PAGE 26
LM5060 SNVS628F – OCTOBER 2009 – REVISED APRIL 2013 www.ti.com Case D for situations where VOUT < VIN, while VOUT is negative and VIN is positive. See Figure 37. RO needs to be selected to protect the OUT pin from currents exceeding 25 mA. RO(MIN) = VOUT 25 mA (19) FAULT DETECTION WITH RS AND RO Figure 38 shows an example circuit where the OUT pin is protected against a reverse battery situation with a current limiting resistor RO.
PAGE 27
LM5060 www.ti.com SNVS628F – OCTOBER 2009 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision E (April 2013) to Revision F • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
PAGE 28
PACKAGE OPTION ADDENDUM www.ti.
PAGE 29
PACKAGE OPTION ADDENDUM www.ti.
PAGE 30
PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM5060MM/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5060MMX/NOPB VSSOP DGS 10 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5060Q1MM/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.
PAGE 31
PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5060MM/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0 LM5060MMX/NOPB VSSOP DGS 10 3500 367.0 367.0 35.0 LM5060Q1MM/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0 LM5060Q1MMX/NOPB VSSOP DGS 10 3500 367.0 367.0 35.
PAGE 32
PAGE 33
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.