LM5066 www.ti.
LM5066 SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 www.ti.com Typical Application Schematic Q2 VIN VOUT RS Q1 CIN D1 Z1 R4 GATE SENSE OUT DIODE FB VIN_K VDD VIN R1 COUT R5 UVLO/EN RPG R2 PGD OVLO LM5066 AGND GND R3 SMBA SDAO SDAI SCL VDD SMBus Interface 1 PF VDD ADR2 ADR1 ADR0 RETRY CL N/C N/C Auxillary ADC Input (0V ± 2.97V) VAUX VREF 1 PF PWR TIMER RPWR CTIMER Connection Diagram Solder exposed pad to ground.
LM5066 www.ti.com SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 PIN DESCRIPTIONS (continued) Pin No. Name Description 3 SENSE Current sense input 4 VIN_K Positive supply kelvin pin 5 VIN Positive supply input 6 N/C No connection 7 UVLO/EN Under-voltage lockout An external resistor divider from the system input voltage sets the under-voltage turn-on threshold. An internal 20 µA current source provides hysteresis. The enable threshold at the pin is nominally 2.48V.
LM5066 SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 Absolute Maximum Ratings www.ti.com (1) VIN, VIN_K, GATE, UVLO/EN, OUT, SENSE, PGD to GND (2) -0.3V to 100V OVLO, FB, TIMER, PWR to GND -0.3V to 7.0V SCL, SDAI, SDAO, CL, ADR0, ADR1, ADR2, VDD, VAUX, DIODE, RETRY to GND -0.3V to 6.0V SENSE to VIN_K, VIN to VIN_K, AGND to GND -0.3V to +0.
LM5066 www.ti.com SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 Electrical Characteristics Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C unless otherwise stated. Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
LM5066 SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 www.ti.com Electrical Characteristics (continued) Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C unless otherwise stated. Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
LM5066 www.ti.com SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 Electrical Characteristics (continued) Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C unless otherwise stated. Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
LM5066 SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 www.ti.com Typical Performance Characteristics Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 48V. All graphs show junction temperature. VIN Pin Current Sense Pin Current (Enabled) 7.5 SENSE PIN CURRENT (ENABLED) ( A) VIN INPUT CURRENT (mA) 8.0 VIN= 80V 7.0 VIN= 48V 6.5 6.0 5.5 VIN= 10V 5.
LM5066 www.ti.com SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 Typical Performance Characteristics (continued) Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 48V. All graphs show junction temperature. UVLO Hysteresis Current FB Threshold 2.48 FB THRESHOLD (V) UVLO HYSTERESIS CURRENT ( A) 20.8 20.7 20.6 VIN = 10V to 80V 20.5 2.46 2.44 2.42 20.
LM5066 SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 48V. All graphs show junction temperature. PIN Measurement Accuracy (VIN - SENSE = 50 mV) 0.5 1.0 0.4 0.8 0.3 0.6 PIN ERROR (% OF FSR) IIN ERROR ( % OF FSR) IIN Measurement Accuracy (VIN - SENSE = 50 mV) 0.2 0.1 0.0 -0.1 -0.2 -0.3 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.4 -0.8 -0.5 -1.
LM5066 www.ti.com SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 Typical Performance Characteristics (continued) Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 48V. All graphs show junction temperature. Current Limit Event (CL = VDD) 2 ms/DIV Circuit Breaker Event (CL = VDD) 500 µs/DIV VTIMER (2V/Div) VTIMER (2V/Div) VGATE (20V/Div) VGATE (20V/Div) VOUT (20V/Div) VOUT (20V/Div) ILOAD (4A/Div) CL = 8.6A CB = 1.
LM5066 SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 www.ti.com LM5066 20 PA VDD REG VDD PGD FB OUT VIN VIN_K SENSE BLOCK DIAGRAM 2.46V UV OV 12 bit ADC S/ H Diode Temp Sense SMBUS INTERFACE 20 PA VDS GATE 4.2 mA 115 mA GATE CONTROL 16.5V OUT Current Limit/ Power Limit Control Power Limit Threshold 48/96/193 mV Snapshot Circuit Breaker Threshold MEASUREMENT/ FAULT REGISTORS SDAO IDS Current Limit Sense VAUX SCL SDAI CHARGE PUMP 26/50 mV Current Limit Threshold 2.
LM5066 www.ti.com SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 FUNCTIONAL DESCRIPTION The inline protection functionality of the LM5066 is designed to control the in-rush current to the load upon insertion of a circuit card into a live backplane or other “hot” power source, thereby limiting the voltage sag on the backplane’s supply voltage, and the dV/dt of the voltage applied to the load. The effects on other circuits in the system are minimized by preventing possible unintended resets.
LM5066 SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 www.ti.com and transients at VIN to settle before Q1 is enabled. The insertion time ends when the TIMER pin voltage reaches 3.9V. CT is then quickly discharged by an internal 1.5 mA pull-down current. The GATE pin then switches on Q1 when VIN exceeds the UVLO threshold. If VIN is above the UVLO threshold at the end of the insertion time, Q1 the GATE pin charge pump sources 20 µA to charge the gate capacitance of Q1.
LM5066 www.ti.com SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 During the insertion time (t1 in Figure 2) the GATE pin is held low by a 4.2 mA pull-down current. This maintains Q1 in the off-state until the end of t1, regardless of the voltage at VIN or UVLO. Following the insertion time, during t2 in Figure 2 the gate voltage of Q1 is modulated to keep the current or power dissipation level from exceeding the programmed levels.
LM5066 SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 www.ti.com Fault Timer & Restart When the current limit or power limit threshold is reached during turn-on, or as a result of a fault condition, the gate-to-source voltage of Q1 is modulated to regulate the load current and power dissipation in Q1. When either limiting function is active, a 75 µA fault timer current source charges the external capacitor (CT) at the TIMER pin as shown in Figure 2 (Fault Timeout Period).
LM5066 www.ti.com SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 Under-Voltage Lockout (UVLO) The series pass MOSFET (Q1) is enabled when the input supply voltage (VIN) is within the operating range defined by the programmable under-voltage lockout (UVLO) and over-voltage lockout (OVLO) levels. Typically the UVLO level at VIN is set with a resistor divider (R1-R3) as shown in Figure 5.
LM5066 SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 www.ti.com voltage at the FB pin is below its threshold, the 20 µA current source at FB is disabled. As the output voltage increases, taking FB above its threshold, the current source is enabled, sourcing current out of the pin, raising the voltage at FB to provide threshold hysteresis. The PGD output is forced low when either the UVLO/EN pin is below its threshold or the OVLO pin is above its threshold.
LM5066 www.ti.com SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 The SMBus address of the LM5066 is captured based on the states of the ADR0, ADR1, and ADR2 pins (GND, NC, VDD) during turn on and is latched into a volatile register once VDD has exceeded its POR threshold of 4.1V. Reassigning or postponing the address capture is accomplished by holding the VREF pin to ground. Pulling the VREF pin low will also reset the logic and erase the volatile memory of the LM5066.
LM5066 SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 www.ti.com APPLICATION INFORMATION MMBT3904 Q2 RS 3 mÖ VIN VOUT IPB027N10N3 G Q1 Z1 5.0SMDJ60A GATE SENSE R4 150 kÖ OUT DIODE VIN_K R1 191 kÖ FB VDD VIN RPG UVLO/EN R2 7.5 kÖ R3 8.66 kÖ COUT D1 B380-13-F R5 10 kÖ 100 kÖ PGD OVLO AGND LM5066 GND ADR2 N/C ADR1 N/C ADR0 N/C PMBus Address = 40h Continuous Retry 50 mV Current Limit RETRY CL SMBA SDAO SDAI VAUX SCL VDD VREF 1 PF 1 PF PWR Auxillary ADC Input (0V ± 2.
LM5066 www.ti.com SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 Refer to Programming Guide section: After all hardware design is complete, refer to the programming guide for a step by step procedure regarding software.
LM5066 SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 www.ti.com HIGH CURRENT PATH FROM SYSTEM INPUT VOLTAGE TO DRAIN OF SENSE RESISTOR MOSFET Q1 RS VIN VIN_K SENSE Figure 7. Sense Resistor Connections POWER LIMIT THRESHOLD The LM5066 determines the power dissipation in the external MOSFET (Q1) by monitoring the drain current (the current in RS) and the VDS of Q1 (SENSE to OUT pins).
LM5066 www.ti.com SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 (4) where CL is the load capacitance. For example, if VIN = 48V, CL = 200 µF, and ILIM = 5A, tON calculates to 12 ms. The maximum instantaneous power dissipated in the MOSFET is 12W. This calculation assumes the time from t1 to t2 in Figure 9(a) is small compared to tON, the load does not draw any current until after the output voltage has reached its final value, and PGD switches high (Figure 8A).
LM5066 SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 www.ti.com VIN VIN VDS VDS Drain Current ILIM Drain Current ILIM IP 0 0 VGATE VGATE Gate-to-Source Voltage VGSL VGSL VTH VTH t ON 0 0 t3 t1 t2 a) Current Limit Only t ON 0 0 b) Power Limit and Current Limit Figure 9. MOSFET Power Up Waveforms TIMER CAPACITOR, CT The TIMER pin capacitor (CT) sets the timing for the insertion time delay, fault timeout period, and the restart timing of the LM5066.
LM5066 www.ti.com SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 For example, if CT = 0.8 µF, tRESTART = 7.9 seconds. At the end of the restart time, Q1 is switched on. If the fault is still present, the fault timeout and restart sequence repeats. The on-time duty cycle of Q1 is approximately 0.5% in this mode. UVLO, OVLO By programming the UVLO and OVLO thresholds the LM5066 enables the series pass device (Q1) when the input supply voltage (VIN) is within the desired operational range.
LM5066 SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 www.ti.com The lower OVLO threshold calculates to 55.6V, and the OVLO hysteresis is 4.4V. Note that the OVLO hysteresis is always slightly greater than the UVLO hysteresis in this configuration.
LM5066 www.ti.com SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 (28) (29) (30) VUV(HYS) = R1 x 20 µA (31) (32) Option C: The minimum UVLO level is obtained by connecting the UVLO/EN pin to VIN as shown in Figure 12. Q1 is switched on when the VIN voltage reaches the POREN threshold (≊8.6V). The OVLO thresholds are set using R3, R4. Their values are calculated using the procedure in Option B. VIN VIN 20 PA 10k UVLO/EN 2.48V R3 2.
LM5066 SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 www.ti.com As an example, assume the application requires the following thresholds: VPGDH = 40V, and VPGDL = 38V. Therefore VPGD(HYS) = 2V. The resistor values are: R4 = 100 kΩ, R5 = 6.55 kΩ When the R4 and R5 resistor values are known, the threshold voltages and hysteresis are calculated from the following: VPGDH = 2.46V x (R4 + R5) R5 VPGDL = 2.46V + [R4 x (2.46V - 20 PA)] R5 VPGD(HYS) = R4 x 20 PA (35) Q1 VOUT GATE LM5066 OUT R4 2.
LM5066 www.ti.com SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 SYSTEM CONSIDERATIONS A) Continued proper operation of the LM5066 hot swap circuit requires a voltage clamping element present on the supply side of the connector into which the hot swap circuit is plugged in. A TVS is ideal, as depicted in Figure 16. The TVS is necessary to absorb the voltage transient generated whenever the hot swap circuit shuts off the load current.
LM5066 SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 www.ti.com - The AGND and GND connections should be connected at the pins of the device.The ground connections for the various components around the LM5066 should be connected directly to each other, and to the LM5066’s GND and AGND pin connection, and then connected to the system ground at one point. Do not connect the various component grounds to each other through the high current ground line.
LM5066 www.ti.com SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 PMBUS™ COMMAND SUPPORT The device features an SMBus interface that allows the use of PMBus commands to set warn levels, error masks, and get telemetry on VIN, VOUT, IIN, VAUX, and PIN. The supported PMBus commands are shown in Table 1. Table 1. Supported PMBus Commands Code Name Function R/W Number Of Data Bytes Default Value 80h 01h OPERATION Retrieves or stores the operation status.
LM5066 SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 www.ti.com Table 1. Supported PMBus Commands (continued) Number Of Data Bytes Default Value Code Name Function R/W D6h MFR_SPECIFIC_06 CLEAR_PIN_PEAK Resets the contents of the peak input power register to zero. Send Byte 0 D7h MFR_SPECIFIC_07 GATE_MASK Allows the user to disable MOSFET gate shutdown for various fault conditions. R/W 1 0000h D8h MFR_SPECIFIC_08 ALERT_MASK Retrieves or stores user SMBA fault mask.
LM5066 www.ti.com SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 STANDARD PMBUS COMMANDS OPERATION (01h) The OPERATION command is a standard PMBus command that controls the MOSFET switch. This command may be used to switch the MOSFET ON and OFF under host control. It is also used to re-enable the MOSFET after a fault triggered shutdown. Writing an OFF command, followed by an ON command, will clear all faults and re-enable the device.
LM5066 SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 www.ti.com Table 5. OT_FAULT_LIMIT Register Value Meaning Default 0h – 0FFEh Overtemperature Fault threshold value 0960h (150°C) 0FFFh Overtemperature Fault detection disabled n/a OT_WARN_LIMIT (51h) The OT_WARN_LIMIT command is a standard PMBus command that allows configuring or reading the threshold for the overtemperature warning detection. Reading and writing to this register should use the coefficients shown in Table 41.
LM5066 www.ti.com SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 STATUS_BYTE (78h) The STATUS BYTE is a standard PMBus command that returns the value of a number of flags indicating the state of the LM5066. Accesses to this command should use the PMBus read byte protocol. To clear bits in this register, the underlying fault should be removed on the system and a CLEAR_FAULTS command issued. Table 9.
LM5066 SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 www.ti.com STATUS_VOUT (7Ah) The STATUS_VOUT command is a standard PMBus command that returns the value of the VOUT UV Warn flag. Accesses to this command should use the PMBus read byte protocol. To clear bits in this register, the underlying fault should be cleared and a CLEAR_FAULTS command issued. Table 11.
LM5066 www.ti.com SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 STATUS_CML (7Eh) The STATUS_CML is a standard PMBus command that returns the value of a number of flags related to communication faults. Accesses to this command should use the PMBus read byte protocol. To clear bits in this register, a CLEAR_FAULTS command should be issued. Table 14.
LM5066 SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 www.ti.com READ_VOUT (8Bh) The READ_VOUT command is a standard PMBus command that returns the 12-bit measured value of the output voltage. Reading this register should use the coefficients shown in Table 41. Accesses to this command should use the PMBus read word protocol. This value is also used internally for the VOUT Under Voltage Warning detection. Table 17.
LM5066 www.ti.com SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 MFR_REVISION (9Bh) The MFR_REVISION command is a standard PMBus command that returns the revision level of the part. To read the MFR_REVISION, use the PMBus block read protocol. Table 21.
LM5066 SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 www.ti.com MANUFACTURER SPECIFIC PMBUS™ COMMANDS MFR_SPECIFIC_00: READ_VAUX (D0h) The READ_VAUX command will report the 12-bit ADC measured auxiliary voltage. Voltages greater than or equal to 2.97V to ground will be reported at plus full scale (0FFFh). Voltages less than or equal to 0V referenced to ground will be reported as 0 (0000h). To read data from the READ_VAUX command, use the PMBus Read Word protocol. Table 22.
LM5066 www.ti.com SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 MFR_SPECIFIC_04: MFR_PIN_OP_WARN_LIMIT (D4h) The MFR_PIN_OP_WARN_LIMIT PMBus command sets the input over-power warning threshold. In the event that the input power rises above the value set in this register, the PIN Over-power flags are set in the respective registers and the SMBA is asserted. To access the MFR_PIN_OP_WARN_LIMIT register, use the PMBus Read/Write Word protocol.
LM5066 SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 www.ti.com MFR_SPECIFIC_08: ALERT_MASK (D8h) The ALERT_MASK command is used to mask the SMBA when a specific fault or warning has occurred. Each bit corresponds to one of the 14 different analog and digital faults or warnings that would normally result in an SMBA being asserted. When the corresponding bit is high, that condition will not cause the SMBA to be asserted.
LM5066 www.ti.com SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 Table 30. DEVICE_SETUP Byte Format (continued) Bit Name 0 Unused Meaning In order to configure the Current Limit Setting via this register, it is necessary to set the Current Limit Configuration bit (2) to 1 to enable the register to control the current limit function and the Current Limit Setting bit (4) to select the desired setting. If the Current Limit Configuration bit is not set, the pin setting will be used.
LM5066 SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 www.ti.com Table 32. SAMPLES_FOR_AVG Register (continued) AVGN N = 2AVGN Averaging/Register Update Period (ms) 0011 8 8 0100 16 16 0101 32 32 0110 64 64 0111 128 128 1000 256 256 1001 512 512 1010 1024 1024 1011 2048 2048 1100 4096 4096 Note that a change in the SAMPLES_FOR_AVG register will not be reflected in the average telemetry measurements until the present averaging interval has completed.
LM5066 www.ti.com SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 Table 36. READ_AVG_IIN Register Value Meaning Default 0h – 0FFFh Average of measured values for current sense voltage 0000h MFR_SPECIFIC_15: READ_AVG_PIN The READ_AVG_PIN command will report the upper 12-bits of the average VIN x IIN product as measured by the 12-bit ADC. You will read the default value (0000h) or previous data when the average data is not ready. This data is read with the PMBus Read Word protocol.
LM5066 SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 www.ti.com MFR_SPECIFIC_18: AVG_BLOCK_READ (E2h) The AVG_BLOCK_READ command concatenates the DIAGNOSTIC_WORD with input and output average telemetry information (IIN, VOUT, VIN, PIN) as well as temperature to capture all of the operating information of the part in a single PMBus transaction. The block is 12 bytes long with telemetry information being sent out in the same manner as if an individual READ_AVG_XXX command had been issued (shown below).
DIODE +48 VIN_K IIN + Copyright © 2011–2013, Texas Instruments Incorporated Product Folder Links: LM5066 READ_AVG_VOUT DDh READ_VOUT 8Bh VAUX D0h PEAK-HOLD CLEAR_PIN_PEAK D6h READ_PIN_PEAK D5h AVERAGED DATA READ_AVG_PIN DFh READ_PIN D2h CMP CMP CMP CMP CMP CMP WARNING SYSTEM OT_WARNING_LIMIT STATUS_TEMPERATURE 7Dh VOUT_UV WARNING STATUS_VOUT 7Ah PIN_OP WARNING STATUS_INPUT 7Ch IIN_OC WARNING STATUS_INPUT 7Ch VIN_UV WARNING STATUS_INPUT 7Ch CMP CMP VIN_OV WARNING STATUS_INPUT 7Ch
LM5066 SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 www.ti.com READING AND WRITING TELEMETRY DATA AND WARNING THRESHOLDS All measured telemetry data and user programmed warning thresholds are communicated in 12-bit two’s compliment binary numbers read/written in 2 byte increments conforming to the Direct format as described in section 8.3.3 of the PMBus Power System Management Protocol Specification 1.1 (Part II).
LM5066 www.ti.com SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 Table 42.
LM5066 SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 www.ti.com READING CURRENT The current register actually displays a value equivalent to a voltage across the user specified sense resistor, RS. The coefficients enable the data output to be converted to amps. The values shown in the example are based on having the device programmed for a 26 mV current limit threshold (CL = VDD). In the 26mV range, the LSB value is 9.3 µV and the full scale range is 38.0 mV.
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LM5066 SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 www.ti.com DETERMINING TELEMETRY COEFFICIENTS EMPIRICALLY WITH LINEAR FIT The coefficients for telemetry measurements and warning thresholds presented in Table 41 are adequate for the majority of applications. Current and power coefficients must be calculated per application as they are dependent on the value of the sense resistor, RS, used. Table 42 provides the equations necessary for calculating the current and power coefficients for the general case.
LM5066 www.ti.com SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 WRITING TELEMETRY DATA There are several locations that will require writing data if their optional usage is desired. Use the same coefficients previously calculated for your application, and apply them using this method as prescribed by the PMBus revision section 7.2.
LM5066 SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 www.ti.com PMBUS™ ADDRESS LINES (ADR0, ADR1, ADR2) The three address lines are to be set high (connect to VDD), low (connect to GND), or open to select one of 27 addresses for communicating with the LM5066. Table 44 depicts 7-bit addresses (eighth bit is read/write bit): Table 44.
LM5066 www.ti.com SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 SMBUS COMMUNICATIONS TIMING REQUIREMENTS tR SCL tF tLOW VIH VIL tHIGH tHD;DAT tHD;STA tSU;STA tSU;STO tSU;DAT SDA VIH VIL tBUF P S S P Figure 19. SMBus Timing Diagram Table 45. SMBus Timing Definition Symbol (1) (2) (3) (4) (5) Limits Parameter Min Max 400 Units FSMB SMBus Operating Frequency 10 TBUF Bus free time between Stop and Start Condition 1.3 µs THD:STA Hold time after (Repeated) Start Condition.
LM5066 SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 www.ti.com SMBA RESPONSE The SMBA effectively has two masks: 1. The Alert Mask Register at D8h, and 2. The ARA Automatic Mask. The ARA Automatic Mask is a mask that is set in response to a successful ARA read. An ARA read operation returns the PMBus address of the lowest addressed part on the bus that has its SMBA asserted. A successful ARA read means that THIS part was the one that returned its address.
LM5066 www.ti.com SNVS655G – JUNE 2011 – REVISED FEBRUARY 2013 REVISION HISTORY Changes from Revision F (February 2013) to Revision G • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.com 15-Sep-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PACKAGE MATERIALS INFORMATION www.ti.com 30-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LM5066PMHE/NOPB HTSSOP PWP 28 250 178.0 16.4 LM5066PMHX/NOPB HTSSOP PWP 28 2500 330.0 16.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.8 10.2 1.6 8.0 16.0 Q1 6.8 10.2 1.6 8.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 30-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5066PMHE/NOPB HTSSOP PWP LM5066PMHX/NOPB HTSSOP PWP 28 250 213.0 191.0 55.0 28 2500 367.0 367.0 38.
MECHANICAL DATA PWP0028A MXA28A (Rev D) www.ti.
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