Datasheet

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GND

VCC

VEE

SENSETIMER

UVLO/EN

GATE

OVLO

PGD

LM5067

PWR

OUT

LOAD

- 48V

LM5067

www.ti.com

SNVS532C –OCTOBER 2007–REVISED MARCH 2013

Negative Hot Swap / Inrush Current Controller with Power Limiting

Check for Samples: LM5067

FEATURES

DESCRIPTION

The LM5067 negative hot swap controller provides

• Wide operating range: -9V to -80V

intelligent control of the power supply connections

• In-rush current limit for safe board insertion

during insertion and removal of circuit cards from a

into live power sources

live system backplane or other “hot” power sources.

• Programmable maximum power dissipation in

The LM5067 provides in-rush current control to limit

system voltage droop and transients. The current limit

the external pass device

and power dissipation in the external series pass N-

• Adjustable current limit

Channel MOSFET are programmable, ensuring

• Circuit breaker function for severe over-

operation within the Safe Operating Area (SOA). In

current events

addition, the LM5067 provides circuit protection by

monitoring for over-current and over-voltage

• Adjustable under-voltage lockout (UVLO) and

conditions. The POWER GOOD output indicates

hysteresis

when the output voltage is close to the input voltage.

• Adjustable over-voltage lockout (OVLO) and

The input under-voltage and over-voltage lockout

hysteresis

levels and hysteresis are programmable, as well as

• Initial insertion timer allows ringing and

the fault detection time. The LM5067-1 latches off

transients to subside after system connection

after a fault detection, while the LM5067-2

automatically attempts restarts at a fixed duty cycle.

• Programmable fault timer avoids nuisance

The LM5067 is available in a 10-pin VSSOP package

trips

and a 14-pin SOIC package.

• Active high open drain POWER GOOD output

• Available in latched fault and automatic restart

APPLICATIONS

versions

• Server Backplane Systems

• In-Rush Current Limiting

PACKAGES

• Solid State Circuit Breaker

• VSSOP-10

• Transient Voltage Protector

• SOIC-14 (Latched Fault Version)

• Solid State Relay

• Under-voltage Lock-out

• Power Good Detector/Indicator

Typical Application

Figure 1. Negative Power Bus In-Rush and Fault Protection

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (35 pages)

PAGE 1
LM5067 www.ti.com SNVS532C – OCTOBER 2007 – REVISED MARCH 2013 Negative Hot Swap / Inrush Current Controller with Power Limiting Check for Samples: LM5067 FEATURES DESCRIPTION • • The LM5067 negative hot swap controller provides intelligent control of the power supply connections during insertion and removal of circuit cards from a live system backplane or other “hot” power sources. The LM5067 provides in-rush current control to limit system voltage droop and transients.
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LM5067 SNVS532C – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com Connection Diagram NOTE: N/C Pins are internally not connected to anything. VCC 1 10 UVLO/EN 2 9 OUT OVLO 3 8 GATE PWR 4 7 VEE 5 6 PGD VCC 1 14 PGD N/C 2 13 N/C UVLO/EN 3 12 OUT SENSE OVLO 4 11 N/C TIMER PWR 5 10 GATE VEE 6 9 SENSE N/C 7 8 TIMER Figure 2. Top View 10-Lead VSSOP Figure 3. Top View 14-Lead SOIC PIN DESCRIPTIONS Pin No.
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LM5067 www.ti.com SNVS532C – OCTOBER 2007 – REVISED MARCH 2013 Absolute Maximum Ratings (1) Current into VCC (100 µs pulse) 100 mA OUT, PGD to VEE -0.3V to 100V UVLO, OVLO to VEE -0.3V to 17V SENSE to VEE -0.3V to +0.3V ESD Rating, Human Body Model (2) 2kV Storage Temperature -65°C to +150°C Junction Temperature +150°C (1) (2) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
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LM5067 SNVS532C – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com Electrical Characteristics (continued) Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
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LM5067 www.ti.com SNVS532C – OCTOBER 2007 – REVISED MARCH 2013 Electrical Characteristics (continued) Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
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LM5067 SNVS532C – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics Unless otherwise specified the following conditions apply: TJ = 25°C. 6 ICC vs. Operating Voltage - Disabled ICC vs. Operating Voltage - Enabled Operating Voltage vs. ICC SENSE Pin Current vs. System Voltage OUT Pin Current vs. System Voltage GATE Source Current vs.
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LM5067 www.ti.com SNVS532C – OCTOBER 2007 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Unless otherwise specified the following conditions apply: TJ = 25°C. GATE Pull-Down Current, Circuit Breaker vs. GATE Voltage PGD Low Voltage vs. Sink Current MOSFET Power Dissipation Limit vs. RPWR and RS UVLO & OVLO Hysteresis Current vs. Temperature UVLO, OVLO Threshold Voltage vs. Temperature VZ Operating Voltage vs.
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LM5067 SNVS532C – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) POWER LIMIT THRESHOLD (mV) Unless otherwise specified the following conditions apply: TJ = 25°C. Current Limit Threshold vs. Temperature Circuit Breaker Threshold vs. Temperature Power Limit Threshold vs. Temperature Gate Source Current vs.
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LM5067 www.ti.com SNVS532C – OCTOBER 2007 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Unless otherwise specified the following conditions apply: TJ = 25°C. POREN Threshold vs. Temperature TIMER Pin Thresholds vs. Temperature TIMER PIN THRESHOLDS (V) 4.1 Upper Restart Threshold 3.9 1.4 Lower Restart Threshold 1.2 0.4 Lower Reset Threshold 0.2 -40 -20 0 20 40 60 80 100 125 JUNCTION TEMPERATURE (°C) TIMER Pin Fault Detection Current vs.
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LM5067 SNVS532C – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com BLOCK DIAGRAM VCC Vcc VZ LM5067 13V Vcc Vee 50 mV VEE ID 52 PA Current Limit Threshold Gate Control SENSE GATE 2.2 mA 110 mA 1 M: Current Limit Power Limit Control Power Limit Threshold VDS OUT Vee PGD 1.23V/ 2.5V Vee 6 PA Insertion Timer 23 PA PWR 85 PA Fault Timer 22 PA TIMER AND GATE LOGIC CONTROL TIMER OVLO 2.5V 2.5V 2.5 PA Fault Discharge Vee 1.55 mA End Insertion Time Vee 4.0V UVLO/EN 1.25V Vee 22 PA 0.
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LM5067 www.ti.com SNVS532C – OCTOBER 2007 – REVISED MARCH 2013 FUNCTIONAL DESCRIPTION The LM5067 is designed to control the in-rush current to the load upon insertion of a circuit card into a live backplane or other “hot” power source, thereby limiting the voltage sag on the backplane’s supply voltage, and the dV/dt of the voltage applied to the load. Effects on other circuits in the system are minimized, preventing possible unintended resets.
PAGE 12
LM5067 SNVS532C – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com The GATE pin switches on Q1 when VSYS exceeds the UVLO threshold (UVLO pin >2.5V above VEE). If VSYS exceeds the UVLO threshold at the end of the insertion time, Q1 is switched on at that time. The GATE pin sources 52 µA to charge Q1’s gate capacitance. The maximum gate-to-source voltage of Q1 is limited by the LM5067’s operating voltage (VZ) to approximately 13V.
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LM5067 www.ti.com SNVS532C – OCTOBER 2007 – REVISED MARCH 2013 Gate Control The external N-channel MOSFET is turned on when the GATE pin sources 52 µA to enhance the gate. During normal operation (t3 in Figure 6) Q1’s gate is held charged to approximately 13V above VEE, typically within 20 mV of the voltage at VCC. If the maximum VGS rating of Q1 is less than 13V, a lower voltage external zener diode must be added between the GATE and SENSE pins.
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LM5067 SNVS532C – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com Circuit Breaker If the load current increases rapidly (e.g., the load is short-circuited) the current in the sense resistor (RS) may exceed the current limit threshold before the current limit control loop is able to respond. If the current exceeds approximately twice the current limit threshold (100 mV/RS), Q1’s gate is quickly pulled down by the 110 mA pulldown current at the GATE pin, and a Fault Timeout Period begins.
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LM5067 www.ti.com SNVS532C – OCTOBER 2007 – REVISED MARCH 2013 Fault Detection I LIMIT Load Current 52 PA Gate Charge 2.2 mA pulldown GATE Pin 2.5 PA 4V 85 PA TIMER Pin 1.25V 1 2 3 7 8 0.3V t RESTART Fault Timeout Period All voltages are with respect to VEE Figure 9.
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LM5067 SNVS532C – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com APPLICATION INFORMATION (REFER TO FIGURE 4) RIN, CIN The LM5067 operating voltage is determined by an internal 13V shunt regulator which receives its current from the system voltage via RIN. When the system voltage exceeds 13V, the LM5067 operating voltage (VCC – VEE) is between VEE and VEE+13V.
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LM5067 www.ti.com SNVS532C – OCTOBER 2007 – REVISED MARCH 2013 RPWR = 1.42 x 105 x RS x PFET(LIM) where • • PFET(LIM) is the desired power limit threshold for Q1 RS is the current sense resistor described in the Current Limit section (3) For example, if RS is 10 mΩ, and the desired power limit threshold is 60W, RPWR calculates to 85.2 kΩ. If Q1’s power dissipation reaches the power limit threshold, Q1’s gate is modulated to control the load current, keeping Q1’s power from exceeding the threshold.
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LM5067 SNVS532C – OCTOBER 2007 – REVISED MARCH 2013 • www.ti.com RL is the load resistance and VSYS is the absolute value of the system input voltage (5) The Fault Timeout Period must be set longer than tON to prevent a fault shutdown before the turn-on sequence is complete. GND R IN C IN RL VEE VCC LM5067 CL VEE SENSE GATE OUT VSYS RS Q1 Figure 12.
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LM5067 www.ti.com • • SNVS532C – OCTOBER 2007 – REVISED MARCH 2013 The SOA (Safe Operating Area) chart of the device, and the thermal properties, should be used to determine the maximum power dissipation threshold set by the RPWR resistor. The programmed maximum power dissipation should have a reasonable margin from the maximum power defined by the FET's SOA chart if the LM5067-2 is used since the FET will be repeatedly stressed during fault restart cycles.
PAGE 20
LM5067 SNVS532C – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com For example, if CT = 0.33 µF, tRESTART = 3.1 seconds. At the end of the restart time, Q1 is switched on. If the fault is still present, the fault timeout and restart sequence repeats. The on-time duty cycle of Q1 is approximately 0.5% in this mode. UVLO, OVLO By programming the UVLO and OVLO thresholds the LM5067 enables the series pass device (Q1) when the input supply voltage (VSYS) is within the desired operational range.
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LM5067 www.ti.com SNVS532C – OCTOBER 2007 – REVISED MARCH 2013 As an example, assume the application requires the following thresholds: VUVH = -36V, VUVL = -32V, VOVH = 60V. 36V ± 32V 4V R1 = = 182 k: = 22 PA 22 PA R3 = 2.5V x 182 k: x 32V = 8.23 k: 60V x (32V - 2.5V) R2 = 2.5V x 182 k: - 8.23 k: = 7.19 k: (32V - 2.5V) (12) The lower OVLO threshold calculates to -55.8V, and the OVLO hysteresis is 4.2V.
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LM5067 SNVS532C – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com To Load GND RIN CIN VEE R1 VCC UVLO/EN 2.50V Vee R2 Vee LM5067 22 PA R3 TIMER AND GATE LOGIC CONTROL 2.50V OVLO Vee R4 VEE 22 PA VSYS Figure 15. Programming the Four Thresholds The four resistor values are calculated as follows: • Determine the upper UVLO threshold (VUVH) to enable Q1, and the lower UVLO threshold (VUVL) to disable Q1. VUV(HYS) VUVH - VUVL R1 = R2 = • 22 PA = 22 PA 2.5V x R1 (VUVL - 2.
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LM5067 www.ti.com SNVS532C – OCTOBER 2007 – REVISED MARCH 2013 VUVH = 2.5V + [R1 x (2.5V + 22 PA)] R2 VUVL = 2.5V x (R1 + R2) R2 VUV(HYS) = R1 x 22 PA VOVH = 2.5V x (R3 + R4) R4 VOVL = 2.5V + [R3 x (2.5V - 22 PA)] R4 VOV(HYS) = R3 x 22 PA (16) NOTE Ensure the voltages at the UVLO and OVLO pins do not exceed the Absolute Maximum ratings for those pins when the system voltage is at maximum. Option C: The minimum UVLO level is obtained by connecting the UVLO pin to VCC as shown in Figure 16.
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LM5067 SNVS532C – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com SHUTDOWN / ENABLE CONTROL Figure 17 shows how to use the UVLO/EN pin for remote shutdown and enable control. Taking the UVLO/EN pin below its 2.5V threshold (with respect to VEE) shuts off the load current. Upon releasing the UVLO/EN pin the LM5067 switches on the load current with in-rush current and power limiting. In Figure 18 the OVLO pin is used for remote shutdown and enable control.
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LM5067 www.ti.com SNVS532C – OCTOBER 2007 – REVISED MARCH 2013 VSYS LM5067 Power Good PGD VEE R PG2 PGD C PG VSYS a ) Delay Rising Edge Only R PG1 R PG1 R PG LM5067 VPGD VPGD VPGD VEE b) Long delay at rising edge , Short delay at falling edge Power Good LM 5067 Power Good PGD R PG2 C PG VSYS C PG VEE c ) Short Delay at Rising Edge and Long Delay at Falling Edge, or Equal Delays Figure 20.
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LM5067 SNVS532C – OCTOBER 2007 – REVISED MARCH 2013 • www.ti.com If power dissipation within the LM5067 is high, an exposed copper pad should be provided beneath the package, and that pad should be connected to exposed copper on the board’s other side with as many vias as possible. See Thermal Considerations. GND C IN R IN VSYS R1 R2 R3 To Load LM5067 PGD VCC OUT UVLO OVLO GATE PWR SENSE VEE TIMER Q1 RS PLUG - IN CARD CARD EDGE CONNECTOR Figure 21.
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LM5067 www.ti.com SNVS532C – OCTOBER 2007 – REVISED MARCH 2013 PLUG - IN BOARD GND R IN LIVE BACKPLANE CIN VCC CL PGD LM5067 VEE SENSE GATE OUT - 48V VSYS RS Inductive Load Q1 VOUT Figure 22.
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LM5067 SNVS532C – OCTOBER 2007 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision B (March 2013) to Revision C • 28 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM5067MM-1/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5067MM-2 VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5067MM-2/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5067MM-1/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0 LM5067MM-2 VSSOP DGS 10 1000 210.0 185.0 35.0 LM5067MM-2/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0 LM5067MMX-1/NOPB VSSOP DGS 10 3500 367.0 367.0 35.0 LM5067MMX-2/NOPB VSSOP DGS 10 3500 367.0 367.0 35.0 LM5067MWX-1/NOPB SOIC NPA 14 1000 367.
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MECHANICAL DATA NPA0014B www.ti.
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