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SYS

OUT

Power

Good

UVLO

OVLO

PWR

GNDTIMER

PGD

OUT

VIN SENSE GATE

LM5069

www.ti.com

SNVS452D –SEPTEMBER 2006–REVISED MAY 2013

LM5069 Positive High Voltage Hot Swap / Inrush Current Controller with Power Limiting

Check for Samples: LM5069

FEATURES

APPLICATIONS

• Wide Operating Range: +9V to +80V

• Server Backplane Systems

• In-rush Current Limit for Safe Board Insertion • Base Station Power Distribution Systems

into Live Power Sources

• Solid State Circuit Breaker

• Programmable Maximum Power Dissipation in

• 24V/48V Industrial Systems

the External Pass Device

• Adjustable Current Limit PACKAGE

• Circuit Breaker Function for Severe Over-

• VSSOP-10

Current Events

DESCRIPTION

• Internal High Side Charge Pump and Gate

Driver for External N-channel MOSFET

The LM5069 positive hot swap controller provides

intelligent control of the power supply connections

• Adjustable Under-Voltage Lockout (UVLO) and

during insertion and removal of circuit cards from a

Hysteresis

live system backplane or other "hot" power sources.

• Adjustable Over-Voltage Lockout (OVLO) and

The LM5069 provides in-rush current control to limit

Hysteresis

system voltage droop and transients. The current limit

and power dissipation in the external series pass N-

• Initial Insertion Timer Allows Ringing and

Channel MOSFET are programmable, ensuring

Transients to Subside after System

operation within the Safe Operating Area (SOA). The

Connection

POWER GOOD output indicates when the output

• Programmable Fault Timer Avoids Nuisance

voltage is within 1.25V of the input voltage. The input

Trips

under-voltage and over-voltage lockout levels and

• Active High Open Drain POWER GOOD Output

hysteresis are programmable, as well as the initial

insertion delay time and fault detection time. The

• Available in Latched Fault and Automatic

LM5069-1 latches off after a fault detection, while the

Restart Versions

LM5069-2 automatically restarts at a fixed duty cycle.

The LM5069 is available in a 10 pin VSSOP package.

TYPICAL APPLICATION

Figure 1. Positive Power Supply Control

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (28 pages)

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LM5069 www.ti.
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LM5069 SNVS452D – SEPTEMBER 2006 – REVISED MAY 2013 www.ti.com CONNECTION DIAGRAM SENSE 1 10 GATE VIN OUT 2 9 UVLO 3 8 PGD OVLO 4 7 PWR GND 5 6 TIMER Figure 2. Top View 10-Lead VSSOP PIN DESCRIPTIONS Pin # Name Description Applications Information 1 SENSE Current sense input The voltage across the current sense resistor (RS) is measured from VIN to this pin. If the voltage across RS reaches 55mV the load current is limited and the fault timer activates.
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LM5069 www.ti.com SNVS452D – SEPTEMBER 2006 – REVISED MAY 2013 ABSOLUTE MAXIMUM RATINGS (1) (2) (3) VIN to GND -0.3V to 100V SENSE, OUT, PGD to GND GATE to GND -0.3V to 100V (3) -0.3V to 100V UVLO to GND -0.3V to 100V OVLO to GND -0.3V to 7V VIN to SENSE -0.3V to +0.3V ESD Rating (4) Human Body Model 2kV Storage Temperature -65°C to +150°C Junction Temperature +150°C (1) (2) (3) (4) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
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LM5069 SNVS452D – SEPTEMBER 2006 – REVISED MAY 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
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LM5069 www.ti.com SNVS452D – SEPTEMBER 2006 – REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 48V VIN Pin Input Current vs. VIN SENSE PIN INPUT CURRENT (PA) VIN PIN INPUT CURRENT (mA) 1.5 Enabled, UVLO = VIN 1.0 0.5 Disabled, UVLO = 0V 0 SENSE Pin Input Current 100 2.0 Disabled, UVLO = 0V 75 50 25 Enabled, UVLO = VIN 0 0 20 40 60 0 80 20 VIN VOLTAGE (V) Figure 4. OUT Pin Current GATE Pin Voltage vs.
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LM5069 SNVS452D – SEPTEMBER 2006 – REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 48V MOSFET Power Dissipation Limit vs. RPWR and RS 250 RS = 0.005: PFET (W) 160 RS = 0.1: RS = 0.01: 120 80 RS = 0.02: 40 RS = 0.
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LM5069 www.ti.com SNVS452D – SEPTEMBER 2006 – REVISED MAY 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 48V Current Limit Threshold vs. Temperature Circuit Breaker Threshold vs. Temperature 115 CIRCUIT BREAKER THRESHOLD (VOLTAGE ACROSS RS) (mV) CURRENT LIMIT THRESHOLD (VOLTAGE ACROSS RS) (mV) 57 56 55 54 53 -40 -20 0 20 40 60 80 110 105 100 95 90 85 -40 -20 100 125 40 60 80 Figure 16.
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LM5069 SNVS452D – SEPTEMBER 2006 – REVISED MAY 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 48V PGD Low Voltage vs. Temperature PGD OUTPUT LOW VOLTAGE (mV) 160 120 80 . 40 PGD Sink Current = 2 mA 0 -40 -20 0 20 40 60 80 100 125 JUNCTION TEMPERATURE (oC) Figure 21.
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LM5069 www.ti.com SNVS452D – SEPTEMBER 2006 – REVISED MAY 2013 BLOCK DIAGRAM LM5069 Charge Pump 55 mV ID VIN Current Limit Threshold SENSE 16 PA Gate Control GATE 2 mA 230 mA 1 M: OUT Current Limit/ Power Limit Control Power Limit Threshold VDS 12V OUT PGD 1.25V/ 2.5V 5.5 PA Insertion Timer 20 PA PWR 85 PA Fault Timer 21 PA TIMER AND GATE LOGIC CONTROL TIMER OVLO 2.5V 2.5V 1.5 mA End Insertion Time 2.5 PA Fault Discharge 4.0V UVLO 1.25V 21 PA GND 8.4/8.3V 0.
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LM5069 SNVS452D – SEPTEMBER 2006 – REVISED MAY 2013 www.ti.com FUNCTIONAL DESCRIPTION Q1 VSYS VOUT RS CIN CL R1 SENSE GATE UVLO OUT RPG LM5069 R2 OVLO TIMER R3 Power Good PGD GND PWR RPWR CT Figure 22.
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LM5069 www.ti.com SNVS452D – SEPTEMBER 2006 – REVISED MAY 2013 As the voltage at the OUT pin increases, the LM5069 monitors the drain current and power dissipation of MOSFET Q1. In-rush current limiting and/or power limiting circuits actively control the current delivered to the load. During the in-rush limiting interval (t2 in Figure 24) an internal 85 µA fault timer current source charges CT.
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LM5069 SNVS452D – SEPTEMBER 2006 – REVISED MAY 2013 www.ti.com If the in-rush limiting condition persists such that the TIMER pin reached 4V during t2, the GATE pin is then pulled low by the 2 mA pull-down current. The GATE pin is then held low until either a power up sequence is initiated (LM5069-1), or until the end of the restart sequence (LM5069-2). See the Fault Timer & Restart section.
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LM5069 www.ti.com SNVS452D – SEPTEMBER 2006 – REVISED MAY 2013 Fault Timer & Restart When the current limit or power limit threshold is reached during turn-on or as a result of a fault condition, the gate-to-source voltage of Q1 is modulated to regulate the load current and power dissipation. When either limiting function is activated, an 85 µA fault timer current source charges the external capacitor (CT) at the TIMER pin as shown in Figure 27 (Fault Timeout Period).
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LM5069 SNVS452D – SEPTEMBER 2006 – REVISED MAY 2013 www.ti.com Over-Voltage Lock-Out (OVLO) The series pass MOSFET (Q1) is enabled when the input supply voltage (VSYS) is within the operating range defined by the programmable under-voltage lockout (UVLO) and over-voltage lock-out (OVLO) levels. If VSYS raises the OVLO pin voltage above 2.5V Q1 is switched off by the 2 mA pull-down current at the GATE pin, denying power to the load. When the OVLO pin is above 2.
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LM5069 www.ti.com SNVS452D – SEPTEMBER 2006 – REVISED MAY 2013 HIGH CURRENT PATH FROM SYSTEM INPUT VOLTAGE TO MOSFET'S DRAIN SENSE RESISTOR RS SENSE VIN 3 10 9 8 4 LM5069 7 5 6 Figure 29. Sense Resistor Connections POWER LIMIT THRESHOLD The LM5069 determines the power dissipation in the external MOSFET (Q1) by monitoring the drain current (the current in RS), and the VDS of Q1 (SENSE to OUT pins).
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LM5069 SNVS452D – SEPTEMBER 2006 – REVISED MAY 2013 www.ti.com where RL is the load resistance. The Fault Timeout Period must be set longer than tON to prevent a fault shutdown before the turn-on sequence is complete. RS Q1 VSYS OUT PGD VIN LM5069 CL RL GND GND Figure 30. No Load Current During Turn-On RS Q1 VSYS CL OUT VIN PGD RL LM5069 GND GND Figure 31.
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LM5069 www.ti.com SNVS452D – SEPTEMBER 2006 – REVISED MAY 2013 MOSFET SELECTION It is recommended that the external MOSFET (Q1) selection be based on the following criteria: - The BVDSS rating should be greater than the maximum system voltage (VSYS), plus ringing and transients which can occur at VSYS when the circuit card, or adjacent cards, are inserted or removed.
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LM5069 SNVS452D – SEPTEMBER 2006 – REVISED MAY 2013 tRESTART = CT x www.ti.com 7 x 2.75V 7 x 2.75V 3.7V + + 2.5 PA 85 PA 2.5 PA = CT x 9.4 x 106 For example, if CT = 0.33 µF, tRESTART = 3.1 seconds. At the end of the restart time, Q1 is switched on. If the fault is still present, the fault timeout and restart sequence repeats. The on-time duty cycle of Q1 is approximately 0.5% in this mode.
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LM5069 www.ti.com R2 = SNVS452D – SEPTEMBER 2006 – REVISED MAY 2013 2.5V x 190.5 k: - 8.61 k: = 7.53 k: (32V - 2.5V) The lower OVLO threshold calculates to 55.8V, and the OVLO hysteresis is 4.2V. Note that the OVLO hysteresis is always slightly greater than the UVLO hysteresis in this configuration. When the R1-R3 resistor values are known, the threshold voltages and hysteresis are calculated from the following: 2.5V VUVH = 2.5V + [R1 x (21 PA + )] (R2 + R3) VUVL = 2.
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LM5069 SNVS452D – SEPTEMBER 2006 – REVISED MAY 2013 www.ti.com VUVH = 2.5V + [R1 x (2.5V + 21 PA)] R2 2.5V x (R1 + R2) VUVL = R2 VUV(HYS) = R1 x 21 µA 2.5V x (R3 + R4) R4 VOVL = 2.5V + [R3 x (2.5V - 21 PA)] R4 VOVH = VOV(HYS) = R3 x 21 µA Option C: The minimum UVLO level is obtained by connecting the UVLO pin to VIN as shown in Figure 35. Q1 is switched on when the VIN voltage reaches the POREN threshold (≊8.4V).
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LM5069 www.ti.com SNVS452D – SEPTEMBER 2006 – REVISED MAY 2013 VPGD VPGD VPGD R PG1 LM5069 PGD Power Good CPG R PG1 R PG1 LM5069 R PG2 PGD LM5069 Power Good CPG GND GND a) Delay Rising Edge Only b) Long delay at rising edge, short delay at falling edge PGD R PG2 Power Good C PG GND c) Short Delay at Rising Edge and Long Delay at Falling Edge or Equal Delays Figure 37.
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LM5069 SNVS452D – SEPTEMBER 2006 – REVISED MAY 2013 www.ti.com GND VSYS To Load RS Q1 SENSE GATE OUT VIN UVLO PGD OVLO PWR GND TIMER R1 R2 R3 LM5069 PLUG-IN CARD CARD EDGE CONNECTOR Figure 38. Recommended Board Connector Design System Considerations A) Continued proper operation of the LM5069 hot swap circuit requires capacitance be present on the supply side of the connector into which the hot swap circuit is plugged in, as depicted in Figure 23.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 17-May-2014 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-May-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM5069MM-1/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5069MM-2 VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 LM5069MM-2/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 16-May-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5069MM-1/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0 LM5069MM-2 VSSOP DGS 10 1000 210.0 185.0 35.0 LM5069MM-2/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0 LM5069MMX-1/NOPB VSSOP DGS 10 3500 367.0 367.0 35.0 LM5069MMX-2/NOPB VSSOP DGS 10 3500 367.0 367.0 35.
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