Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - PoE controller HTSSOP 16 Controller (PD) DC/DC

LM5072

www.ti.com

SNVS437D –MARCH 2006–REVISED APRIL 2013

LM5072 Integrated 100V Power Over Ethernet PD Interface and PWM Controller with Aux

Support

Check for Samples: LM5072

FEATURES

DESCRIPTION

The LM5072 Powered Device (PD) interface and

• PD Interface

Pulse-Width-Modulation (PWM) controller provides a

– Fully Compliant IEEE 802.3af PD Interface

complete power solution, fully compliant to IEEE

– Versatile Auxiliary Power Options

802.3af, for the PD connecting into Power over

Ethernet (PoE) networks. This controller integrates all

– 9V Minimum Auxiliary Power Operating

functions necessary to implement both a PD powered

Range

interface and DC-DC converter with a minimum

– 100V Maximum Input Voltage Rating

number of external components. The LM5072

– Programmable DC Current Limit Up To

provides the flexibility for the PD to also accept power

800mA

from auxiliary sources such as AC adapters in a

variety of configurations. The low RDS(ON) PD

– 100V, 0.7Ω Hot Swap MOSFET

interface hot swap MOSFET and programmable DC

– Integrated PD Signature Resistor

current limit extend the range of LM5072 applications

– Integrated PoE Input UVLO

up to twice the power level of 802.3af compliant PD

devices. The 100V maximum voltage rating simplifies

– Programmable Inrush Current Limit

selection of the transient voltage suppressor that

– PD Classification Capability

protects the PD from network transients. The LM5072

– Power Good Indicator

includes an easy-to-use PWM controller that

facilitates the various single-ended power supply

– Thermal Shutdown Protection

topologies including the flyback, forward and buck.

• PWM Controller

The PWM control scheme is based on peak current

– Current Mode PWM Controller

mode control, which provides inherent advantages

including line feed-forward, cycle-by-cycle current

– 100V Start-Up Regulator

limit, and simplified feedback loop compensation.

– Error Amplifier with 2% Voltage Reference

Two versions of the LM5072 provide either an 80%

– Supports Isolated and Non-Isolated

maximum duty cycle (-80 suffix), or a 50% maximum

Applications

duty cycle (-50 suffix).

– Programmable Oscillator Frequency

PACKAGES

– Programmable Soft-Start

• TSSOP-16 EP (Exposed Pad)

– 800 mA Peak Gate Driver

– 80% Maximum Duty Cycle with Built-in

Slope Compensation (-80 Device)

– 50% Maximum Duty Cycle, No Slope

Compensation (-50 Device)

APPLICATIONS

• IEEE 802.3af Compliant PoE Powered Devices

• Non-Compliant, Application Specific Devices

• Higher Power Ethernet Powered Devices

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (34 pages)

PAGE 1
LM5072 www.ti.com SNVS437D – MARCH 2006 – REVISED APRIL 2013 LM5072 Integrated 100V Power Over Ethernet PD Interface and PWM Controller with Aux Support Check for Samples: LM5072 FEATURES DESCRIPTION • The LM5072 Powered Device (PD) interface and Pulse-Width-Modulation (PWM) controller provides a complete power solution, fully compliant to IEEE 802.3af, for the PD connecting into Power over Ethernet (PoE) networks.
PAGE 2
LM5072 SNVS437D – MARCH 2006 – REVISED APRIL 2013 www.ti.com Simplified Application Diagram +VOUT +PoE LM5072 VCC VIN SS + FAUX RAUX RT ICL_FAUX COMP - FAUX RCLASS FB nPGOOD OUT CS DCCL ARTN - PoE VEE RTN Connection Diagram 1 2 3 4 5 6 7 8 LM5072 RT ARTN SS COMP VIN RCLASS ICL_FAUX DCCL FB RAUX CS nPGOOD 16 15 14 13 12 11 10 VEE VCC RTN OUT 9 Figure 1.
PAGE 3
LM5072 www.ti.com SNVS437D – MARCH 2006 – REVISED APRIL 2013 PIN DESCRIPTIONS Pin Number Name Description 1 RT PWM controller oscillator frequency programming pin. 2 SS Soft-start programming pin. 3 VIN Positive supply pin for the PD interface and the internal PWM controller start-up regulator. 4 RCLASS 5 ICL_FAUX PD classification programming pin. 6 DCCL 7 VEE Negative supply pin for PD interface; connected to PoE and/or front auxiliary power return path.
PAGE 4
LM5072 SNVS437D – MARCH 2006 – REVISED APRIL 2013 www.ti.com Absolute Maximum Ratings (1) (2) VIN , RTN to VEE (3) -0.3V to 100V RAUX to ARTN -0.3V to 100V ICL_FAUX to VEE -0.3V to 100V DCCL, RCLASS to VEE -0.3V to 7V nPGOOD to ARTN -0.3V to 16V ARTN to RTN -0.3V to 0.3V VCC, OUT to ARTN -0.3V to 16V CS, FB, RT to ARTN -0.3V to 7V COMP, SS to ARTN -0.3V to 5.5V ESD Rating Human Body Model (4) 2000V Lead Soldering Temp.
PAGE 5
LM5072 www.ti.com SNVS437D – MARCH 2006 – REVISED APRIL 2013 Electrical Characteristics(1) (continued) Specifications in standard type face are for TJ = +25°C and those in boldface type apply over the full operating junction temperature range. Unless otherwise specified: VIN = 48V, FOSC = 250kHz. Symbol Parameter Conditions Min Typ Max Units VDS Required for Power Good Status 1.3 1.5 1.7 V VDS Hysteresis of Power Good Status 0.8 1.0 1.2 V VGS Required for Power Good Status 4.5 5.5 6.
PAGE 6
LM5072 SNVS437D – MARCH 2006 – REVISED APRIL 2013 www.ti.com Electrical Characteristics(1) (continued) Specifications in standard type face are for TJ = +25°C and those in boldface type apply over the full operating junction temperature range. Unless otherwise specified: VIN = 48V, FOSC = 250kHz. Symbol Parameter Conditions Min Typ Max Units 8 10 12 µA Frequency1 (RT = 26.1 kΩ) 175 200 225 KHz Frequency2 (RT = 8.7 kΩ) 515 580 645 KHz Sync threshold 2.6 3.2 3.
PAGE 7
LM5072 www.ti.com SNVS437D – MARCH 2006 – REVISED APRIL 2013 Typical Performance Characteristics UVLO Threshold vs Temperature Default Current Limit vs Temperature 475 32.0 DC CURRENT LIMIT (mA) UVLO THRESHOLD (V) 470 31.5 31.0 30.5 465 460 455 450 445 440 435 430 425 30.0 -40 -20 0 20 40 60 -40 -20 80 100 120 0 TEMPERATURE (ºC) Figure 2.
PAGE 8
LM5072 SNVS437D – MARCH 2006 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) Oscillator Frequency vs RT Resistance Error Amplifier Reference Voltage vs Temperature 1000 1.2750 E/A REFERENCE VOLTAGE (V) OSCILLATOR FREQUENCY (kHz) 900 800 700 600 500 400 300 200 100 1.2650 1.2550 1.2450 1.2350 0 5 1.2250 -40 -20 15 25 35 45 55 65 75 85 95 105 0 20 40 60 80 100 120 TEMPERATURE (ºC) RT RESISTANCE (k:) Figure 8. Figure 9.
PAGE 9
LM5072 www.ti.com SNVS437D – MARCH 2006 – REVISED APRIL 2013 Specialized Block Diagrams VIN 3 signature 24.5 k: 2.5V 12.0V + 10 VCC - + 5V_PDI + 1. 25V Threshold VIN = 25V - Disable_PDI - + 2.4V 2.0V Threshold VIN= 38V VIN Hysteresis = 6V UVLO 1. 25V + EN RCLASS + 1. 25V Auxiliary Controller 4 13 RAUX thermal_ limit 50 PA 11 nPGOOD 5 2.5V VCC - S front_aux R Q ICL _FAUX + Disable 1. 25V pgood + 50 PA + 1. 25V PWM Controller 1 RT 2 SS 9 OUT 12 CS 6 VEE 1.
PAGE 10
LM5072 SNVS437D – MARCH 2006 – REVISED APRIL 2013 www.ti.com 45 PA 0 15 OSC 80 % MAX DUTY LIMIT (- 80) 50 % MAX DUTY LIMIT (- 50) 5V S SET Q DRIVER 9 OUT R CLR 5k RT CLK Slope Compensation disabled for -50 Device COMP 1 Slope Compensation Generator Q PWM 100k 1. 25V 14 1.4V FB LOGIC 50k 10 PA SS SS to Error Amplifier 2 SS 2k 0.5V CURRENT LIMIT 12 CLK + LEB current sense 65 ns blanking CS 16 ARTN Figure 15.
PAGE 11
LM5072 www.ti.com SNVS437D – MARCH 2006 – REVISED APRIL 2013 DESCRIPTION OF OPERATION AND APPLICATIONS INFORMATION The LM5072 integrates a fully IEEE 802.3af compliant PD interface and PWM controller in a single integrated circuit, providing a complete and low cost power solution for devices that connect to PoE systems. The implementation requires a minimal number of external components. The LM5072’s Hot Swap PD interface provides four major advantages: 1.
PAGE 12
LM5072 SNVS437D – MARCH 2006 – REVISED APRIL 2013 www.ti.com Voltage 42V 30V Classification 14.5V 10V Time 2.7V Discovery Full Power Application Classification Power Removal Figure 16. Sequence of PoE Operating Modes Table 1. Operating Modes With Respect To Input Voltage Mode of Operation Voltage from PoE Cable per IEEE 802.3af LM5072 Input Voltage (VIN pin to VEE pin) Detection (Signature) 2.7V to 10.0V 1.5V to 10.0V Classification 14.5V to 20.5V 12V to 23.
PAGE 13
LM5072 www.ti.com SNVS437D – MARCH 2006 – REVISED APRIL 2013 Table 2. Classification Levels and Required External Resistor Value Class PD Max Power Level ICLASS Range To LM5072 RCLASS Value From To From 0 (Default) 0.44W 12.95W 0 mA 4 mA 1 0.44W 3.84W 9 mA 12 mA 130Ω 2 3.84W 6.49W 17 mA 20 mA 71.5Ω 3 6.49W 12.95W 26 mA 30 mA 46.4Ω 4 Reserved Reserved 36 mA 44 mA 31.6Ω Open LM5072 PoE Line Input VIN 3 front_aux + EN - RCLASS 4 + 1.25V - 1.25V Threshold VIN = 23.
PAGE 14
LM5072 SNVS437D – MARCH 2006 – REVISED APRIL 2013 www.ti.com Undervoltage Lockout (UVLO) The LM5072’s internal preset UVLO circuit continuously monitors the PoE input voltage between the VIN and VEE pins. When the VIN voltage rises above 38V nominal, the UVLO circuit will release the hot swap MOSFET and initiate the startup inrush sequence. When the VIN voltage falls below 31V nominal during normal operating mode, the LM5072 disables the PD by shutting off the hot swap MOSFET.
PAGE 15
LM5072 www.ti.com SNVS437D – MARCH 2006 – REVISED APRIL 2013 To adjust the capacitor charging time for a particular application requirement, the inrush limit can be programmed to any value between 150 and 400 mA with an external resistor (RICL) between the ICL_FAUX and VEE pins, as shown in Figure 20. The relationship between the RICL value and the desired inrush current limit IINRUSH satisfies the following equation: RICL(k:) = 100 mA x 127.5 k: IINRUSH (mA) (1) LM5072 to inrush current limit 1.
PAGE 16
LM5072 SNVS437D – MARCH 2006 – REVISED APRIL 2013 www.ti.com The maximum recommended DC current limit is 800 mA. While thermal analysis should be a standard part of the module development process, it may warrant additional attention if the DC current limit is programmed to values in excess of 400 mA.
PAGE 17
LM5072 www.ti.com SNVS437D – MARCH 2006 – REVISED APRIL 2013 CPGOOD(nF) = 0.05mA + ILED (mA) 1mA x tPG_Delay (ms) 0.25 ms x 100 nF (3) For example, selecting 1000 nF for CPGOOD, the delay time will be 50 ms if no LED is used and about 0.83 ms when an LED, drawing 3 mA, is used. The delay required for continued operation will depend on the amplitude of the transient, the DC current limit, the load, and the total amount of input capacitance. Note that this delay does not ensure continued operation.
PAGE 18
LM5072 SNVS437D – MARCH 2006 – REVISED APRIL 2013 www.ti.com +RAUX +PoE +VOUT VIN LM5072 VCC SS RAUX RT ICL_ FAUX COMP RCLASS FB nPGOOD OUT CS DCCL VEE -PoE ARTN RTN -RAUX 0.1 PF Figure 24. The RAUX Configuration Table 3. Comparison Between FAUX and RAUX Operation Tradeoff FAUX Operation RAUX Operation Hot Swap Protection / Current Limit Protection Automatically provided by the hot swap MOSFET. Requires a series resistor to limit the inrush current during hot swap.
PAGE 19
LM5072 www.ti.com SNVS437D – MARCH 2006 – REVISED APRIL 2013 If either FAUX or RAUX power is supplied prior to PoE power, it will prevent the recognition of the PD by the PSE. Consequently, continuity of power delivery cannot be ensured because the PoE supply will not be present when auxiliary power is removed. FAUX Option With the FAUX option, the LM5072 hot swap MOSFET provides inrush and DC current limit protection for the auxiliary power source.
PAGE 20
LM5072 SNVS437D – MARCH 2006 – REVISED APRIL 2013 www.ti.com A Note About FAUX and RAUX Pin False Input State Detection The ICL_FAUX and RAUX pins are used to sense the presence of auxiliary power sources. The input voltage of each pin must remain low when the auxiliary power sources are absent. However, the Or-ing diodes feeding the auxiliary power are not ideal and leak reverse current that can flow from the PoE input to both the ICL_FAUX and RAUX pins.
PAGE 21
LM5072 www.ti.com SNVS437D – MARCH 2006 – REVISED APRIL 2013 LM 5072 Vo 5V COMP Zcomp 15 R1 5k 14 FB 1.25V to PWM R2 16 SS ARTN Figure 26. Internal Error Amplifier – Used for Non-isolated Output Applications For isolated applications, the error amplifier function is located on the isolated secondary side. The LM5072’s error amplifier can be disabled by connecting the FB pin to the ARTN pin.
PAGE 22
LM5072 SNVS437D – MARCH 2006 – REVISED APRIL 2013 www.ti.com Leading Edge Narrow Spike Figure 29. Typical Current Sense Waveform Having a Leading Edge Spike The current sense signal is also used for cycle-by-cycle over-current protection. When the CS pin signal exceeds 0.5V, the PWM pulse of that cycle will be immediately terminated. The desired cycle-by-cycle over-current protection level is achieved by selecting the proper value of current sense resistor that produces 0.5V at the CS pin.
PAGE 23
LM5072 www.ti.com SNVS437D – MARCH 2006 – REVISED APRIL 2013 LM5072 RT 100 pF 1 to Clock RT Synch Pulse 16 ARTN Figure 30. Oscillator Synchronization Implementation Special attention should be paid to the relationship between the oscillator frequency and the PWM switching frequency. For the LM5072-50 version, the programmed oscillator frequency is internally divided by two in order to facilitate the 50% duty cycle limit.
PAGE 24
LM5072 SNVS437D – MARCH 2006 – REVISED APRIL 2013 5. 6. 7. 8. www.ti.com winding. This re-configuration should make use of the spare pins of the transformer. R24 should be deleted from the schematic completely, being replaced by a short connection for an isolated application, or by an open for a non-isolated application.
PAGE 25
LM5072 www.ti.com SNVS437D – MARCH 2006 – REVISED APRIL 2013 7. C26 should be placed directly across the SS and ARTN pins. 8. C21 should be placed directly across the nPGOOD and ARTN pins. 9. R25 should be directly routed from the output port. 10. R9 should be directly routed from R14/R15. 11. D6 and Z1 should be placed to achieve the shortest connection from C4 or C5 to the drain pad(s) of Q1 for better snubbing. 12. C2 and R4 should be placed to achieve the shortest connection across D5. 13.
PAGE 26
LM5072 SNVS437D – MARCH 2006 – REVISED APRIL 2013 www.ti.com Application Example #2 Figure 32 shows an example of an isolated, dual-output solution for the PD. The 3.3V output is tightly regulated while the 5V output is cross-regulated. Both front auxiliary (FAUX) and rear auxiliary (RAUX) power options are given, although only one option may be needed in practice. Note that for the RAUX option, D2 is only installed when the supply voltage of the auxiliary power source is lower than 14.5V. Figure 32.
PAGE 27
LM5072 www.ti.com SNVS437D – MARCH 2006 – REVISED APRIL 2013 Application Example #3: Figure 33 shows an application example of the non-isolated version of Figure 31. This non-isolated version saves many parts used in the isolated feedback example shown in Figure 31. Similar simplification also applies to the non-isolated version of Figure 32. Figure 33. PD Solution with Non-Isolated Flyback Topology Application Example #4 Figure 34 shows an application example of a PD solution using the buck topology.
PAGE 28
LM5072 SNVS437D – MARCH 2006 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision C (April 2013) to Revision D • 28 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
PAGE 29
PACKAGE OPTION ADDENDUM www.ti.
PAGE 30
PACKAGE OPTION ADDENDUM www.ti.com 7-Oct-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PAGE 31
PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) LM5072MHX-50/NOPB HTSSOP PWP 16 2500 330.0 12.4 LM5072MHX-80/NOPB HTSSOP PWP 16 2500 330.0 12.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.95 8.3 1.6 8.0 12.0 Q1 6.95 8.3 1.6 8.0 12.
PAGE 32
PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5072MHX-50/NOPB HTSSOP PWP 16 2500 367.0 367.0 35.0 LM5072MHX-80/NOPB HTSSOP PWP 16 2500 367.0 367.0 35.
PAGE 33
MECHANICAL DATA PWP0016A MXA16A (Rev A) www.ti.
PAGE 34
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.