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LM5085

PGATE

ISEN

GND

VCC

ADJ

4.5V to 75V

Input

GND

SHUTDOWN

VCC

ADJ

Cff

OUT

FB2

FB1

OUT

GND

VIN

LM5085, LM5085-Q1

www.ti.com

SNVS565G –NOVEMBER 2008–REVISED MARCH 2013

LM5085/LM5085-Q1 75V Constant On-Time PFET Buck Switching Controller

Check for Samples: LM5085, LM5085-Q1

FEATURES

DESCRIPTION

The LM5085 is a high efficiency PFET switching

• LM5085-Q1 is an Automotive Grade Product

regulator controller that can be used to quickly and

that is AEC-Q100 Grade 1 Qualified (-40°C to

easily develop a small, efficient buck regulator for a

125°C Operating Junction Temperature)

wide range of applications. This high voltage

• Wide 4.5V to 75V Input Voltage Range

controller contains a PFET gate driver and a high

voltage bias regulator which operates over a wide

• Adjustable Current Limit Using R

DS(ON)

or a

4.5V to 75V input range. The constant on-time

Current Sense Resistor

regulation principle requires no loop compensation,

• Programmable Switching Frequency to 1MHz

simplifies circuit implementation, and results in

• No Loop Compensation Required

ultrafast load transient response. The operating

frequency remains nearly constant with line and load

• Ultra-Fast Transient Response

variations due to the inverse relationship between the

• Nearly Constant Operating Frequency with

input voltage and the on-time. The PFET architecture

Line and Load Variations

allows 100% duty cycle operation for a low dropout

• Adjustable Output Voltage from 1.25V

voltage. Either the R

DS(ON)

of the PFET or an external

sense resistor can be used to sense current for over-

• Precision ±2% Feedback Reference

current detection.

• Capable of 100% Duty Cycle Operation

• Internal Soft-start Timer

• Integrated High Voltage Bias Regulator

• Thermal Shutdown

Package

• HVSSOP-8

• VSSOP-8

• WSON-8 (3mm x 3mm)

Typical Application, Basic Step Down Controller

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (29 pages)

PAGE 1
LM5085, LM5085-Q1 www.ti.com SNVS565G – NOVEMBER 2008 – REVISED MARCH 2013 LM5085/LM5085-Q1 75V Constant On-Time PFET Buck Switching Controller Check for Samples: LM5085, LM5085-Q1 FEATURES DESCRIPTION • The LM5085 is a high efficiency PFET switching regulator controller that can be used to quickly and easily develop a small, efficient buck regulator for a wide range of applications.
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LM5085, LM5085-Q1 SNVS565G – NOVEMBER 2008 – REVISED MARCH 2013 www.ti.com Connection Diagram Exposed Pad on Bottom Connect to Ground ADJ 1 8 VIN RT 2 7 VCC FB 3 6 PGATE GND 4 5 ISEN VIN ADJ 1 8 RT 2 7 VCC FB 3 6 PGATE GND 4 5 ISEN Exposed Pad on Bottom Connect to Ground Figure 1. Top View 8-Lead HVSSOP-8 Figure 2. Top View 8-Lead WSON ADJ 1 8 RT 2 7 VCC FB 3 6 PGATE GND 4 5 ISEN VIN Figure 3. Top View 8-Lead VSSOP Pin Descriptions Pin No.
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LM5085, LM5085-Q1 www.ti.com SNVS565G – NOVEMBER 2008 – REVISED MARCH 2013 Absolute Maximum Ratings (1) (2) VIN to GND -0.3V to 76V ISEN to GND -3V to VIN + 0.3V ADJ to GND -0.3V to VIN + 0.3V RT, FB to GND -0.3V to 7V VIN to VCC, VIN to PGATE -0.3V to 10V ESD Rating (3) Human Body Model 2kV Storage Temperature Range (1) (2) (3) -65°C to +150°C Absolute Maximum Ratings are limits beyond which damage to the device may occur.
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LM5085, LM5085-Q1 SNVS565G – NOVEMBER 2008 – REVISED MARCH 2013 www.ti.com Electrical Characteristics (continued) Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
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LM5085, LM5085-Q1 www.ti.com SNVS565G – NOVEMBER 2008 – REVISED MARCH 2013 Typical Performance Characteristics Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 48V. Efficiency (Circuit of Figure 28) Input Operating Current vs. VIN Figure 4. Figure 5. Shutdown Current vs. VIN VCC vs. VIN Figure 6. Figure 7. VCC vs. ICC On-Time vs. RT and VIN Figure 8. Figure 9.
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LM5085, LM5085-Q1 SNVS565G – NOVEMBER 2008 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 48V. Off-Time vs. VIN and VFB Voltage at the RT Pin VOLTAGE AT THE RT PIN (V) 4 25 k: 50 k: 3 100 k: 200 k: 2 RT = 500 k: 300 k: 1 0 0 10 20 30 40 50 60 70 80 VIN (V) 6 Figure 10. Figure 11. ADJ Pin Current vs. VIN Input Operating Current vs. Temperature Figure 12. Figure 13.
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LM5085, LM5085-Q1 www.ti.com SNVS565G – NOVEMBER 2008 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 48V. On-Time vs. Temperature Minimum On-Time vs. Temperature Figure 16. Figure 17. Off-Time vs. Temperature Current Limit Comparator Offset vs. Temperature Figure 18. Figure 19. ADJ Pin Current vs. Temperature PGATE Driver Output Resistance vs. Temperature Figure 20. Figure 21.
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LM5085, LM5085-Q1 SNVS565G – NOVEMBER 2008 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Unless otherwise specified the following conditions apply: TJ = 25°C, VIN = 48V. Feedback Reference Voltage vs. Temperature Soft-Start Time vs. Temperature Figure 22. Figure 23. RT Pin Shutdown Threshold vs. Temperature Figure 24.
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LM5085, LM5085-Q1 www.ti.com SNVS565G – NOVEMBER 2008 – REVISED MARCH 2013 Block Diagram 4.5V to 75V Input VIN GND VIN CIN Negative Bias Regulator 7.7V CBYP LM5085 + - 0.73V RT + CVCC CADJ Thermal Shutdown RT + VCC VIN RADJ VCC UVLO ON Time One-Shot Gate Driver RSEN PGATE Q1 SHUTDOWN VCC 1.25V Soft-Start Gate Driver Control Logic L1 ADJ COUT 40 PA GND + QS - R REGULATION COMPARATOR 1.
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LM5085, LM5085-Q1 SNVS565G – NOVEMBER 2008 – REVISED MARCH 2013 www.ti.com FUNCTIONAL DESCRIPTION OVERVIEW The LM5085 is a PFET buck (step-down) DC-DC controller using the constant on-time (COT) control principle. The input operating voltage range of the LM5085 is 4.5V to 75V. The use of a PFET in a buck regulator greatly simplifies the gate drive requirements and allows for 100% duty cycle operation to extend the regulation range when operating at low input voltage.
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LM5085, LM5085-Q1 www.ti.com SNVS565G – NOVEMBER 2008 – REVISED MARCH 2013 ON-TIME TIMER The on-time of the PFET gate drive output (PGATE pin) is determined by the resistor (RT) and the input voltage (VIN), and is calculated from: -7 tON = 1.45 x 10 x (RT + 1.4) (VIN - 1.56V + RT/3167) + 50 ns (3) where RT is in kΩ. The minimum on-time, which occurs at maximum VIN, should not be set less than 150ns (see Current Limiting section).
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LM5085, LM5085-Q1 SNVS565G – NOVEMBER 2008 – REVISED MARCH 2013 www.ti.com CURRENT LIMITING The LM5085 current limiting operates by sensing the voltage across either the RDS(ON) of Q1, or a sense resistor, during the on-time and comparing it to the voltage across the resistor RADJ (see Figure 26). The current limit function is much more accurate and stable over temperature when a sense resistor is used. The RDS(ON) of a MOSFET has a wide process variation and a large temperature coefficient.
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LM5085, LM5085-Q1 www.ti.com SNVS565G – NOVEMBER 2008 – REVISED MARCH 2013 The on-time in Equation 11 is shorter than the normal on-time since the PFET is shut off when the current limit threshold is crossed. If the off-time is not long enough, such that the current decrease (Equation 12) is less than the current increase (Equation 11), the current levels are higher at the start of the next on-time. This results in a further decrease in on-time, since the current limit threshold is crossed sooner.
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LM5085, LM5085-Q1 SNVS565G – NOVEMBER 2008 – REVISED MARCH 2013 www.ti.com P-CHANNEL MOSFET SELECTION The PFET must be rated for the maximum input voltage, with some margin above that to allow for transients and ringing which can occur on the supply line and the switching node. The gate-to-source voltage (VGS) normally provided to the PFET is 7.7V for VIN greater than 8.5V.
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LM5085, LM5085-Q1 www.ti.com SNVS565G – NOVEMBER 2008 – REVISED MARCH 2013 Applications Information EXTERNAL COMPONENTS The procedure for calculating the external components is illustrated with the following design example.
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LM5085, LM5085-Q1 www.ti.com IPK IOR IOUT 1/FS SW Node Inductor Current SNVS565G – NOVEMBER 2008 – REVISED MARCH 2013 Figure 27. Inductor Current Waveform RSEN, RADJ: To achieve good current limit accuracy and avoid over designing the power stage components, the sense resistor method is used for current limiting in this example. A standard value 10mΩ resistor is selected for RSEN, resulting in a 50mV drop at maximum load current, and a maximum 0.25W power dissipation in the resistor.
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LM5085, LM5085-Q1 www.ti.com SNVS565G – NOVEMBER 2008 – REVISED MARCH 2013 R3, C1, C2: The minimum ripple configuration uses these three components to generate the ripple voltage required at the FB pin since there is insufficient ripple at VOUT. A minimum of 25 mVp-p must be applied to the FB pin to obtain stable constant frequency operation. R3 and C1 are selected to generate a sawtooth waveform at their junction, and that waveform is AC coupled to the FB pin via C2.
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LM5085, LM5085-Q1 SNVS565G – NOVEMBER 2008 – REVISED MARCH 2013 www.ti.com PDISS = 55V x ((40nC x 300kHz) + 1.4mA) = 737mW (32) Using an HVSSOP package with a θJA of 46°C/W produces a temperature rise of 34°C from junction to ambient. Final Design Example Circuit The final circuit is shown in Figure 28, and its performance is presented in Figure 29 through Figure 32. 7V to 55V Input CIN 33 PF GND 0.47 PF VCC VIN VIN CVCC LM5085 CBYP 1 PF CADJ 1000 pF ADJ RT 90.9 k: RADJ RSEN 2.1 k: 0.
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LM5085, LM5085-Q1 www.ti.com SNVS565G – NOVEMBER 2008 – REVISED MARCH 2013 Alternate Output Ripple Configurations The minimum ripple configuration, employing C1, C2, and R3 in Figure 28, results in a low ripple amplitude at VOUT determined mainly by the characteristics of the output capacitor and the ripple current in L1. This configuration allows multiple ceramic capacitors to be used for VOUT if the output voltage is provided to several places on the PC board.
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LM5085, LM5085-Q1 SNVS565G – NOVEMBER 2008 – REVISED MARCH 2013 www.ti.com LM5085 L1 PGATE Q1 D1 VOUT R4 RFB2 FB COUT GND RFB1 GND Figure 34. Lowest Cost Ripple Generating Configuration PC Board Layout In most applications, the heat sink pad or tab of Q1 is connected to the switch node, i.e. the junction of Q1, L1 and D1.
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LM5085, LM5085-Q1 www.ti.com SNVS565G – NOVEMBER 2008 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision F (March 2013) to Revision G • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 19-Jul-2013 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing LM5085MM/NOPB VSSOP DGK 8 LM5085MME/NOPB VSSOP DGK LM5085MMX/NOPB VSSOP DGK LM5085MY/NOPB MSOPPower PAD LM5085MYE/NOPB SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 8 250 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 8 3500 330.0 12.4 5.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM5085SDE/NOPB WSON NGQ 8 250 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1 LM5085SDX/NOPB WSON NGQ 8 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.
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MECHANICAL DATA DGN0008A MUY08A (Rev A) BOTTOM VIEW www.ti.
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MECHANICAL DATA NGQ0008A SDA08A (Rev A) www.ti.
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