Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - gate drivers Non-inverting High side, Low side, Sychronous SOIC 8

UVLO

DRIVER

UVLO

LEVEL

SHIFT

DRIVER

VDD

VSS

LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C

www.ti.com

SNOSAW2P –SEPTEMBER 2006–REVISED MARCH 2013

LM5100A/B/C

LM5101A/B/C 3A, 2A and 1A High Voltage High-Side and Low-Side Gate Drivers

Check for Samples: LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C

FEATURES

DESCRIPTION

The LM5100A/B/C and LM5101A/B/C High Voltage

• Drives Both a High-side and Low-side N-

Gate Drivers are designed to drive both the high-side

Channel MOSFETs

and the low-side N-Channel MOSFETs in a

• Independent High and Low Driver Logic Inputs

synchronous buck or a half-bridge configuration. The

• Bootstrap Supply Voltage up to 118V DC

floating high-side driver is capable of operating with

supply voltages up to 100V. The “A” versions provide

• Fast Propagation Times (25 ns Typical)

a full 3A of gate drive while the “B” and “C” versions

• Drives 1000 pF Load with 8 ns Rise and Fall

provide 2A and 1A respectively. The outputs are

Times

independently controlled with CMOS input thresholds

• Excellent Propagation Delay Matching (3 ns

(LM5100A/B/C) or TTL input thresholds

(LM5101A/B/C). An integrated high voltage diode is

typical)

provided to charge the high-side gate drive bootstrap

• Supply Rail Under-voltage Lockout

capacitor. A robust level shifter operates at high

• Low Power Consumption

speed while consuming low power and providing

• Pin Compatible with HIP2100/HIP2101 clean level transitions from the control logic to the

high-side gate driver. Under-voltage lockout is

provided on both the low-side and the high-side

TYPICAL APPLICATIONS

power rails. These devices are available in the

• Current Fed Push-pull Converters

standard SOIC-8 pin, SO PowerPad-8 pin and the

• Half and Full Bridge Power Converters

WSON-10 pin packages. The LM5100C and

LM5101C are also available in MSOP-PowerPad-8

• Synchronous Buck Converters

package. The LM5101A is also available in WSON-8

• Two Switch Forward Power Converters

pin package.

• Forward with Active Clamp Converters

Package

• SOIC-8

• SO PowerPad-8

• WSON-8 (4 mm x 4 mm)

• WSON-10 (4 mm x 4 mm)

• MSOP-PowerPad-8

Simplified Block Diagram

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (28 pages)

PAGE 1
LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C www.ti.com SNOSAW2P – SEPTEMBER 2006 – REVISED MARCH 2013 LM5100A/B/C LM5101A/B/C 3A, 2A and 1A High Voltage High-Side and Low-Side Gate Drivers Check for Samples: LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C FEATURES DESCRIPTION • The LM5100A/B/C and LM5101A/B/C High Voltage Gate Drivers are designed to drive both the high-side and the low-side N-Channel MOSFETs in a synchronous buck or a half-bridge configuration.
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LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C SNOSAW2P – SEPTEMBER 2006 – REVISED MARCH 2013 www.ti.com Table 1.
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LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C www.ti.com SNOSAW2P – SEPTEMBER 2006 – REVISED MARCH 2013 PIN DESCRIPTIONS(1) (continued) Pin # SO Power Pad-8 SOIC-8 4 WSON8 (1) 4 5 4 5 WSON10 (1) MSOPPowerPad -8 (1) 4 5 4 7 5 Name Description Application Information HS High-side MOSFET source connection Connect to the bootstrap capacitor negative terminal and the source of the high-side MOSFET. HI High-side driver control input The LM5100A/B/C inputs have CMOS type thresholds.
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LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C SNOSAW2P – SEPTEMBER 2006 – REVISED MARCH 2013 www.ti.com Electrical Characteristics Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
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LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C www.ti.com SNOSAW2P – SEPTEMBER 2006 – REVISED MARCH 2013 Electrical Characteristics (continued) Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
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LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C SNOSAW2P – SEPTEMBER 2006 – REVISED MARCH 2013 www.ti.com Switching Characteristics Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are specified through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
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LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C www.ti.com SNOSAW2P – SEPTEMBER 2006 – REVISED MARCH 2013 Typical Performance Characteristics Peak Sourcing Current vs VDD Peak Sinking Current vs VDD 5.0 5.0 4.5 4.5 4.0 4.0 LM5100A/LM5101A 3.5 CURRENT (A) CURRENT (A) 3.5 3.0 2.5 2.0 LM5100B/LM5101B 1.5 1.0 2.5 2.0 LM5100B/LM5101B 1.5 1.0 LM5100C/LM5101C 0.5 0.0 LM5100A/LM5101A 3.0 7 8 9 10 11 12 13 14 LM5100C/LM5101C 0.5 0.0 15 7 8 9 10 11 12 Figure 1. Figure 2.
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LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C SNOSAW2P – SEPTEMBER 2006 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) Operating Current vs Temperature IHB vs Frequency 2.3 100000 2.1 HB = 12V, HS = 0V IDDO (LM5101A/B/C) CL = 4400 pF 10000 IDDO (LM5100A/B/C) 1.7 CURRENT (PA) CURRENT (mA) 1.9 IHBO 1.5 1.3 CL = 1000 pF 1000 CL = 0 pF 100 1.1 0.9 0.7 -50 -25 0 25 50 75 10 0.
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LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C www.ti.com SNOSAW2P – SEPTEMBER 2006 – REVISED MARCH 2013 Typical Performance Characteristics (continued) LM5100A/B/C Input Threshold vs Temperature Bootstrap Diode Forward Voltage 50 1.00E-01 THRESHOLD VOLTAGE (%VDD) T = 150°C 1.00E-02 ID (A) 1.00E-03 T = 25°C 1.00E-04 T = -40°C 1.00E-05 1.00E-06 0.2 0.3 0.4 0.5 0.6 0.7 0.8 49 48 Rising 47 46 45 44 Falling 43 42 41 40 -50 -25 0.
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LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C SNOSAW2P – SEPTEMBER 2006 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) LM5101A/B/C Propagation Delay vs Temperature LO & HO Gate Drive - High Level Output Voltage vs Temperature 1.0 40 VDD = 12V 0.9 0.8 35 LM5100C/LM5101C 30 VOH (V) DELAY (ns) 0.7 T_PLH 25 0.6 0.5 LM5100B/LM5101B 0.4 0.3 T_PHL 0.2 20 LM5100A/LM5101A 0.1 15 -50 -25 0 25 50 0.
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LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C www.ti.com SNOSAW2P – SEPTEMBER 2006 – REVISED MARCH 2013 TIMING DIAGRAM LI LI HI tHPLH tLPLH HI tHPHL tLPHL LO LO HO HO tMON tMOFF Figure 24. Layout Considerations The optimum performance of high and low-side gate drivers cannot be achieved without taking due considerations during circuit board layout. Following points are emphasized. 1.
PAGE 12
LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C SNOSAW2P – SEPTEMBER 2006 – REVISED MARCH 2013 www.ti.com Recommended Layout for Driver IC and Passives VDD LO HB VSS SO PowerPAD-8 LI HS HI To Hi-Side FET D Multi Layer Option LO N G HO HS HO Single Layer Option HO To Low-Side FET Power Dissipation Considerations The total IC power dissipation is the sum of the gate driver losses and the bootstrap diode losses.
PAGE 13
LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C www.ti.com SNOSAW2P – SEPTEMBER 2006 – REVISED MARCH 2013 The bootstrap diode power loss is the sum of the forward bias power loss that occurs while charging the bootstrap capacitor and the reverse bias power loss that occurs during reverse recovery. Since each of these events happens once per cycle, the diode power loss is proportional to frequency.
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LM5100A, LM5100B, LM5100C, LM5101A, LM5101B, LM5101C SNOSAW2P – SEPTEMBER 2006 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision O (March 2013) to Revision P • 14 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device LM5100AMRX/NOPB Package Package Pins Type Drawing SO Power PAD DDA SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM5100AMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM5100ASD WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LM5100CSD/NOPB WSON DPR 10 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM5100CSDX/NOPB WSON DPR 10 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 LM5101AMRX/NOPB SO Power PAD DDA 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LM5101AMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5100AMRX/NOPB SO PowerPAD DDA 8 2500 367.0 367.0 35.0 LM5100AMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM5100ASD WSON DPR 10 1000 210.0 185.0 35.0 LM5100ASD/NOPB WSON DPR 10 1000 210.0 185.0 35.0 LM5100ASDX/NOPB WSON DPR 10 4500 367.0 367.0 35.0 LM5100BMAX/NOPB SOIC D 8 2500 367.0 367.0 35.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5101ASDX-1/NOPB WSON NGT 8 4500 367.0 367.0 35.0 LM5101ASDX/NOPB WSON DPR 10 4500 367.0 367.0 35.0 LM5101BMAX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LM5101BSD/NOPB WSON DPR 10 1000 210.0 185.0 35.0 LM5101BSDX/NOPB WSON DPR 10 4500 367.0 367.0 35.0 LM5101CMAX/NOPB SOIC D 8 2500 367.0 367.0 35.
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MECHANICAL DATA DGN0008A MUY08A (Rev A) BOTTOM VIEW www.ti.
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MECHANICAL DATA DDA0008B MRA08B (Rev B) www.ti.
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MECHANICAL DATA NGT0008A SDC08A (Rev A) www.ti.
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MECHANICAL DATA DPR0010A SDC10A (Rev A) www.ti.
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