Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - gate drivers Non-inverting Half-bridge WSON 10 (4x4)

LM5113

www.ti.com

SNVS725F –JUNE 2011–REVISED APRIL 2013

LM5113 5A, 100V Half-Bridge Gate Driver for Enhancement Mode GaN FETs

Check for Samples: LM5113

FEATURES

DESCRIPTION

• Independent High-Side and Low-Side TTL

The LM5113 is designed to drive both the high-side

Logic Inputs

and the low-side enhancement mode Gallium Nitride

• 1.2A/5A Peak Source/Sink Current

(GaN) FETs in a synchronous buck or a half bridge

• High-Side Floating Bias Voltage Rail Operates

configuration. The floating high-side driver is capable

up to 100VDC

of driving a high-side enhancement mode GaN FET

operating up to 100V. The high-side bias voltage is

• Internal Bootstrap Supply Voltage Clamping

generated using a bootstrap technique and is

• Split Outputs for Adjustable Turn-on/Turn-off

internally clamped at 5.2V, which prevents the gate

Strength

voltage from exceeding the maximum gate-source

• 0.6Ω /2.1Ω Pull-down/Pull-up Resistance

voltage rating of enhancement mode GaN FETs. The

inputs of the LM5113 are TTL logic compatible, and

• Fast Propagation Times (28ns Typical)

can withstand input voltages up to 14V regardless of

• Excellent Propagation Delay Matching (1.5ns

the VDD voltage. The LM5113 has split gate outputs,

Typical)

providing flexibility to adjust the turn-on and turn-off

• Supply Rail Under-Voltage Lockout strength independently.

• Low Power Consumption

In addition, the strong sink capability of the LM5113

maintains the gate in the low state, preventing

TYPICAL APPLICATIONS

unintended turn-on during switching. The LM5113

can operate up to several MHz. The LM5113 is

• Current Fed Push-Pull converters

available in a standard WSON-10 pin package and a

• Half and Full-Bridge converters

12-bump DSBGA package. The WSON-10 pin

package contains an exposed pad to aid power

• Synchronous Buck converters

dissipation. The DSBGA package offers a compact

• Two-switch Forward converters

footprint and minimized package inductance.

• Forward with Active Clamp converters

PACKAGES

• WSON-10 (4 mm x 4 mm)

• DSBGA (2 mm x 2 mm)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (21 pages)

PAGE 1
LM5113 www.ti.com SNVS725F – JUNE 2011 – REVISED APRIL 2013 LM5113 5A, 100V Half-Bridge Gate Driver for Enhancement Mode GaN FETs Check for Samples: LM5113 FEATURES 1 • 2 • • • • • • • • • Independent High-Side and Low-Side TTL Logic Inputs 1.2A/5A Peak Source/Sink Current High-Side Floating Bias Voltage Rail Operates up to 100VDC Internal Bootstrap Supply Voltage Clamping Split Outputs for Adjustable Turn-on/Turn-off Strength 0.6Ω /2.
PAGE 2
LM5113 SNVS725F – JUNE 2011 – REVISED APRIL 2013 www.ti.com Typical Application HB UVLO & CLAMP HOH LEVEL SHIFT HOL HS HI VDD UVLO LOH LOL LI VSS Figure 1.
PAGE 3
LM5113 www.ti.com SNVS725F – JUNE 2011 – REVISED APRIL 2013 Connection Diagram VDD 1 10 LOH HB 2 9 LOL HOH 3 8 VSS HOL 4 7 LI HS 5 6 HI Exposed Pad Figure 2.
PAGE 4
LM5113 SNVS725F – JUNE 2011 – REVISED APRIL 2013 www.ti.com PIN DESCRIPTIONS (continued) Pin Number Name Description Applications Information DSBGA WSON-10 A2 8 VSS Ground return All signals are referenced to this ground. A1 9 LOL Low-side gate driver sink-current output Connect to the gate of the low-side GaN FET with a short, low inductance path. A gate resistor can be used to adjust the turn-off speed.
PAGE 5
LM5113 www.ti.com SNVS725F – JUNE 2011 – REVISED APRIL 2013 Electrical Characteristics (continued) Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
PAGE 6
LM5113 SNVS725F – JUNE 2011 – REVISED APRIL 2013 www.ti.com Switching Characteristics (continued) Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature (TJ) range of -40°C to +125°C. Minimum and Maximum limits are ensured through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes only.
PAGE 7
LM5113 www.ti.com SNVS725F – JUNE 2011 – REVISED APRIL 2013 Typical Performance Characteristics Peak Source Current vs Output Voltage Peak Sink Current vs Output Voltage Figure 4. Figure 5. IDDO vs Frequency IHBO vs Frequency Figure 6. Figure 7. IDD vs Temperature IHB vs Temperature Figure 8. Figure 9.
PAGE 8
LM5113 SNVS725F – JUNE 2011 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) 8 UVLO Rising Thresholds vs Temperature UVLO Falling Thresholds vs Temperature Figure 10. Figure 11. Input Thresholds vs Temperature Input Threshold Hysteresis vs Temperature Figure 12. Figure 13. Bootstrap Diode Forward Voltage Propagation Delay vs Temperature Figure 14. Figure 15.
PAGE 9
LM5113 www.ti.com SNVS725F – JUNE 2011 – REVISED APRIL 2013 Typical Performance Characteristics (continued) (1) LO&HO Gate Drive — High/Low Level Output Voltage vs Temperature HB Regulation Voltage vs Temperature Figure 16. Figure 17. Note Unless otherwise specified, VDD = VHB = 5V, VSS = VHS = 0V.
PAGE 10
LM5113 SNVS725F – JUNE 2011 – REVISED APRIL 2013 www.ti.com Detailed Operating Description The LM5113 is designed to drive both the high-side and the low-side enhancement mode Gallium Nitride FETs in a synchronous buck or a half-bridge configuration. The outputs of the LM5113 are independently controlled with TTL input thresholds. The inputs of the LM5113 can withstand voltages up to 14V regardless of the VDD voltage, and can be directly connected to the outputs of PWM controllers.
PAGE 11
LM5113 www.ti.com SNVS725F – JUNE 2011 – REVISED APRIL 2013 (3) CLoadH and CLoadL are the high-side and the low-side capacitive loads respectively. It can also be calculated with the total input gate charge of the high-side and the low-side transistors as (4) There are some additional losses in the gate drivers due to the internal CMOS stages used to buffer the LO and HO outputs. The following plot shows the measured gate driver power dissipation versus frequency and load capacitance.
PAGE 12
LM5113 SNVS725F – JUNE 2011 – REVISED APRIL 2013 www.ti.com The Load of High-Side Driver is a GaN FET with Total Gate Charge of 10nC Figure 20. Reverse Recovery Power Loss of Bootstrap Diode VIN=50V The sum of the driver loss and the bootstrap diode loss is the total power loss of the IC.
PAGE 13
LM5113 SNVS725F – JUNE 2011 – REVISED APRIL 2013 Bootstrap Capacitor HO To Hi-Side FET HS To Hi-Side FET 2 3 4 5 VDD 1 HB HS 2 3 4 5 VDD 1 HB HS HO HS HOL Bootstrap Capacitor HOH www.ti.com Bypass Capacitor Bypass Capacitor 9 10 LOL LOH LI To Low-Side FET 8 VSS 7 HI LOH 6 10 LOL LI 9 7 HI 8 VSS 6 LO GND LO To Low-Side FET GND Figure 21. WSON-10 Without Gate Resistors Bootstrap Capacitor HO HS Figure 22.
PAGE 14
LM5113 SNVS725F – JUNE 2011 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision E (April 2013) to Revision F • 14 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
PAGE 15
PACKAGE OPTION ADDENDUM www.ti.
PAGE 16
PACKAGE OPTION ADDENDUM www.ti.com 14-Feb-2014 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
PAGE 17
PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing LM5113SD/NOPB WSON DPR 10 LM5113SDE/NOPB WSON DPR LM5113SDX/NOPB WSON DPR LM5113TME/NOPB DSBGA LM5113TMX/NOPB DSBGA SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 10 250 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 10 4500 330.0 12.4 4.
PAGE 18
PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5113SD/NOPB WSON DPR 10 1000 210.0 185.0 35.0 LM5113SDE/NOPB WSON DPR 10 250 210.0 185.0 35.0 LM5113SDX/NOPB WSON DPR 10 4500 367.0 367.0 35.0 LM5113TME/NOPB DSBGA YFX 12 250 210.0 185.0 35.0 LM5113TMX/NOPB DSBGA YFX 12 3000 210.0 185.0 35.
PAGE 19
MECHANICAL DATA DPR0010A SDC10A (Rev A) www.ti.
PAGE 20
MECHANICAL DATA YFX0012xxx D 0.600 ±0.075 E TOP SIDE OF PACKAGE BOTTOM SIDE OF PACKAGE TMP12XXX (Rev A) D: Max = 1.905 mm, Min =1.845 mm E: Max = 1.756 mm, Min =1.695 mm 4215094/A NOTES: A. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994. B. This drawing is subject to change without notice. www.ti.
PAGE 21
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.