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LM5119/LM5119Q

www.ti.com

SNVS676F –AUGUST 2010–REVISED FEBRUARY 2013

LM5119/LM5119Q Wide Input Range Dual Synchronous Buck Controller

Check for Samples: LM5119/LM5119Q

FEATURES

• Programmable output from 0.8V

• Precision 1.5% voltage reference

• LM5119Q is an Automotive Grade product that

is AEC-Q100 grade 1 qualified (-40°C to 125°C

• Programmable current limit

operating junction temperature)

• Hiccup mode overload protection

• Emulated peak current mode control

• Programmable soft-start

• Wide operating range from 5.5V to 65V

• Programmable line under-voltage lockout

• Easily configurable for dual outputs or

• Automatic switch-over to external bias supply

interleaved single output

• Channel2 enable logic input

• Robust 3.3A peak gate drive

• Thermal Shutdown

• Switching frequency programmable to 750kHz

• Leadless LLP32 (5mm x 5mm) package

• Optional diode emulation mode

DESCRIPTION

The LM5119 is a dual synchronous buck controller intended for step-down regulator applications from a high

voltage or widely varying input supply. The control method is based upon current mode control utilizing an

emulated current ramp. Current mode control provides inherent line feed-forward, cycle-by-cycle current limiting

and ease of loop compensation. The use of an emulated control ramp reduces noise sensitivity of the pulse-width

modulation circuit, allowing reliable control of very small duty cycles necessary in high input voltage applications.

The switching frequency is programmable from 50kHz to 750kHz. The LM5119 drives external high-side and low-

side NMOS power switches with adaptive dead-time control. A user-selectable diode emulation mode enables

discontinuous mode operation for improved efficiency at light load conditions. A high voltage bias regulator with

automatic switch-over to external bias further improves efficiency. Additional features include thermal shutdown,

frequency synchronization, cycle-by-cycle and hiccup mode current limit and adjustable line under-voltage

lockout. The device is available in a power enhanced leadless LLP-32 package featuring an exposed die attach

pad to aid thermal dissipation.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (34 pages)

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LM5119/LM5119Q www.ti.com SNVS676F – AUGUST 2010 – REVISED FEBRUARY 2013 LM5119/LM5119Q Wide Input Range Dual Synchronous Buck Controller Check for Samples: LM5119/LM5119Q FEATURES 1 • 2 • • • • • • LM5119Q is an Automotive Grade product that is AEC-Q100 grade 1 qualified (-40°C to 125°C operating junction temperature) Emulated peak current mode control Wide operating range from 5.5V to 65V Easily configurable for dual outputs or interleaved single output Robust 3.
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LM5119/LM5119Q SNVS676F – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.
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LM5119/LM5119Q www.ti.com SNVS676F – AUGUST 2010 – REVISED FEBRUARY 2013 Pin Functions Pin Descriptions Pin Name Description 1 VCC1 Bias supply pin. Locally decouple to PGND1 using a low ESR/ESL capacitor located as close to controller as possible. 2 LO1 Low side MOSFET gate drive output. Connect to the gate of the channel1 low-side synchronous MOSFET through a short, low inductance path. 3 PGND1 Power ground return pin for low side MOSFET gate driver.
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LM5119/LM5119Q SNVS676F – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com Pin Descriptions (continued) Pin Name 22 PGND2 Description Power ground return pin for low side MOSFET gate driver. Connect directly to the low side of the channel2 current sense resistor. 23 LO2 Low side MOSFET gate drive output. Connect to the gate of the channel2 low-side synchronous MOSFET through a short, low inductance path. 24 VCC2 Bias supply pin.
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LM5119/LM5119Q www.ti.com Operating Ratings SNVS676F – AUGUST 2010 – REVISED FEBRUARY 2013 (1) VIN 5.5V to 65V VCC 5.5V to 14V HB to SW 5.5V to 14V Junction Temperature (1) -40°C to +125°C Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating ratings indicate conditions for which the device is intended to be functional. For specifications and test conditions, see Electrical Characteristics.
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LM5119/LM5119Q SNVS676F – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com Electrical Characteristics Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature range of -40°C to +125°C. Unless otherwise specified, the following conditions apply: VIN = 36V, VCC = 8V, VCCDIS = 0V, EN2 = 5V, RT = 25kΩ, no load on LO and HO. Electrical characteristics are per channel where applicable. See (1), (2), and (3).
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LM5119/LM5119Q www.ti.com SNVS676F – AUGUST 2010 – REVISED FEBRUARY 2013 Electrical Characteristics (continued) Limits in standard type are for TJ = 25°C only; limits in boldface type apply over the junction temperature range of -40°C to +125°C. Unless otherwise specified, the following conditions apply: VIN = 36V, VCC = 8V, VCCDIS = 0V, EN2 = 5V, RT = 25kΩ, no load on LO and HO. Electrical characteristics are per channel where applicable. See (1), (2), and (3).
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LM5119/LM5119Q SNVS676F – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.
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LM5119/LM5119Q www.ti.
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LM5119/LM5119Q SNVS676F – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com BLOCK DIAGRAM COMMON VIN CLK 1 COMMON BIAS GENERATOR RT OSCILLATOR / SYNC DETECTOR CLK 2 BIAS 0.
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LM5119/LM5119Q www.ti.com SNVS676F – AUGUST 2010 – REVISED FEBRUARY 2013 DETAILED OPERATING DESCRIPTION The LM5119 high voltage switching regulator features all of the functions necessary to implement an efficient dual channel buck regulator that operates over a very wide input voltage range. The LM5119 may be configured as two independent regulators or as a single high current regulator with two interleaved channels.
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LM5119/LM5119Q SNVS676F – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com VCC VOUT SW L COUT Figure 3. VCC Bias Supply with Additional Inductor Winding In high voltage applications extra care should be taken to ensure the VIN pin does not exceed the absolute maximum voltage rating of 75V. During line or load transients, voltage ringing on the VIN line that exceeds the Absolute Maximum Rating can damage the IC.
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LM5119/LM5119Q www.ti.com SNVS676F – AUGUST 2010 – REVISED FEBRUARY 2013 The RT pin can be used to synchronize the internal oscillator to an external clock. The internal oscillator can be synchronized by AC coupling a positive edge into the RT pin. The voltage at the RT pin is nominally 1.25V and the voltage at the RT pin must exceed 4V to trip the internal synchronization pulse detector. A 5V amplitude signal and 100pF coupling capacitor are recommended.
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LM5119/LM5119Q SNVS676F – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com inductor current plus some additional slope required for slope compensation. Connecting the RAMP pin resistor to SW provides optimum slope compensation with a RAMP capacitor slope that is proportional to VIN. This “adaptive slope compensation” eliminates the requirement for additional slope compensation circuitry with high output voltage set points and frees the user from additional concerns in this area.
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LM5119/LM5119Q www.ti.com SNVS676F – AUGUST 2010 – REVISED FEBRUARY 2013 CURRENT LIMIT COMPARATOR CURRENT SENSE AMPLIFIER 1.2V CS CLK - RS IL + + A=10 CSG RAMP HO SW RRAMP CRAMP Figure 5. Current Limit and Ramp Circuit Hiccup Mode Current Limiting To further protect the regulator during prolonged current limit conditions, an internal counter counts the PWM clock cycles during which cycle-by-cycle current limiting occurs.
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LM5119/LM5119Q SNVS676F – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com HO and LO Output Drivers The LM5119 contains a high current, high-side driver and associated high voltage level shift to drive the buck switch of each regulator channel. This gate driver circuit works in conjunction with an external diode and bootstrap capacitor. A 0.1µF or larger ceramic capacitor, connected with short traces between the HB pin and SW pin, is recommended.
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LM5119/LM5119Q www.ti.com SNVS676F – AUGUST 2010 – REVISED FEBRUARY 2013 APPLICATION INFORMATION EXTERNAL COMPONENTS The procedure for calculating the external components is illustrated with the following design example. Only the values for the 5V output are calculated since the procedure is the same for the 10V output. The circuit shown in Figure 15 is configured for the following specifications: • CH1 output voltage, VOUT1 = 10.0V • CH2 output voltage, VOUT2 = 5.
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LM5119/LM5119Q SNVS676F – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com The maximum ripple current occurs at the maximum input voltage. Typically, IPP is 20% to 40% of the full load current. When operating in the diode emulation mode configuration, the maximum ripple current should be less than twice the minimum load current. For full synchronous operation, higher ripple current is acceptable.
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LM5119/LM5119Q www.ti.com SNVS676F – AUGUST 2010 – REVISED FEBRUARY 2013 ILIM_PEAK = 0.12 55V x 100 ns + = 12.37A 0.01: 15 PH (18) Where tON(MIN) is the minimum HO on-time which is nominally 100ns. The chosen inductor must be evaluated for this condition, especially at elevated temperature where the saturation current rating of the inductor may drop significantly.
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LM5119/LM5119Q SNVS676F – AUGUST 2010 – REVISED FEBRUARY 2013 IOUT 'VIN = 'VIN = www.ti.com ´ SW x CIN 4x¶ (24) 8A = 0.565V 4 x 230 kHz x 15.4 PF (25) The ripple voltage of the input capacitors will be reduced significantly with dual channel operation since each channel operates 180 degrees out of phase from the other. Capacitors connected in parallel should be evaluated for RMS current rating.
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LM5119/LM5119Q www.ti.com SNVS676F – AUGUST 2010 – REVISED FEBRUARY 2013 SOFT START CAPACITOR The capacitor at the SS pin (CSS) determines the soft-start time (tSS), which is the time for the output voltage to reach the final regulated value. The value of CSS for a given time is determined from: CSS = tSS x 10 PA 0.8V (31) For this application, a value of 0.047μF was chosen for a soft-start time of 3.8ms. RESTART CAPACITOR The restart pin sources 10µA into the external restart capacitor (CRES).
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LM5119/LM5119Q SNVS676F – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com VHYS is the desired UVLO hysteresis at VIN, and VIN in the second equation is the desired UVLO release (turnon) voltage. For example, if it is desired for the LM5119 to be enabled when VIN reaches 13.5V, and the desired hysteresis is 1.2V, then RUV2 should be set to 60kΩ and RUV1 should be set to 6.12kΩ. For this application RUV2 was selected to be 60.4kΩ, RUV1was selected to be 6.19kΩ.
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LM5119/LM5119Q www.ti.com SNVS676F – AUGUST 2010 – REVISED FEBRUARY 2013 MOSFET SNUBBER A resistor-capacitor snubber network across the low-side MOSFET reduces ringing and spikes at the switching node. Excessive ringing and spikes can cause erratic operation and couple noise to the output. Selecting the values for the snubber is best accomplished through empirical methods. First, make sure the lead lengths for the snubber connections are very short. Start with a resistor value between 5 and 50Ω.
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LM5119/LM5119Q SNVS676F – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com / (2π x RCOMP x CCOMP) to be about 1.1kHz. Increasing RCOMP, while proportionally decreasing CCOMP, increases the error amp gain. Conversely, decreasing RCOMP while proportionally increasing CCOMP, decreases the error amp gain. For the design example CCOMP was selected as 6800pF and RCOMP was selected as 36.5kΩ. These values configure the compensation network zero at 640Hz.
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LM5119/LM5119Q www.ti.com SNVS676F – AUGUST 2010 – REVISED FEBRUARY 2013 INTERLEAVED OPERATION Interleaved operation can offer many advantages in single output, high current applications. The output power path is split between two identical channels reducing the current in each channel by one-half. Ripple current reduction in the output capacitors is reduced significantly since each channel operates 180 degrees out of phase from the other.
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LM5119/LM5119Q SNVS676F – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com To configure the LM5119 for interleaved operation, connect COMP1 and COMP2 pins together at the IC. Connecting the FB2 pin to VCC2 pin will disable the channel2 error amplifier with a high output impedance at COMP2. Connect the compensation network between FB1 and the common COMP pins. Connect the two power stages together at the output capacitors.
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LM5119/LM5119Q www.ti.com SNVS676F – AUGUST 2010 – REVISED FEBRUARY 2013 PCB BOARD LAYOUT RECOMMENDATIONS The LM5119 consists of two integrated regulators operating almost independently. Crosstalk between the two regulators under certain conditions may be observed as switch jitter. This effect is common for any dual channel regulator. Cross-talk effects are usually most severe when one channel is operating around 50% duty cycle. Careful layout practices help to minimize this effect.
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LM5119/LM5119Q SNVS676F – AUGUST 2010 – REVISED FEBRUARY 2013 www.ti.com VIN CIN1 CIN2 Loop1 PGND2 CSG1 CS1 COUT2 CSG2 CS2 EP VOUT2 PGND1 COUT1 VOUT1 Loop2 AGND RFB2A RFB1A RFB1B RFB2B The bold lines indicate a solid ground plane. Make the traces to the widest and the shortest and use the star ground technique. These lines indicate the high current paths. Make the traces as wide and short as possible These lines indicate the small signal paths.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing LM5119PSQ/NOPB WQFN RTV 32 LM5119PSQE/NOPB WQFN RTV LM5119PSQX/NOPB WQFN RTV LM5119QPSQ/NOPB WQFN LM5119QPSQX/NOPB WQFN SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 32 250 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 32 4500 330.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5119PSQ/NOPB WQFN RTV 32 1000 213.0 191.0 55.0 LM5119PSQE/NOPB WQFN RTV 32 250 213.0 191.0 55.0 LM5119PSQX/NOPB WQFN RTV 32 4500 367.0 367.0 35.0 LM5119QPSQ/NOPB WQFN RTV 32 1000 213.0 191.0 55.0 LM5119QPSQX/NOPB WQFN RTV 32 4500 367.0 367.0 35.
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MECHANICAL DATA RTV0032A SQA32A (Rev B) www.ti.
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