Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - voltage regulators - DC DC switch controllers HTSSOP 28

4.5V - 36V

SS/ON1

SS/ON2

SYNC

UV_Delay

Vout1

1.3V-0.9V

Vout2

1.3V-0.9V

LM5642/LM5642X

LM5642, LM5642X

www.ti.com

SNVS219K –JUNE 2003–REVISED APRIL 2013

LM5642/LM5642X High Voltage, Dual Synchronous Buck Converter with Oscillator

Synchronization

Check for Samples: LM5642, LM5642X

FEATURES

DESCRIPTION

The LM5642 series consists of two current mode

• Two Synchronous Buck Regulators

synchronous buck regulator controllers operating

• 180° Out of Phase Operation

180° out of phase with each other at a normal

• 200 kHz Fixed Nominal Frequency: LM5642

switching frequency of 200kHz for the LM5642 and at

375kHz for the LM5642X.

• 375 kHz Fixed Nominal Frequency: LM5642X

• Synchronizable Switching Frequency from 150

Out of phase operation reduces the input RMS ripple

current, thereby significantly reducing the required

kHz to 250 kHz for the LM5642 and 200 kHz to

input capacitance. The switching frequency can be

500 kHz for the LM5642X

synchronized to an external clock between 150 kHz

• 4.5V to 36V Input Range

and 250 kHz for the LM5642 and between 200 kHz

• 50 µA Shutdown Current

and 500 kHz for the LM5642X. The two switching

regulator outputs can also be paralleled to operate as

• Adjustable Output from 1.3V to 90% of Vin

a dual-phase, single output regulator.

• 0.04% (Typical) Line and Load Regulation

Accuracy

The output of each channel can be independently

adjusted from 1.3V to 90% of Vin. An internal 5V rail

• Current Mode Control with or without a Sense

is also available externally for driving bootstrap

Resistor

circuitry.

• Independent Enable/Soft-start Pins Allow

Current-mode feedback control assures excellent line

Simple Sequential Startup Configuration.

and load regulation and wide loop bandwidth for

• Configurable for Single Output Parallel

excellent response to fast load transients. Current is

Operation. (See Figure 4)

sensed across either the Vds of the top FET or

• Adjustable Cycle-by-cycle Current Limit

across an external current-sense resistor connected

in series with the drain of the top FET.

• Input Under-voltage Lockout

• Output Over-voltage Latch Protection

The LM5642 features analog soft-start circuitry that is

independent of the output load and output

• Output Under-voltage Protection with Delay

capacitance making the soft-start behavior more

• Thermal Shutdown

predictable and controllable than traditional soft-start

• Self Discharge of Output Capacitors when the

circuits.

Regulator is OFF

Over-voltage protection is available for both outputs.

• TSSOP and HTSSOP (Exposed PAD) Packages

A UV-Delay pin is also available to allow delayed shut

off time for the IC during an output under-voltage

APPLICATIONS

event.

• Embedded Computer Systems

Typical Application Circuit

• Navigation Systems

• Telecom Systems

• Set-Top Boxes

• WebPAD

• Point Of Load Power Architectures

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (40 pages)

PAGE 1
LM5642, LM5642X www.ti.com SNVS219K – JUNE 2003 – REVISED APRIL 2013 LM5642/LM5642X High Voltage, Dual Synchronous Buck Converter with Oscillator Synchronization Check for Samples: LM5642, LM5642X FEATURES DESCRIPTION • • • • • The LM5642 series consists of two current mode synchronous buck regulator controllers operating 180° out of phase with each other at a normal switching frequency of 200kHz for the LM5642 and at 375kHz for the LM5642X.
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LM5642, LM5642X SNVS219K – JUNE 2003 – REVISED APRIL 2013 www.ti.
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LM5642, LM5642X www.ti.com SNVS219K – JUNE 2003 – REVISED APRIL 2013 PIN DESCRIPTIONS (continued) COMP2 (Pin 12) Compensation pin for Channel 2. This is the output of the internal transconductance error amplifier. The loop compensation network should be connected between this pin and the signal ground SGND (Pin 8). ILIM2 (Pin 13) Current limit threshold setting for Channel 2. See ILIM1 (Pin 2). KS2 (Pin 14) The positive (+) Kelvin sense for the internal current sense amplifier of Channel 2.
PAGE 4
LM5642, LM5642X SNVS219K – JUNE 2003 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ABSOLUTE MAXIMUM RATINGS (1) (2) Voltages from the indicated pins to SGND/PGND: VIN, ILIM1, ILIM2, KS1, KS2 −0.3V to 38V SW1, SW2, RSNS1, RSNS2 −0.3 to (VIN + 0.3)V −0.3V to 6V FB1, FB2, VDD1, VDD2 −0.3V to (VLIN5 +0.
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LM5642, LM5642X www.ti.com SNVS219K – JUNE 2003 – REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS Unless otherwise specified, VIN = 28V, GND = PGND = 0V, VLIN5 = VDD1 = VDD2. Limits appearing in boldface type apply over the specified operating junction temperature range, (-40°C to +125°C, if not otherwise specified). Specifications appearing in plain type are measured using low duty cycle pulse testing with TA = 25°C (1), (2). Min/Max limits are specified by design, test, or statistical analysis.
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LM5642, LM5642X SNVS219K – JUNE 2003 – REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Unless otherwise specified, VIN = 28V, GND = PGND = 0V, VLIN5 = VDD1 = VDD2. Limits appearing in boldface type apply over the specified operating junction temperature range, (-40°C to +125°C, if not otherwise specified). Specifications appearing in plain type are measured using low duty cycle pulse testing with TA = 25°C (1), (2).
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LM5642, LM5642X www.ti.com SNVS219K – JUNE 2003 – REVISED APRIL 2013 C3 100 pF C2 10 nF Vin = 24V+10% 22 C1 ILIM1 VIN IC1 LM5642 1 PF KS1 RSNS1 6 C34 SYNC UV_DELAY 100 nF 5 HDRV1 CBOOT1 SW1 220 k: S1 C11 ON/SS1 LDRV1 PGND 10 nF FB1 10 S2 C12 VDD 19 VDD1 VDD2 R27 7 4.7 : C27 C26 3 C19 1 PF 4.7 PF R23 8.45 k: 8.2 nF 12 1 12 k: 28 25 27 R2 100: C6 R7 10 m: C4 100 pF R6 26 C7 Q1 100: D3A BAS40-06 VDD L1 4.
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LM5642, LM5642X SNVS219K – JUNE 2003 – REVISED APRIL 2013 www.ti.com C3 100 pF C2 10 nF Vin = 30Vr 10% 22 VIN C1 1 PF ILIM1 IC1 LM5642 1 KS1 28 R2 100: R1 2 16.9 k: C34 26 HDRV1 100 nF CBOOT1 5 SW1 SYNC R28 220 k: 9 S1 UV_DELAY C11 R6 ON/SS1 22 nF LDRV1 FB1 24 VDD 19 ON/SS2 VDD1 7 C27 C26 1 PF 4.7 PF 3 C19 FB2 ILIM2 VDD2 KS2 R27 4.7: VLIN5 RSNS2 Q2 23 27 nF HDRV2 CBOOT2 R23 SW2 8 SGND Si4850EY L1 Vo = 1.8V, 20A 2.7 PH 4.5 m: Q3 R10 2.
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LM5642, LM5642X www.ti.com SNVS219K – JUNE 2003 – REVISED APRIL 2013 BLOCK DIAGRAM VIN Voltage and Current generator BG SD Disable BG reference Bias Generator Vref Current bias IREF Input Power Supply + + - 5V LDO (Allways ON) VLIN5 From another Ch.
PAGE 10
LM5642, LM5642X SNVS219K – JUNE 2003 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS Softstart Waveforms (No-Load Both Channels) UVP Startup Waveform (VIN = 24V) ON/SS1, 2V/div Vo2, 2V/div Vo1, 1V/div Vo1, 2V/div ON/SS1 and 2, 5V/div, VIN = 36V Vo2, 2V/div Io1, 5A/div Vo1, 2V/div ON/SS1 and 2, 5V/div, VIN = 24V UV DELAY, 2V/div 20ms/DIV 4 ms/DIV Figure 6. Figure 7.
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LM5642, LM5642X www.ti.com SNVS219K – JUNE 2003 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Ch. 2 Load Transient Response (VIN = 36V, Vo2 = 3.3V) Ch.1 Load Transient Response (VIN = 36V, Vo1 = 1.8V) Io2, 2A/DIV Io1, 2A/DIV Vo2, 100mV/DIV Vo1, 100mV/DIV 100Ps/DIV 100Ps/DIV Figure 12. Figure 13. Input Supply Current vs Temperature (Shutdown Mode VIN = 28V) Input Supply Current vs VIN Shutdown Mode (25°C) 55 53.5 53 50 52 45 IQ (PA) IQ (PA) 52.5 40 51.5 51 50.
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LM5642, LM5642X SNVS219K – JUNE 2003 – REVISED APRIL 2013 www.ti.com TYPICAL PERFORMANCE CHARACTERISTICS (continued) Operating Frequency vs Temperature (VIN = 28V) FB Reference Voltage vs Temperature 204 1.2365 202 1.236 200 FREQUENCY (kHz) 1.237 1.2355 VREF (V) 1.235 1.2345 1.234 1.2335 198 196 194 192 190 1.233 188 1.2325 186 1.232 -40 -20 0 25 50 75 100 184 -40 125 -20 o 0 25 50 75 100 125 o TEMPERATURE ( C) TEMPERATURE ( C) Figure 18. Figure 19.
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LM5642, LM5642X www.ti.com SNVS219K – JUNE 2003 – REVISED APRIL 2013 TYPICAL PERFORMANCE CHARACTERISTICS (continued) Efficiency vs Load Current Ch.2 = 3.3V, Ch.1 = Off Efficiency vs Load Current Using Vds Sense Ch.2 = 1.8V, Ch.2 = Off 100 100 VIN = 24V VIN = 24V 90 VIN = 36V 90 EFFICIENCY (%) EFFICIENCY (%) 80 80 70 VIN = 36V 70 60 50 60 40 50 30 0 1 2 3 4 5 0 1 2 3 4 5 6 7 LOAD CURRENT (A) LOAD CURRENT (A) Figure 22. Figure 23. Efficiency vs Load Current Using Vds Sense Ch.
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LM5642, LM5642X SNVS219K – JUNE 2003 – REVISED APRIL 2013 www.ti.com OPERATING DESCRIPTIONS SOFT START The ON/SS1 pin has dual functionality as both channel enable and soft start control. Referring to the soft start block diagram is shown in Figure 25, the LM5642 will remain in shutdown mode while both soft start pins are grounded.
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LM5642, LM5642X www.ti.com SNVS219K – JUNE 2003 – REVISED APRIL 2013 low clamp + - 0.45V COMPx + high clamp SS:0.55V OP:2V Figure 26. Voltage Clamp at COMPx Pin FBx from other CH. OVP 1.13BG OVPx + shutdown latch OVP HDRV: off LDRV:on S Q OVP 1/2 R Q UVP in: 0.84BG out:0.80BG + 5u A UVPx UV_DELAY ONx SS Timeout from other CH. S SD power on reset Q R Q shutdown latch UVP HDRV: off LDRV:off TSD UVLO fault Figure 27.
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LM5642, LM5642X SNVS219K – JUNE 2003 – REVISED APRIL 2013 www.ti.com THERMAL SHUTDOWN The LM5642 IC will enter thermal shutdown if the die temperature exceeds 160°C. The top and bottom FETs of both channels will be turned off immediately. In addition, both soft start capacitors will begin to discharge through separate 5.5 µA current sinks. The voltage on both capacitors will settle to approximately 1.1V, where it will remain until the thermal shutdown condition has cleared.
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LM5642, LM5642X www.ti.com SNVS219K – JUNE 2003 – REVISED APRIL 2013 CBOOTx HDRVx SWx Rsw 4R7 0.1 PF Figure 28. HDRV Series Resistor CURRENT SENSING AND LIMITING As shown in Figure 29, the KSx and RSNSx pins are the inputs of the current sense amplifier. Current sensing is accomplished either by sensing the Vds of the top FET or by sensing the voltage across a current sense resistor connected from VIN to the drain of the top FET.
PAGE 18
LM5642, LM5642X SNVS219K – JUNE 2003 – REVISED APRIL 2013 www.ti.com 10 PA LIMx comp LIMx 13k + - POWER SUPPLY KSx 10 nF 100 + ISENSE amp 20m RSNSx 100 100 pF 100 pF Figure 29. Current Sense and Current Limit Current limit is activated when the inductor current is high enough to cause the voltage at the RSNSx pin to be lower than that of the ILIMx pin. This toggles the Ilim comparator, thus turning off the top FET immediately.
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LM5642, LM5642X www.ti.com SNVS219K – JUNE 2003 – REVISED APRIL 2013 DUAL-PHASE PARALLEL OPERATION In applications with high output current demand, the two switching channels can be configured to operate as a two phase converter to provide a single output voltage with current sharing between the two switching channels. This approach greatly reduces the stress and heat on the output stage components while lowering input ripple current.
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LM5642, LM5642X SNVS219K – JUNE 2003 – REVISED APRIL 2013 www.ti.com FSW = 200 kHz D1 5 Ps 5 Ps D2 2.5 Ps (a) FSW = 150 kHz D1 6.67 Ps 6.67 Ps D2 2.5 Ps (b) FSW = 250 kHz D1 4 Ps 4 Ps D2 2.5 Ps (c) Figure 30. Period Fixed Delay Example Component Selection OUTPUT VOLTAGE SETTING The output voltage for each channel is set by the ratio of a voltage divider as shown in Figure 31. The resistor values can be determined by the following equation: where • Vfb = 1.
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LM5642, LM5642X www.ti.com SNVS219K – JUNE 2003 – REVISED APRIL 2013 Vout R2 FBx R1 GND Figure 31. Output Voltage Setting Example: Vnom = 5V, Vfb = 1.2364V, Ifbmax = 200nA. (8) Choose 60K (9) The Cycle Skip and Dropout modes of the LM5642 series regulate the minimum and maximum output voltage/duty cycle that the converter can deliver. Both modes check the voltage at the COMP pin. Minimum output voltage is determined by the Cycle Skip Comparator.
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LM5642, LM5642X SNVS219K – JUNE 2003 – REVISED APRIL 2013 www.ti.com Output Capacitor Selection In applications that exhibit large, fast load current swings, the slew rate of such a load current transient will likely be beyond the response speed of the regulator. Therefore, to meet voltage transient requirements during worstcase load transients, special consideration should be given to output capacitor selection.
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LM5642, LM5642X www.ti.com SNVS219K – JUNE 2003 – REVISED APRIL 2013 Inductor Selection The size of the output inductor can be determined from the desired output ripple voltage, Vrip, and the impedance of the output capacitors at the switching frequency. The equation to determine the minimum inductance value is as follows: (15) In the above equation, Re is used in place of the impedance of the output capacitors.
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LM5642, LM5642X SNVS219K – JUNE 2003 – REVISED APRIL 2013 www.ti.com The equation for calculating the maximum total input ripple RMS current for duty cycles under 50% is: where • • • • I1 is maximum load current of Channel 1 I2 is the maximum load current of Channel 2 D1 is the duty cycle of Channel 1 D2 is the duty cycle of Channel 2 (21) Example: Imax_1 = 3.6A, Imax_2 = 3.6A, D1 = 0.42, and D2 = 0.275 (22) Choose input capacitors that can handle 1.
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LM5642, LM5642X www.ti.com SNVS219K – JUNE 2003 – REVISED APRIL 2013 MOSFET Selection BOTTOM FET SELECTION During normal operation, the bottom FET is switching on and off at almost zero voltage. Therefore, only conduction losses are present in the bottom FET. The most important parameter when selecting the bottom FET is the on-resistance (RDS-ON). The lower the on-resistance, the lower the power loss. The bottom FET power loss peaks at maximum input voltage and load current.
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LM5642, LM5642X SNVS219K – JUNE 2003 – REVISED APRIL 2013 www.ti.com (28) When using FETs in parallel, the same guidelines apply to the top FET as apply to the bottom FET. Loop Compensation The general purpose of loop compensation is to meet static and dynamic performance requirements while maintaining stability. Loop gain is what is usually checked to determine small-signal performance.
PAGE 27
LM5642, LM5642X www.ti.com SNVS219K – JUNE 2003 – REVISED APRIL 2013 The control-output corner frequencies, and thus the desired compensation corner frequencies, can be determined approximately by the following equations: (29) fP = 1 1 - D - .5 + 2SRO CO 2SfLCO (30) Since fp is determined by the output network, it will shift with loading (Ro). It is best to use a minimum Iout value of approximately 100mA when determining the maximum Ro value.
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LM5642, LM5642X SNVS219K – JUNE 2003 – REVISED APRIL 2013 www.ti.com A second zero can also be added with a resistor in series with Cc2. If used, this zero should be placed at fn, where the control to output gain rolls off at -40dB/dec. Generally, fn will be well below the 0dB level and thus will have little effect on stability. Rc2 can be calculated with the following equation: (39) Vo Vc CC1 RC1 gm R2 CC2 RC2 compensation network R1 Figure 35.
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LM5642, LM5642X www.ti.com SNVS219K – JUNE 2003 – REVISED APRIL 2013 Table 1. Bill Of Materials for Figure 3 24V to 1.8, 3.3V LM5642 ID Part Number Type Size U1 LM5642 Dual Synchronous Controller TSSOP-28 Q1, Q4 Si4850EY N-MOSFET SO-8 Q2, Q5 Si4840DY N-MOSFET SO-8 D3 BAS40-06 Schottky Diode L1 RLF12560T-4R2N100 Inductor L2 RLF12545T-100M5R1 Inductor 12.5x12.5x 4.5mm Parameters Qty Vendor 1 TI 60V 2 Vishay 40V 2 Vishay SOT-23 40V 1 Vishay 12.5x12.5x 6mm 4.
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LM5642, LM5642X SNVS219K – JUNE 2003 – REVISED APRIL 2013 www.ti.com Table 2. Bill of Materials for Figure 4 30V to 1.8V, 20A LM5642 ID Part Number Type Size U1 LM5642 Dual Synchronou s Controller TSSOP-28 Parameters Qty Vendor 1 TI Q1, Q4 Si4850EY N-MOSFET SO-8 60V 2 Vishay Q2, Q3, Q5, Q6 Si4470DY N-MOSFET SO-8 60V 4 Vishay D3 BAS40-06 Schottky Diode SOT-23 40V 1 Vishay L1,L2 RLF12560T-2R7N110 Inductor 12.5x12.5x 6mm 2.7µH,4.5mΩ 11.
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LM5642, LM5642X www.ti.com SNVS219K – JUNE 2003 – REVISED APRIL 2013 Table 3. Bill Of Materials Based on Figure 3 Vin= 9-16V, VO1,2=1.5V,1.8V, 5A LM5642X ID Part Number Type Size U1 LM5642X Dual Synchronous Controller TSSOP-28 Q1, Q4 Si4850EY N-MOSFET SO-8 Q2, Q5 Si4840DY N-MOSFET SO-8 Parameters Qty Vendor 1 TI 60V 2 Vishay 40V 2 Vishay D3 BA54A Schottky Diode SOT-23 30V 1 Vishay L1, L2 RLF12545T-4R2N100 Inductor 12.5x12.5x 4.5mm 4.2µH, 7mΩ 6.
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LM5642, LM5642X SNVS219K – JUNE 2003 – REVISED APRIL 2013 www.ti.com Table 4. Bill Of Materials Based on Figure 3 Vin= 9-16V, VO1,2=3.3V,5V, 5A LM5642X ID Part Number Type Size U1 LM5642X Dual Synchronous Controller TSSOP-28 Q1, Q4 Si4850EY N-MOSFET SO-8 Q2, Q5 Si4840DY N-MOSFET SO-8 Parameters Qty Vendor 1 TI 60V 2 Vishay 40V 2 Vishay D3 BA54A Schottky Diode SOT-23 30V 1 Vishay L1, L2 RLF12545T-5R6N6R1 Inductor 12.5x12.5x 4.5mm 5.6µH, 9mΩ 6.
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LM5642, LM5642X www.ti.com SNVS219K – JUNE 2003 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision J (April 2013) to Revision K • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device LM5642MHX/NOPB Package Package Pins Type Drawing SPQ HTSSOP Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant PWP 28 2500 330.0 16.4 6.8 10.2 1.6 8.0 16.0 Q1 LM5642MTCX TSSOP PW 28 2500 330.0 16.4 6.8 10.2 1.6 8.0 16.0 Q1 LM5642XMHX/NOPB HTSSOP PWP 28 2500 330.0 16.4 6.8 10.2 1.6 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM5642MHX/NOPB HTSSOP PWP 28 2500 367.0 367.0 35.0 LM5642MTCX TSSOP PW 28 2500 367.0 367.0 38.0 LM5642XMHX/NOPB HTSSOP PWP 28 2500 367.0 367.0 35.0 LM5642XMTX/NOPB TSSOP PW 28 2500 367.0 367.0 38.
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MECHANICAL DATA PWP0028A MXA28A (Rev D) www.ti.
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