Datasheet

LM628, LM629
SNVS781C –JUNE 1999–REVISED MARCH 2013 www.ti.com
Bit 3, the index-pulse acquired interrupt flag, is set to logic one when an index pulse has occurred (if command
SIP had been executed) and indicates that the index position register has been updated. The flag is functional
independent of the host interrupt mask status. Bit 3 is cleared by command RSTI.
Bit 2, the trajectory complete interrupt flag, is set to logic one when the trajectory programmed by the LTRJ
command and initiated by the STT command has been completed. Because of overshoot or a limiting condition
(such as commanding the velocity to be higher than the motor can achieve), the motor may not yet be at the final
commanded position. This bit is the logical OR of bits 7 and 10 of the Signals Register, see command RDSIGS
below. The flag functions independently of the host interrupt mask status. Bit 2 is cleared via command RSTI.
Bit 1, the command-error interrupt flag, is set to logic one when the user attempts to read data when a write was
appropriate (or vice versa). The flag is functional independent of the host interrupt mask status. Bit 1 is cleared
via command RSTI.
Bit 0, the busy flag, is frequently tested by the user (via the host computer program) to determine the busy/ready
status prior to writing and reading any data. Such writes and reads may be executed only when bit 0 is logic zero
(not busy). Any command or data writes when the busy bit is high will be ignored. Any data reads when the busy
bit is high will read the current contents of the I/O port buffers, not the data expected by the host. Such reads or
writes (with the busy bit high) will not generate a command-error interrupt.
RDSIGS COMMAND: READ SIGNALS REGISTER
Command Code:0C Hex
Bytes Read:Two
Data Range:See Text
Executable During Motion:Yes
The LM628 internal “signals” register may be read using this command. The first byte read is the more
significant. The less significant byte of this register (with the exception of bit 0) duplicates the status byte. See
Table 8.
Table 8. Signals Register Bit Allocation
Bit Position Function
Bit 15 Host Interrupt
Bit 14 Acceleration Loaded (But Not Updated)
Bit 13 UDF Executed (But Filter Not yet Updated)
Bit 12 Forward Direction
Bit 11 Velocity Mode
Bit 10 On Target
Bit 9 Turn Off upon Excessive Position Error
Bit 8 Eight-Bit Output Mode
Bit 7 Motor Off
Bit 6 Breakpoint Reached [Interrupt]
Bit 5 Excessive Position Error [Interrupt]
Bit 4 Wraparound Occurred [Interrupt]
Bit 3 Index Pulse Acquired [Interrupt]
Bit 2 Trajectory Complete [Interrupt]
Bit 1 Command Error [Interrupt]
Bit 0 Acquire Next Index (SIP Executed)
Bit 15, the host interrupt flag, is set to logic one when the host interrupt output (Pin 17) is logic one. Pin 17 is set
to logic one when any of the six host interrupt conditions occur (if the corresponding interrupt has not been
masked). Bit 15 (and Pin 17) are cleared via command RSTI.
Bit 14, the acceleration-loaded flag, is set to logic one when acceleration data is written to the LM628. Bit 14 is
cleared by the STT command.
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