Datasheet

LM628, LM629
www.ti.com SNVS781C –JUNE 1999–REVISED MARCH 2013
TYPICAL HOST COMPUTER/PROCESSOR INTERFACE
The LM628 is interfaced with the host computer/processor via an 8-bit parallel bus. Figure 13 shows such an
interface and a minimum system configuration.
As shown in Figure 13, the LM628 interfaces with the host data, address and control lines. The address lines are
decoded to generate the LM628 CS input; the host address LSB directly drives the LM628 PS input. Figure 13
also shows an 8-bit DAC and an LM12 Power Op Amp interfaced to the LM628.
LM628 AND HIGH PERFORMANCE CONTROLLER (HPC) INTERFACE
Figure 14 shows the LM628 interfaced to a HPC High Performance Controller. The delay and logic associated
with the WR line is used to effectively increase the write-data hold time of the HPC (as seen at the LM628) by
causing the WR pulse to rise early. Note that the HPC CK2 output provides the clock for the LM628. The
74LS245 is used to decrease the read-data hold time, which is necessary when interfacing to fast host busses.
INTERFACING A 12-BIT DAC
Figure 15 illustrates use of a 12-bit DAC with the LM628. The 74LS378 hex gated-D flip-flop and an inverter
demultiplex the 12-bit output. DAC offset must be adjusted to minimize DAC linearity and monotonicity errors.
Two methods exist for making this adjustment. If the DAC1210 has been socketed, remove it and temporarily
connect a 15 kΩ resistor between Pins 11 and 13 of the DAC socket (Pins 2 and 6 of the LF356) and adjust the
25 kΩ potentiometer for 0V at Pin 6 of the LF356.
If the DAC is not removable, the second method of adjustment requires that the DAC1210 inputs be presented
an all-zeros code. This can be arranged by commanding the appropriate move via the LM628, but with no
feedback from the system encoder. When the all-zeros code is present, adjust the pot for 0V at Pin 6 of the
LF356.
A MONOLITHIC LINEAR DRIVE USING LM12 POWER OP AMP
Figure 16 shows a motor-drive amplifier built using the LM12 Power Operational Amplifier. This circuit is very
simple and can deliver up to 8A at 30V (using the LM12L/LM12CL). Resistors R1 and R2 should be chosen to
set the gain to provide maximum output voltage consistent with maximum input voltage. This example provides a
gain of 2.2, which allows for amplifier output saturation at ±22V with a ±10V input, assuming power supply
voltages of ±30V. The amplifier gain should not be higher than necessary because the system is non-linear when
saturated, and because gain should be controlled by the LM628. The LM12 can also be configured as a current
driver, see 1987 Linear Databook, Vol. 1, p. 2–280.
TYPICAL PWM MOTOR DRIVE INTERFACES
Figure 17 shows an LM18298 dual full-bridge driver interfaced to the LM629 PWM outputs to provide a switch-
mode power amplifier for driving small brush/commutator motors.
Incremental Encoder Interface
The incremental (position feedback) encoder interface consists of three lines: Phase A (Pin 2), Phase B (Pin 3),
and Index (Pin 1). The index pulse output is not available on some encoders. The LM628 will work with both
encoder types, but commands SIP and RDIP will not be meaningful without an index pulse (or alternative input
for this input … be sure to tie Pin 1 high if not used).
Some consideration is merited relative to use in high Gaussian-noise environments. If noise is added to the
encoder inputs (either or both inputs) and is such that it is not sustained until the next encoder transition, the
LM628 decoder logic will reject it. Noise that mimics quadrature counts or persists through encoder transitions
must be eliminated by appropriate EMI design.
Simple digital “filtering” schemes merely reduce susceptibility to noise (there will always be noise pulses longer
than the filter can eliminate). Further, any noise filtering scheme reduces decoder bandwidth. In the LM628 it was
decided (since simple filtering does not eliminate the noise problem) to not include a noise filter in favor of
offering maximum possible decoder bandwidth. Attempting to drive encoder signals too long a distance with
simple TTL lines can also be a source of “noise” in the form of signal degradation (poor risetime and/or ringing).
This can also cause a system to lose positional integrity. Probably the most effective countermeasure to noise
induction can be had by using balanced-line drivers and receivers on the encoder inputs. Figure 18 shows
circuitry using the DS26LS31 and DS26LS32.
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