Datasheet

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LMC6061

www.ti.com

SNOS648D –NOVEMBER 1994–REVISED MARCH 2013

PRECISION CMOS SINGLE MICROPOWER OPERATIONAL AMPLIFIER

Check for Samples: LMC6061

FEATURES

DESCRIPTION

The LMC6061 is a precision single low offset voltage,

(Typical Unless Otherwise Noted)

micropower operational amplifier, capable of

• Low Offset Voltage: 100 µV

precision single supply operation. Performance

• Ultra Low Supply Current: 20 μA

characteristics include ultra low input bias current,

high voltage gain, rail-to-rail output swing, and an

• Operates From 4.5V to 15V Single Supply

input common mode voltage range that includes

• Ultra Low Input Bias Current: 10 fA

ground. These features, plus its low power

• Output Swing Within 10 mV of Supply Rail,

consumption, make the LMC6061 ideally suited for

100k Load

battery powered applications.

• Input Common-mode Range Includes V

−

Other applications using the LMC6061 include

• High Voltage Gain: 140 dB

precision full-wave rectifiers, integrators, references,

sample-and-hold circuits, and true instrumentation

• Improved Latchup Immunity

amplifiers.

APPLICATIONS

This device is built with TI's advanced double-Poly

Silicon-Gate CMOS process.

• Instrumentation Amplifier

For designs that require higher speed, see the

• Photodiode and Infrared Detector Preamplifier

LMC6081 precision single operational amplifier.

• Transducer Amplifiers

For a dual or quad operational amplifier with similar

• Hand-held Analytic Instruments

features, see the LMC6062 or LMC6064 respectively.

• Medical Instrumentation

PATENT PENDING

• D/A Converter

• Charge Amplifier for Piezoelectric Transducers

Connection Diagrams

Figure 1. 8-Pin PDIP/SOIC Figure 2. Distribution of LMC6061 Input Offset

Voltage (T

= +25°C)

Top View

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (21 pages)

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LMC6061 www.ti.com SNOS648D – NOVEMBER 1994 – REVISED MARCH 2013 PRECISION CMOS SINGLE MICROPOWER OPERATIONAL AMPLIFIER Check for Samples: LMC6061 FEATURES 1 (Typical Unless Otherwise Noted) 2 • • • • • • • • Low Offset Voltage: 100 µV Ultra Low Supply Current: 20 μA Operates From 4.
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LMC6061 SNOS648D – NOVEMBER 1994 – REVISED MARCH 2013 www.ti.com Absolute Maximum Ratings (1) (2) (3) Differential Input Voltage ±Supply Voltage (V+) +0.3V, Voltage at Input/Output Pin (V−) −0.3V Supply Voltage (V+ − V−) 16V + See (4) − See (5) Output Short Circuit to V Output Short Circuit to V Lead Temperature (Soldering, 10 sec.) Storage Temp.
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LMC6061 www.ti.com SNOS648D – NOVEMBER 1994 – REVISED MARCH 2013 DC Electrical Characteristics Unless otherwise specified, all limits ensured for TJ = 25°C. Boldface limits apply at the temperature extremes. V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified.
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LMC6061 SNOS648D – NOVEMBER 1994 – REVISED MARCH 2013 www.ti.com DC Electrical Characteristics (continued) Unless otherwise specified, all limits ensured for TJ = 25°C. Boldface limits apply at the temperature extremes. V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified. Symbol VO Output Swing LMC6061AM LMC6061AI LMC6061I Limit (2) Limit (2) Limit (2) 4.990 4.990 4.950 V 4.970 4.980 4.925 Min 0.010 0.010 0.050 V 0.030 0.020 0.075 Max 4.975 4.975 4.
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LMC6061 www.ti.com SNOS648D – NOVEMBER 1994 – REVISED MARCH 2013 AC Electrical Characteristics (continued) Unless otherwise specified, all limits ensured for TJ = 25°C, Boldface limits apply at the temperature extremes. V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified. Symbol T.H.D. Parameter Total Harmonic Distortion Conditions F = 1 kHz, AV = −5 RL = 100 kΩ, VO = 2 VPP ±5V Supply Typ (1) LMC6061AM LMC6061AI LMC6061I Limit (2) Limit (2) Limit (2) Units 0.
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LMC6061 SNOS648D – NOVEMBER 1994 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics VS = ±7.5V, TA = 25°C, Unless otherwise specified 6 Distribution of LMC6061 Input Offset Voltage (TA = +25°C) Distribution of LMC6061 Input Offset Voltage (TA = −55°C) Figure 3. Figure 4. Distribution of LMC6061 Input Offset Voltage (TA = +125°C) Input Bias Current vs Temperature Figure 5. Figure 6. Supply Current vs Supply Voltage Input Voltage vs Output Voltage Figure 7. Figure 8.
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LMC6061 www.ti.com SNOS648D – NOVEMBER 1994 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VS = ±7.5V, TA = 25°C, Unless otherwise specified Common Mode Rejection Ratio vs Frequency Power Supply Rejection Ratio vs Frequency Figure 9. Figure 10. Input Voltage Noise vs Frequency Output Characteristics Sourcing Current Figure 11. Figure 12. Output Characteristics Sinking Current Gain and Phase Response vs Temperature (−55°C to +125°C) Figure 13. Figure 14.
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LMC6061 SNOS648D – NOVEMBER 1994 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) VS = ±7.5V, TA = 25°C, Unless otherwise specified 8 Gain and Phase Response vs Capacitive Load with RL = 20 kΩ Gain and Phase Response vs Capacitive Load with RL = 500 kΩ Figure 15. Figure 16. Open Loop Frequency Response Inverting Small Signal Pulse Response Figure 17. Figure 18. Inverting Large Signal Pulse Response Non-Inverting Small Signal Pulse Response Figure 19. Figure 20.
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LMC6061 www.ti.com SNOS648D – NOVEMBER 1994 – REVISED MARCH 2013 Typical Performance Characteristics (continued) VS = ±7.5V, TA = 25°C, Unless otherwise specified Non-Inverting Large Signal Pulse Response Stability vs Capacitive Load, RL = 20 kΩ Figure 21. Figure 22. Stability vs Capacitive Load RL = 1 MΩ Figure 23.
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LMC6061 SNOS648D – NOVEMBER 1994 – REVISED MARCH 2013 www.ti.com APPLICATIONS HINTS Amplifier Topology The LMC6061 incorporates a novel op-amp design topology that enables it to maintain rail-to-rail output swing even when driving a large load. Instead of relying on a push-pull unity gain output buffer stage, the output stage is taken directly from the internal integrator, which provides both low output impedance and large gain.
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LMC6061 www.ti.com SNOS648D – NOVEMBER 1994 – REVISED MARCH 2013 Figure 25. LMC6061 Noninverting Gain of 10 Amplifier, Compensated to Handle Capacitive Loads In the circuit of Figure 25, R1 and C1 serve to counteract the loss of phase margin by feeding the high frequency component of the output signal back to the amplifier's inverting input, thereby preserving phase margin in the overall feedback loop. Capacitive load driving capability is enhanced by using a pull up resistor to V+ Figure 26.
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LMC6061 SNOS648D – NOVEMBER 1994 – REVISED MARCH 2013 www.ti.com Figure 27. Example of Guard Ring in P.C. Board Layout Inverting Amplifier Non-Inverting Amplifier Follower Figure 28.
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LMC6061 www.ti.com SNOS648D – NOVEMBER 1994 – REVISED MARCH 2013 (Input pins are lifted out of PC board and soldered directly to components. All other pins connected to PC board). Figure 29. Air Wiring Latchup CMOS devices tend to be susceptible to latchup due to their internal parasitic SCR effects. The (I/O) input and output pins look similar to the gate of the SCR. There is a minimum current required to trigger the SCR gate lead.
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LMC6061 SNOS648D – NOVEMBER 1994 – REVISED MARCH 2013 www.ti.com ∴ AV ≈ 100 for circuit shown (R2 = 9.822k). Figure 30. Instrumentation Amplifier Figure 31. Low-Leakage Sample and Hold Figure 32.
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LMC6061 www.ti.com SNOS648D – NOVEMBER 1994 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision C (March 2013) to Revision D • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMC6061AIMX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMC6061AIMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1 LMC6061IMX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMC6061AIMX SOIC D 8 2500 367.0 367.0 35.0 LMC6061AIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0 LMC6061IMX SOIC D 8 2500 367.0 367.0 35.0 LMC6061IMX/NOPB SOIC D 8 2500 367.0 367.0 35.
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