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LMC6064

www.ti.com

SNOS656D –AUGUST 2000–REVISED MARCH 2013

LMC6064 Precision CMOS Quad Micropower Operational Amplifier

Check for Samples: LMC6064

FEATURES

DESCRIPTION

The LMC6064 is a precision quad low offset voltage,

(Typical Unless Otherwise Noted)

micropower operational amplifier, capable of

• Low Offset Voltage: 100 μV

precision single supply operation. Performance

• Ultra Low Supply Current: 16 μA/Amplifier

characteristics include ultra low input bias current,

high voltage gain, rail-to-rail output swing, and an

• Operates from 4.5V to 15V Single Supply

input common mode voltage range that includes

• Ultra Low Input Bias Current: 10 fA

ground. These features, plus its low power

• Output Swing within 10 mV of Supply Rail,

consumption make the LMC6064 ideally suited for

100k Load

battery powered applications.

• Input Common-Mode Range Includes V

−

Other applications using the LMC6064 include

• High Voltage Gain: 140 dB

precision full-wave rectifiers, integrators, references,

sample-and-hold circuits, and true instrumentation

• Improved Latchup Immunity

amplifiers.

APPLICATIONS

This device is built with TI's advanced double-Poly

Silicon-Gate CMOS process.

• Instrumentation Amplifier

For designs that require higher speed, see the

• Photodiode and Infrared Detector Preamplifier

LMC6084 precision quad operational amplifier.

• Transducer Amplifiers

For single or dual operational amplifier with similar

• Hand-Held Analytic Instruments

features, see the LMC6061 or LMC6062 respectively.

• Medical Instrumentation

PATENT PENDING

• D/A Converter

• Charge Amplifier for Piezoelectric Transducers

Connection Diagram

14-Pin PDIP/SOIC

Top View

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (22 pages)

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LMC6064 www.ti.com SNOS656D – AUGUST 2000 – REVISED MARCH 2013 LMC6064 Precision CMOS Quad Micropower Operational Amplifier Check for Samples: LMC6064 FEATURES DESCRIPTION 1 (Typical Unless Otherwise Noted) 2 • • • • • • • • Low Offset Voltage: 100 μV Ultra Low Supply Current: 16 μA/Amplifier Operates from 4.
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LMC6064 SNOS656D – AUGUST 2000 – REVISED MARCH 2013 www.ti.com Low-Leakage Sample and Hold These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) Differential Input Voltage ±Supply Voltage (V+) +0.3V, Voltage at Input/Output Pin (V−) −0.
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LMC6064 www.ti.com SNOS656D – AUGUST 2000 – REVISED MARCH 2013 DC Electrical Characteristics Unless otherwise specified, all limits ensured for TJ = 25°C. Boldface limits apply at the temperature extremes. V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified.
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LMC6064 SNOS656D – AUGUST 2000 – REVISED MARCH 2013 www.ti.com DC Electrical Characteristics (continued) Unless otherwise specified, all limits ensured for TJ = 25°C. Boldface limits apply at the temperature extremes. V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified. Symbol VO Parameter Conditions V+ = 5V Output Swing Typ (1) LMC6064AM LMC6064AI LMC6064I Limit (2) Limit (2) Limit (2) 4.990 4.990 4.950 V 4.970 4.980 4.925 Min 0.010 0.010 0.050 V 0.
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LMC6064 www.ti.com SNOS656D – AUGUST 2000 – REVISED MARCH 2013 AC Electrical Characteristics Unless otherwise specified, all limits ensured for TJ = 25°C, Boldface limits apply at the temperature extremes. V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified.
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LMC6064 SNOS656D – AUGUST 2000 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics 6 Distribution of LMC6064 Input Offset Voltage (TA = +25°C) Distribution of LMC6064 Input Offset Voltage (TA = −55°C) Figure 1. Figure 2. Distribution of LMC6064 Input Offset Voltage (TA = +125°C) Input Bias Current vs Temperature Figure 3. Figure 4. Supply Current vs Supply Voltage Input Voltage vs Output Voltage Figure 5. Figure 6.
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LMC6064 www.ti.com SNOS656D – AUGUST 2000 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Common Mode Rejection Ratio vs Frequency Power Supply Rejection Ratio vs Frequency Figure 7. Figure 8. Input Voltage Noise vs Frequency Output Characteristics Sourcing Current Figure 9. Figure 10. Output Characteristics Sinking Current Gain and Phase Response vs Temperature (−55°C to +125°C) Figure 11. Figure 12.
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LMC6064 SNOS656D – AUGUST 2000 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) 8 Gain and Phase Response vs Capacitive Load with RL = 20 kΩ Gain and Phase Response vs Capacitive Load with RL = 500 kΩ Figure 13. Figure 14. Open Loop Frequency Response Inverting Small Signal Pulse Response Figure 15. Figure 16. Inverting Large Signal Pulse Response Non-Inverting Small Signal Pulse Response Figure 17. Figure 18.
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LMC6064 www.ti.com SNOS656D – AUGUST 2000 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Non-Inverting Large Signal Pulse Response Crosstalk Rejection vs Frequency Figure 19. Figure 20. Stability vs Capacitive Load, RL = 20 kΩ Stability vs Capacitive Load RL = 1 MΩ Figure 21. Figure 22.
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LMC6064 SNOS656D – AUGUST 2000 – REVISED MARCH 2013 www.ti.com APPLICATIONS HINTS AMPLIFIER TOPOLOGY The LMC6064 incorporates a novel op-amp design topology that enables it to maintain rail-to-rail output swing even when driving a large load. Instead of relying on a push-pull unity gain output buffer stage, the output stage is taken directly from the internal integrator, which provides both low output impedance and large gain.
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LMC6064 www.ti.com SNOS656D – AUGUST 2000 – REVISED MARCH 2013 Figure 24. LMC6064 Noninverting Gain of 10 Amplifier, Compensated to Handle Capacitive Loads In the circuit of Figure 24, R1 and C1 serve to counteract the loss of phase margin by feeding the high frequency component of the output signal back to the amplifier's inverting input, thereby preserving phase margin in the overall feedback loop. Capacitive load driving capability is enhanced by using a pull up resistor to V+ (Figure 25).
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LMC6064 SNOS656D – AUGUST 2000 – REVISED MARCH 2013 www.ti.com Figure 26. Example of Guard Ring in P.C. Board Layout Inverting Amplifier Non-Inverting Amplifier Follower Figure 27.
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LMC6064 www.ti.com SNOS656D – AUGUST 2000 – REVISED MARCH 2013 Latchup CMOS devices tend to be susceptible to latchup due to their internal parasitic SCR effects. The (I/O) input and output pins look similar to the gate of the SCR. There is a minimum current required to trigger the SCR gate lead. The LMC6064 and LMC6082 are designed to withstand 100 mA surge current on the I/O pins. Some resistive method should be used to isolate any capacitance from supplying excess current to the I/O pins.
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LMC6064 SNOS656D – AUGUST 2000 – REVISED MARCH 2013 www.ti.com ∴AV ≈ 100 for circuit shown (R2 = 9.822k). Figure 29. Instrumentation Amplifier Figure 30. Low-Leakage Sample and Hold Figure 31.
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LMC6064 www.ti.com SNOS656D – AUGUST 2000 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision C (March 2013) to Revision D • Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com (4) 1-Nov-2013 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMC6064AIMX SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1 LMC6064AIMX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1 LMC6064IMX SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMC6064AIMX SOIC D 14 2500 367.0 367.0 35.0 LMC6064AIMX/NOPB SOIC D 14 2500 367.0 367.0 35.0 LMC6064IMX SOIC D 14 2500 367.0 367.0 35.0 LMC6064IMX/NOPB SOIC D 14 2500 367.0 367.0 35.
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MECHANICAL DATA NFF0014A N0014A N14A (Rev G) www.ti.
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