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LMC6084

www.ti.com

SNOS657D –AUGUST 2000–REVISED MARCH 2013

LMC6084 Precision CMOS Quad Operational Amplifier

Check for Samples: LMC6084

FEATURES

DESCRIPTION

The LMC6084 is a precision quad low offset voltage

(Typical Unless Otherwise Stated)

operational amplifier, capable of single supply

• Low Offset Voltage: 150 μV

operation. Performance characteristics include ultra

• Operates from 4.5V to 15V Single Supply

low input bias current, high voltage gain, rail-to-rail

output swing, and an input common mode voltage

• Ultra Low Input Bias Current: 10 fA

range that includes ground. These features, plus its

• Output Swing to within 20 mV of Supply Rail,

low offset voltage, make the LMC6084 ideally suited

100k Load

for precision circuit applications.

• Input Common-Mode Range Includes V

−

Other applications using the LMC6084 include

• High Voltage Gain: 130 dB

precision full-wave rectifiers, integrators, references,

• Improved Latchup Immunity

and sample-and-hold circuits.

This device is built with National's advanced Double-

APPLICATIONS

Poly Silicon-Gate CMOS process.

• Instrumentation Amplifier

For designs with more critical power demands, see

• Photodiode and Infrared Detector Preamplifier

the LMC6064 precision quad micropower operational

amplifier.

• Transducer Amplifiers

• Medical Instrumentation

For a single or dual operational amplifier with similar

features, see the LMC6081 or LMC6082 respectively.

• D/A Converter

• Charge Amplifier for Piezoelectric Transducers

PATENT PENDING

Connection Diagram

Figure 1. 14-Pin PDIP/SOIC Figure 2. Input Bias Current

Top View vs Temperature

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2All trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (20 pages)

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LMC6084 www.ti.com SNOS657D – AUGUST 2000 – REVISED MARCH 2013 LMC6084 Precision CMOS Quad Operational Amplifier Check for Samples: LMC6084 FEATURES 1 (Typical Unless Otherwise Stated) 2 • • • • • • • Low Offset Voltage: 150 μV Operates from 4.
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LMC6084 SNOS657D – AUGUST 2000 – REVISED MARCH 2013 www.ti.com Absolute Maximum Ratings (1) (2) Differential Input Voltage ±Supply Voltage (V+) +0.3V, (V−) −0.3V Voltage at Input/Output Pin Supply Voltage (V+ − V−) 16V Output Short Circuit to V+ See (3) Output Short Circuit to V− See (4) Lead Temperature (Soldering, 10 Sec.) 260°C Storage Temp.
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LMC6084 www.ti.com SNOS657D – AUGUST 2000 – REVISED MARCH 2013 DC Electrical Characteristics (continued) Unless otherwise specified, all limits guaranteed for TJ = 25°C. Boldface limits apply at the temperature extremes. V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified. Symbol Parameter Conditions RIN Input Resistance CMRR Common Mode 0V ≤ VCM ≤ 12.0V Rejection Ratio V+ = 15V Positive Power Supply 5V ≤ V+ ≤ 15V Rejection Ratio VO = 2.
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LMC6084 SNOS657D – AUGUST 2000 – REVISED MARCH 2013 www.ti.com DC Electrical Characteristics (continued) Unless otherwise specified, all limits guaranteed for TJ = 25°C. Boldface limits apply at the temperature extremes. V+ = 5V, V− = 0V, VCM = 1.5V, VO = 2.5V and RL > 1M unless otherwise specified. Symbol IS Parameter Supply Current Conditions All Four Amplifiers Typ (1) LMC6084AM LMC6084AI LMC6084I Limit (2) Limit (2) Limit (2) 3.0 3.0 3.0 mA 3.6 3.6 3.6 Max 3.4 3.4 3.4 mA 4.0 4.
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LMC6084 www.ti.com SNOS657D – AUGUST 2000 – REVISED MARCH 2013 Typical Performance Characteristics Distribution of LMC6084 Input Offset Voltage (TA = +25°C) Distribution of LMC6084 Input Offset Voltage (TA = −55°C) Figure 3. Figure 4. Distribution of LMC6084 Input Offset Voltage (TA = +125°C) Input Bias Current vs Temperature Figure 5. Figure 6. Supply Current vs Supply Voltage Input Voltage vs Output Voltage Figure 7. Figure 8.
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LMC6084 SNOS657D – AUGUST 2000 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) 6 Common Mode Rejection Ratio vs Frequency Power Supply Rejection Ratio vs Frequency Figure 9. Figure 10. Input Voltage Noise vs Frequency Output Characteristics Sourcing Current Figure 11. Figure 12. Output Characteristics Sinking Current Gain and Phase Response vs Temperature (−55°C to +125°C) Figure 13. Figure 14.
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LMC6084 www.ti.com SNOS657D – AUGUST 2000 – REVISED MARCH 2013 Typical Performance Characteristics (continued) Gain and Phase Response vs Capacitive Load with RL = 600Ω Gain and Phase Response vs Capacitive Load with RL = 500 kΩ Figure 15. Figure 16. Open Loop Frequency Response Inverting Small Signal Pulse Response Figure 17. Figure 18. Inverting Large Signal Pulse Response Non-Inverting Small Signal Pulse Response Figure 19. Figure 20.
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LMC6084 SNOS657D – AUGUST 2000 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) 8 Non-Inverting Large Signal Pulse Response Crosstalk Rejection vs Frequency Figure 21. Figure 22. Stability vs Capacitive Load, RL = 600Ω Stability vs Capacitive Load RL = 1 MΩ Figure 23. Figure 24.
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LMC6084 www.ti.com SNOS657D – AUGUST 2000 – REVISED MARCH 2013 APPLICATIONS HINTS AMPLIFIER TOPOLOGY The LMC6084 incorporates a novel op-amp design topology that enables it to maintain rail-to-rail output swing even when driving a large load. Instead of relying on a push-pull unity gain output buffer stage, the output stage is taken directly from the internal integrator, which provides both low output impedance and large gain.
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LMC6084 SNOS657D – AUGUST 2000 – REVISED MARCH 2013 www.ti.com Figure 26. LMC6084 Noninverting Gain of 10 Amplifier, Compensated to Handle Capacitive Loads In the circuit of Figure 26, R1 and C1 serve to counteract the loss of phase margin by feeding the high frequency component of the output signal back to the amplifier's inverting input, thereby preserving phase margin in the overall feedback loop. Capacitive load driving capability is enhanced by using a pull up resistor to V+ Figure 27.
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LMC6084 www.ti.com SNOS657D – AUGUST 2000 – REVISED MARCH 2013 Figure 28. Example of Guard Ring in P.C. Board Layout Inverting Amplifier Non-Inverting Amplifier Follower Figure 29.
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LMC6084 SNOS657D – AUGUST 2000 – REVISED MARCH 2013 www.ti.com Latchup CMOS devices tend to be susceptible to latchup due to their internal parasitic SCR effects. The (I/O) input and output pins look similar to the gate of the SCR. There is a minimum current required to trigger the SCR gate lead. The LMC6084 is designed to withstand 100 mA surge current on the I/O pins. Some resistive method should be used to isolate any capacitance from supplying excess current to the I/O pins.
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LMC6084 www.ti.com SNOS657D – AUGUST 2000 – REVISED MARCH 2013 ∴AV ≈ 100 for circuit shown (R2 = 9.822k). Figure 31. Instrumentation Amplifier Figure 32. Low-Leakage Sample and Hold Figure 33.
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LMC6084 SNOS657D – AUGUST 2000 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision C (March 2013) to Revision D • 14 Page Changed layout of National Data Sheet to TI format ..........................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMC6084AIMX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1 LMC6084IMX SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1 LMC6084IMX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMC6084AIMX/NOPB SOIC D 14 2500 367.0 367.0 35.0 LMC6084IMX SOIC D 14 2500 367.0 367.0 35.0 LMC6084IMX/NOPB SOIC D 14 2500 367.0 367.0 35.
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